Add new target type: OpenRISC
Add support for OpenRISC target. This implementation supports the adv_debug_sys debug unit core. The mohor dbg_if is not supported. Support for mohor TAP core and Altera Virtual JTAG core are also provided. Change-Id: I3b1cfab1bbb28e497c4fca6ed1bd3a4362609b72 Signed-off-by: Franck Jullien <franck.jullien@gmail.com> Reviewed-on: http://openocd.zylin.com/1547 Tested-by: jenkins Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
This commit is contained in:
Franck Jullien
Spencer Oliver
parent
d19fafc8bd
commit
4e79b48e2c
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@ -1261,6 +1261,7 @@ AC_CONFIG_FILES([
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src/jtag/hla/Makefile
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src/jtag/aice/Makefile
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src/transport/Makefile
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src/target/openrisc/Makefile
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src/xsvf/Makefile
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src/svf/Makefile
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src/target/Makefile
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@ -4179,6 +4179,17 @@ There are several variants defined:
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@code{pxa26x} ... instruction register length is 5 bits
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@item @code{pxa3xx} ... instruction register length is 11 bits
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@end itemize
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@item @code{openrisc} -- this is an OpenRISC 1000 core.
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The current implementation supports two JTAG TAP cores:
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@itemize @minus
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@item @code{OpenCores TAP} (See: @emph{http://opencores.org/project,jtag})
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@item @code{Altera Virtual JTAG TAP} (See: @emph{http://www.altera.com/literature/ug/ug_virtualjtag.pdf})
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@end itemize
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And two debug interfaces cores:
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@itemize @minus
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@item @code{Advanced debug interface} (See: @emph{http://opencores.org/project,adv_debug_sys})
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@item @code{SoC Debug Interface} (See: @emph{http://opencores.org/project,dbg_interface})
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@end itemize
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@end itemize
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@end deffn
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@ -7493,6 +7504,51 @@ the peripherals.
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@xref{targetevents,,Target Events}.
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@end deffn
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@section OpenRISC Architecture
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The OpenRISC CPU is a soft core. It is used in a programmable SoC which can be
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configured with any of the TAP / Debug Unit available.
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@subsection TAP and Debug Unit selection commands
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@deffn Command {tap_select} (@option{vjtag}|@option{mohor})
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Select between the Altera Virtual JTAG and Mohor TAP.
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@end deffn
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@deffn Command {du_select} (@option{adv}|@option{mohor}) [option]
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Select between the Advanced Debug Interface and the classic one.
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An option can be passed as a second argument to the debug unit.
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When using the Advanced Debug Interface, option = 1 means the RTL core is
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configured with ADBG_USE_HISPEED = 1. This configuration skips status checking
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between bytes while doing read or write bursts.
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@end deffn
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@subsection Registers commands
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@deffn Command {addreg} [name] [address] [feature] [reg_group]
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Add a new register in the cpu register list. This register will be
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included in the generated target descriptor file.
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@strong{[feature]} must be "org.gnu.gdb.or1k.group[0..10]".
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@strong{[reg_group]} can be anything. The default register list defines "system",
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"dmmu", "immu", "dcache", "icache", "mac", "debug", "perf", "power", "pic"
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and "timer" groups.
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@emph{example:}
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@example
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addreg rtest 0x1234 org.gnu.gdb.or1k.group0 system
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@end example
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@end deffn
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@deffn Command {readgroup} (@option{group})
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Display all registers in @emph{group}.
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@emph{group} can be "system",
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"dmmu", "immu", "dcache", "icache", "mac", "debug", "perf", "power", "pic",
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"timer" or any new group created with addreg command.
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@end deffn
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@anchor{softwaredebugmessagesandtracing}
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@section Software Debug Messages and Tracing
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@cindex Linux-ARM DCC support
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@ -397,3 +397,24 @@ int hexify(char *hex, const char *bin, int count, int out_maxlen)
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return cmd_len;
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}
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void buffer_shr(void *_buf, unsigned buf_len, unsigned count)
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{
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unsigned i;
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unsigned char *buf = _buf;
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unsigned bytes_to_remove;
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unsigned shift;
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bytes_to_remove = count / 8;
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shift = count - (bytes_to_remove * 8);
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for (i = 0; i < (buf_len - 1); i++)
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buf[i] = (buf[i] >> shift) | ((buf[i+1] << (8 - shift)) & 0xff);
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buf[(buf_len - 1)] = buf[(buf_len - 1)] >> shift;
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if (bytes_to_remove) {
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memmove(buf, &buf[bytes_to_remove], buf_len - bytes_to_remove);
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memset(&buf[buf_len - bytes_to_remove], 0, bytes_to_remove);
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}
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}
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@ -238,5 +238,6 @@ void bit_copy_discard(struct bit_copy_queue *q);
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* used in ti-icdi driver and gdb server */
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int unhexify(char *bin, const char *hex, int count);
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int hexify(char *hex, const char *bin, int count, int out_maxlen);
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void buffer_shr(void *_buf, unsigned buf_len, unsigned count);
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#endif /* BINARYBUFFER_H */
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@ -6,6 +6,9 @@ else
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OOCD_TRACE_FILES =
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endif
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SUBDIRS = openrisc
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libtarget_la_LIBADD = $(top_builddir)/src/target/openrisc/libopenrisc.la
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BIN2C = $(top_builddir)/src/helper/bin2char$(EXEEXT_FOR_BUILD)
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DEBUG_HANDLER = $(srcdir)/xscale/debug_handler.bin
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@ -0,0 +1,15 @@
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include $(top_srcdir)/common.mk
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noinst_LTLIBRARIES = libopenrisc.la
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libopenrisc_la_SOURCES = $(OPENRISC_SRC)
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OPENRISC_SRC = \
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or1k.c \
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or1k_du_adv.c \
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or1k_tap_mohor.c \
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or1k_tap_vjtag.c
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noinst_HEADERS = \
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or1k.h \
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or1k_du.h \
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or1k_tap.h
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File diff suppressed because it is too large
Load Diff
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@ -0,0 +1,159 @@
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/***************************************************************************
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* Copyright (C) 2011 by Julius Baxter *
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* julius@opencores.org *
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* *
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* Copyright (C) 2013 by Marek Czerski *
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* ma.czerski@gmail.com *
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* *
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* Copyright (C) 2013 by Franck Jullien *
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* elec4fun@gmail.com *
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* *
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* *
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* This program is free software; you can redistribute it and/or modify *
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* it under the terms of the GNU General Public License as published by *
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* the Free Software Foundation; either version 2 of the License, or *
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* (at your option) any later version. *
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* *
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* This program is distributed in the hope that it will be useful, *
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* but WITHOUT ANY WARRANTY; without even the implied warranty of *
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
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* GNU General Public License for more details. *
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* *
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* You should have received a copy of the GNU General Public License *
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* along with this program; if not, write to the *
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* Free Software Foundation, Inc., *
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* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
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***************************************************************************/
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#ifndef OR1K_H
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#define OR1K_H
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#ifdef HAVE_CONFIG_H
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#include "config.h"
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#endif
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#include <target/target.h>
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/* SPR groups start address */
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#define GROUP0 (0 << 11)
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#define GROUP1 (1 << 11)
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#define GROUP2 (2 << 11)
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#define GROUP3 (3 << 11)
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#define GROUP4 (4 << 11)
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#define GROUP5 (5 << 11)
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#define GROUP6 (6 << 11)
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#define GROUP7 (7 << 11)
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#define GROUP8 (8 << 11)
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#define GROUP9 (9 << 11)
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#define GROUP10 (10 << 11)
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/* OR1K registers */
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enum or1k_reg_nums {
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OR1K_REG_R0 = 0,
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OR1K_REG_R1,
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OR1K_REG_R2,
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OR1K_REG_R3,
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OR1K_REG_R4,
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OR1K_REG_R5,
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OR1K_REG_R6,
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OR1K_REG_R7,
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OR1K_REG_R8,
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OR1K_REG_R9,
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OR1K_REG_R10,
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OR1K_REG_R11,
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OR1K_REG_R12,
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OR1K_REG_R13,
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OR1K_REG_R14,
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OR1K_REG_R15,
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OR1K_REG_R16,
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OR1K_REG_R17,
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OR1K_REG_R18,
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OR1K_REG_R19,
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OR1K_REG_R20,
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OR1K_REG_R21,
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OR1K_REG_R22,
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OR1K_REG_R23,
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OR1K_REG_R24,
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OR1K_REG_R25,
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OR1K_REG_R26,
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OR1K_REG_R27,
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OR1K_REG_R28,
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OR1K_REG_R29,
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OR1K_REG_R30,
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OR1K_REG_R31,
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OR1K_REG_PPC,
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OR1K_REG_NPC,
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OR1K_REG_SR,
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OR1KNUMCOREREGS
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};
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struct or1k_jtag {
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struct jtag_tap *tap;
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int or1k_jtag_inited;
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int or1k_jtag_module_selected;
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uint8_t *current_reg_idx;
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struct or1k_tap_ip *tap_ip;
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struct or1k_du *du_core;
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};
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struct or1k_common {
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struct or1k_jtag jtag;
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struct reg_cache *core_cache;
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uint32_t core_regs[OR1KNUMCOREREGS];
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int nb_regs;
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struct or1k_core_reg *arch_info;
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};
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static inline struct or1k_common *
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target_to_or1k(struct target *target)
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{
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return (struct or1k_common *)target->arch_info;
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}
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struct or1k_core_reg {
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const char *name;
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uint32_t list_num; /* Index in register cache */
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uint32_t spr_num; /* Number in architecture's SPR space */
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struct target *target;
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struct or1k_common *or1k_common;
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const char *feature; /* feature name in XML tdesc file */
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const char *group; /* register group in XML tdesc file */
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};
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struct or1k_core_reg_init {
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const char *name;
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uint32_t spr_num; /* Number in architecture's SPR space */
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const char *feature; /* feature name in XML tdesc file */
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const char *group; /* register group in XML tdesc file */
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};
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/* ORBIS32 Trap instruction */
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#define OR1K_TRAP_INSTR 0x21000001
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enum or1k_debug_reg_nums {
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OR1K_DEBUG_REG_DMR1 = 0,
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OR1K_DEBUG_REG_DMR2,
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OR1K_DEBUG_REG_DCWR0,
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OR1K_DEBUG_REG_DCWR1,
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OR1K_DEBUG_REG_DSR,
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OR1K_DEBUG_REG_DRR,
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OR1K_DEBUG_REG_NUM
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};
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#define NO_SINGLE_STEP 0
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#define SINGLE_STEP 1
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/* OR1K Debug registers and bits needed for resuming */
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#define OR1K_DEBUG_REG_BASE GROUP6 /* Debug registers Base address */
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#define OR1K_DMR1_CPU_REG_ADD (OR1K_DEBUG_REG_BASE + 16) /* Debug Mode Register 1 0x3010 */
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#define OR1K_DMR1_ST 0x00400000 /* Single-step trace */
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#define OR1K_DMR1_BT 0x00800000 /* Branch trace */
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#define OR1K_DMR2_WGB 0x003ff000 /* Watchpoints generating breakpoint */
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#define OR1K_DSR_TE 0x00002000 /* Trap exception */
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/* OR1K Instruction cache registers needed for invalidating instruction
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* memory during adding and removing breakpoints.
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*/
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#define OR1K_ICBIR_CPU_REG_ADD ((4 << 11) + 2) /* IC Block Invalidate Register 0x2002 */
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#endif
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@ -0,0 +1,77 @@
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/***************************************************************************
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* Copyright (C) 2013 Franck Jullien *
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* elec4fun@gmail.com *
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* *
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* This program is free software; you can redistribute it and/or modify *
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* it under the terms of the GNU General Public License as published by *
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* the Free Software Foundation; either version 2 of the License, or *
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* (at your option) any later version. *
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* *
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* This program is distributed in the hope that it will be useful, *
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* but WITHOUT ANY WARRANTY; without even the implied warranty of *
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
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* GNU General Public License for more details. *
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* *
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* You should have received a copy of the GNU General Public License *
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* along with this program; if not, write to the *
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* Free Software Foundation, Inc., *
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* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
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***************************************************************************/
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#ifndef OR1K_DU
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#define OR1K_DU
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#ifdef HAVE_CONFIG_H
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#include "config.h"
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#endif
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#define CPU_STALL 0
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#define CPU_UNSTALL 1
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#define CPU_RESET 0
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#define CPU_NOT_RESET 1
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int or1k_du_adv_register(void);
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/* Linear list over all available or1k debug unit */
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extern struct list_head du_list;
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struct or1k_du {
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const char *name;
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struct list_head list;
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int options;
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int (*or1k_jtag_init)(struct or1k_jtag *jtag_info);
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int (*or1k_is_cpu_running)(struct or1k_jtag *jtag_info, int *running);
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int (*or1k_cpu_stall)(struct or1k_jtag *jtag_info, int action);
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int (*or1k_cpu_reset)(struct or1k_jtag *jtag_info, int action);
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int (*or1k_jtag_read_cpu)(struct or1k_jtag *jtag_info,
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uint32_t addr, int count, uint32_t *value);
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int (*or1k_jtag_write_cpu)(struct or1k_jtag *jtag_info,
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uint32_t addr, int count, const uint32_t *value);
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int (*or1k_jtag_read_memory)(struct or1k_jtag *jtag_info, uint32_t addr, uint32_t size,
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int count, uint8_t *buffer);
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int (*or1k_jtag_write_memory)(struct or1k_jtag *jtag_info, uint32_t addr, uint32_t size,
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int count, const uint8_t *buffer);
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};
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static inline struct or1k_du *or1k_jtag_to_du(struct or1k_jtag *jtag_info)
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{
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return (struct or1k_du *)jtag_info->du_core;
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}
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static inline struct or1k_du *or1k_to_du(struct or1k_common *or1k)
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{
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struct or1k_jtag *jtag = &or1k->jtag;
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return (struct or1k_du *)jtag->du_core;
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}
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#endif
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@ -0,0 +1,900 @@
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/***************************************************************************
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* Copyright (C) 2013 by Franck Jullien *
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* elec4fun@gmail.com *
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* *
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* Inspired from adv_jtag_bridge which is: *
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* Copyright (C) 2008-2010 Nathan Yawn *
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* nyawn@opencores.net *
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* *
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* And the Mohor interface version of this file which is: *
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* Copyright (C) 2011 by Julius Baxter *
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* julius@opencores.org *
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* *
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* This program is free software; you can redistribute it and/or modify *
|
||||
* it under the terms of the GNU General Public License as published by *
|
||||
* the Free Software Foundation; either version 2 of the License, or *
|
||||
* (at your option) any later version. *
|
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* *
|
||||
* This program is distributed in the hope that it will be useful, *
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of *
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
|
||||
* GNU General Public License for more details. *
|
||||
* *
|
||||
* You should have received a copy of the GNU General Public License *
|
||||
* along with this program; if not, write to the *
|
||||
* Free Software Foundation, Inc., *
|
||||
* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
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***************************************************************************/
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#ifdef HAVE_CONFIG_H
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#include "config.h"
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#endif
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#include "or1k_tap.h"
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#include "or1k.h"
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#include "or1k_du.h"
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#include <target/target.h>
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#include <jtag/jtag.h>
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/* This an option to the adv debug unit.
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* If this is defined, status bits will be skipped on burst
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* reads and writes to improve download speeds.
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* This option must match the RTL configured option.
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*/
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#define ADBG_USE_HISPEED 1
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/* Definitions for the top-level debug unit. This really just consists
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* of a single register, used to select the active debug module ("chain").
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*/
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#define DBG_MODULE_SELECT_REG_SIZE 2
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#define DBG_MAX_MODULES 4
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#define DC_WISHBONE 0
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#define DC_CPU0 1
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#define DC_CPU1 2
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#define DC_JSP 3
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/* CPU control register bits mask */
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#define DBG_CPU_CR_STALL 0x01
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#define DBG_CPU_CR_RESET 0x02
|
||||
|
||||
/* Polynomial for the CRC calculation
|
||||
* Yes, it's backwards. Yes, this is on purpose.
|
||||
* The hardware is designed this way to save on logic and routing,
|
||||
* and it's really all the same to us here.
|
||||
*/
|
||||
#define ADBG_CRC_POLY 0xedb88320
|
||||
|
||||
/* These are for the internal registers in the Wishbone module
|
||||
* The first is the length of the index register,
|
||||
* the indexes of the various registers are defined after that.
|
||||
*/
|
||||
#define DBG_WB_REG_SEL_LEN 1
|
||||
#define DBG_WB_REG_ERROR 0
|
||||
|
||||
/* Opcode definitions for the Wishbone module. */
|
||||
#define DBG_WB_OPCODE_LEN 4
|
||||
#define DBG_WB_CMD_NOP 0x0
|
||||
#define DBG_WB_CMD_BWRITE8 0x1
|
||||
#define DBG_WB_CMD_BWRITE16 0x2
|
||||
#define DBG_WB_CMD_BWRITE32 0x3
|
||||
#define DBG_WB_CMD_BREAD8 0x5
|
||||
#define DBG_WB_CMD_BREAD16 0x6
|
||||
#define DBG_WB_CMD_BREAD32 0x7
|
||||
#define DBG_WB_CMD_IREG_WR 0x9
|
||||
#define DBG_WB_CMD_IREG_SEL 0xd
|
||||
|
||||
/* Internal register definitions for the CPU0 module. */
|
||||
#define DBG_CPU0_REG_SEL_LEN 1
|
||||
#define DBG_CPU0_REG_STATUS 0
|
||||
|
||||
/* Opcode definitions for the first CPU module. */
|
||||
#define DBG_CPU0_OPCODE_LEN 4
|
||||
#define DBG_CPU0_CMD_NOP 0x0
|
||||
#define DBG_CPU0_CMD_BWRITE32 0x3
|
||||
#define DBG_CPU0_CMD_BREAD32 0x7
|
||||
#define DBG_CPU0_CMD_IREG_WR 0x9
|
||||
#define DBG_CPU0_CMD_IREG_SEL 0xd
|
||||
|
||||
/* Internal register definitions for the CPU1 module. */
|
||||
#define DBG_CPU1_REG_SEL_LEN 1
|
||||
#define DBG_CPU1_REG_STATUS 0
|
||||
|
||||
/* Opcode definitions for the second CPU module. */
|
||||
#define DBG_CPU1_OPCODE_LEN 4
|
||||
#define DBG_CPU1_CMD_NOP 0x0
|
||||
#define DBG_CPU1_CMD_BWRITE32 0x3
|
||||
#define DBG_CPU1_CMD_BREAD32 0x7
|
||||
#define DBG_CPU1_CMD_IREG_WR 0x9
|
||||
#define DBG_CPU1_CMD_IREG_SEL 0xd
|
||||
|
||||
#define MAX_READ_STATUS_WAIT 10
|
||||
#define MAX_READ_BUSY_RETRY 2
|
||||
#define MAX_READ_CRC_RETRY 2
|
||||
#define MAX_WRITE_CRC_RETRY 2
|
||||
#define BURST_READ_READY 1
|
||||
#define MAX_BUS_ERRORS 2
|
||||
|
||||
#define MAX_BURST_SIZE (4 * 1024)
|
||||
|
||||
#define STATUS_BYTES 1
|
||||
#define CRC_LEN 4
|
||||
|
||||
static struct or1k_du or1k_du_adv;
|
||||
|
||||
static const char * const chain_name[] = {"WISHBONE", "CPU0", "CPU1", "JSP"};
|
||||
|
||||
static uint32_t adbg_compute_crc(uint32_t crc, uint32_t data_in,
|
||||
int length_bits)
|
||||
{
|
||||
for (int i = 0; i < length_bits; i++) {
|
||||
uint32_t d, c;
|
||||
d = ((data_in >> i) & 0x1) ? 0xffffffff : 0;
|
||||
c = (crc & 0x1) ? 0xffffffff : 0;
|
||||
crc = crc >> 1;
|
||||
crc = crc ^ ((d ^ c) & ADBG_CRC_POLY);
|
||||
}
|
||||
|
||||
return crc;
|
||||
}
|
||||
|
||||
static int find_status_bit(void *_buf, int len)
|
||||
{
|
||||
int i = 0;
|
||||
int count = 0;
|
||||
int ret = -1;
|
||||
uint8_t *buf = _buf;
|
||||
|
||||
while (!(buf[i] & (1 << count++)) && (i < len)) {
|
||||
if (count == 8) {
|
||||
count = 0;
|
||||
i++;
|
||||
}
|
||||
}
|
||||
|
||||
if (i < len)
|
||||
ret = (i * 8) + count;
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int or1k_adv_jtag_init(struct or1k_jtag *jtag_info)
|
||||
{
|
||||
struct or1k_tap_ip *tap_ip = jtag_info->tap_ip;
|
||||
|
||||
int retval = tap_ip->init(jtag_info);
|
||||
if (retval != ERROR_OK) {
|
||||
LOG_ERROR("TAP initialization failed");
|
||||
return retval;
|
||||
}
|
||||
|
||||
/* TAP is now configured to communicate with debug interface */
|
||||
jtag_info->or1k_jtag_inited = 1;
|
||||
|
||||
/* TAP reset - not sure what state debug module chain is in now */
|
||||
jtag_info->or1k_jtag_module_selected = -1;
|
||||
|
||||
jtag_info->current_reg_idx = malloc(DBG_MAX_MODULES * sizeof(uint8_t));
|
||||
memset(jtag_info->current_reg_idx, 0, DBG_MAX_MODULES * sizeof(uint8_t));
|
||||
|
||||
if (or1k_du_adv.options & ADBG_USE_HISPEED)
|
||||
LOG_INFO("adv debug unit is configured with option ADBG_USE_HISPEED");
|
||||
|
||||
LOG_DEBUG("Init done");
|
||||
|
||||
return ERROR_OK;
|
||||
|
||||
}
|
||||
|
||||
/* Selects one of the modules in the debug unit
|
||||
* (e.g. wishbone unit, CPU0, etc.)
|
||||
*/
|
||||
static int adbg_select_module(struct or1k_jtag *jtag_info, int chain)
|
||||
{
|
||||
if (jtag_info->or1k_jtag_module_selected == chain)
|
||||
return ERROR_OK;
|
||||
|
||||
/* MSB of the data out must be set to 1, indicating a module
|
||||
* select command
|
||||
*/
|
||||
uint8_t data = chain | (1 << DBG_MODULE_SELECT_REG_SIZE);
|
||||
|
||||
LOG_DEBUG("Select module: %s", chain_name[chain]);
|
||||
|
||||
struct scan_field field;
|
||||
|
||||
field.num_bits = (DBG_MODULE_SELECT_REG_SIZE + 1);
|
||||
field.out_value = &data;
|
||||
field.in_value = NULL;
|
||||
jtag_add_dr_scan(jtag_info->tap, 1, &field, TAP_IDLE);
|
||||
|
||||
int retval = jtag_execute_queue();
|
||||
if (retval != ERROR_OK)
|
||||
return retval;
|
||||
|
||||
jtag_info->or1k_jtag_module_selected = chain;
|
||||
|
||||
return ERROR_OK;
|
||||
}
|
||||
|
||||
/* Set the index of the desired register in the currently selected module
|
||||
* 1 bit module select command
|
||||
* 4 bits opcode
|
||||
* n bits index
|
||||
*/
|
||||
static int adbg_select_ctrl_reg(struct or1k_jtag *jtag_info, uint8_t regidx)
|
||||
{
|
||||
int index_len;
|
||||
uint32_t opcode;
|
||||
uint32_t opcode_len;
|
||||
|
||||
/* If this reg is already selected, don't do a JTAG transaction */
|
||||
if (jtag_info->current_reg_idx[jtag_info->or1k_jtag_module_selected] == regidx)
|
||||
return ERROR_OK;
|
||||
|
||||
switch (jtag_info->or1k_jtag_module_selected) {
|
||||
case DC_WISHBONE:
|
||||
index_len = DBG_WB_REG_SEL_LEN;
|
||||
opcode = DBG_WB_CMD_IREG_SEL;
|
||||
opcode_len = DBG_WB_OPCODE_LEN;
|
||||
break;
|
||||
case DC_CPU0:
|
||||
index_len = DBG_CPU0_REG_SEL_LEN;
|
||||
opcode = DBG_CPU0_CMD_IREG_SEL;
|
||||
opcode_len = DBG_CPU0_OPCODE_LEN;
|
||||
break;
|
||||
case DC_CPU1:
|
||||
index_len = DBG_CPU1_REG_SEL_LEN;
|
||||
opcode = DBG_CPU1_CMD_IREG_SEL;
|
||||
opcode_len = DBG_CPU1_OPCODE_LEN;
|
||||
break;
|
||||
default:
|
||||
LOG_ERROR("Illegal debug chain selected (%i) while selecting control register",
|
||||
jtag_info->or1k_jtag_module_selected);
|
||||
return ERROR_FAIL;
|
||||
}
|
||||
|
||||
/* MSB must be 0 to access modules */
|
||||
uint32_t data = (opcode & ~(1 << opcode_len)) << index_len;
|
||||
data |= regidx;
|
||||
|
||||
struct scan_field field;
|
||||
|
||||
field.num_bits = (opcode_len + 1) + index_len;
|
||||
field.out_value = (uint8_t *)&data;
|
||||
field.in_value = NULL;
|
||||
jtag_add_dr_scan(jtag_info->tap, 1, &field, TAP_IDLE);
|
||||
|
||||
int retval = jtag_execute_queue();
|
||||
if (retval != ERROR_OK)
|
||||
return retval;
|
||||
|
||||
jtag_info->current_reg_idx[jtag_info->or1k_jtag_module_selected] = regidx;
|
||||
|
||||
return ERROR_OK;
|
||||
}
|
||||
|
||||
/* Write control register (internal to the debug unit) */
|
||||
static int adbg_ctrl_write(struct or1k_jtag *jtag_info, uint8_t regidx,
|
||||
uint32_t *cmd_data, int length_bits)
|
||||
{
|
||||
int index_len;
|
||||
uint32_t opcode;
|
||||
uint32_t opcode_len;
|
||||
|
||||
LOG_DEBUG("Write control register %d: 0x%08x", regidx, cmd_data[0]);
|
||||
|
||||
int retval = adbg_select_ctrl_reg(jtag_info, regidx);
|
||||
if (retval != ERROR_OK) {
|
||||
LOG_ERROR("Error while calling adbg_select_ctrl_reg");
|
||||
return retval;
|
||||
}
|
||||
|
||||
switch (jtag_info->or1k_jtag_module_selected) {
|
||||
case DC_WISHBONE:
|
||||
index_len = DBG_WB_REG_SEL_LEN;
|
||||
opcode = DBG_WB_CMD_IREG_WR;
|
||||
opcode_len = DBG_WB_OPCODE_LEN;
|
||||
break;
|
||||
case DC_CPU0:
|
||||
index_len = DBG_CPU0_REG_SEL_LEN;
|
||||
opcode = DBG_CPU0_CMD_IREG_WR;
|
||||
opcode_len = DBG_CPU0_OPCODE_LEN;
|
||||
break;
|
||||
case DC_CPU1:
|
||||
index_len = DBG_CPU1_REG_SEL_LEN;
|
||||
opcode = DBG_CPU1_CMD_IREG_WR;
|
||||
opcode_len = DBG_CPU1_OPCODE_LEN;
|
||||
break;
|
||||
default:
|
||||
LOG_ERROR("Illegal debug chain selected (%i) while doing control write",
|
||||
jtag_info->or1k_jtag_module_selected);
|
||||
return ERROR_FAIL;
|
||||
}
|
||||
|
||||
struct scan_field field[2];
|
||||
|
||||
/* MSB must be 0 to access modules */
|
||||
uint32_t data = (opcode & ~(1 << opcode_len)) << index_len;
|
||||
data |= regidx;
|
||||
|
||||
field[0].num_bits = length_bits;
|
||||
field[0].out_value = (uint8_t *)cmd_data;
|
||||
field[0].in_value = NULL;
|
||||
|
||||
field[1].num_bits = (opcode_len + 1) + index_len;
|
||||
field[1].out_value = (uint8_t *)&data;
|
||||
field[1].in_value = NULL;
|
||||
|
||||
jtag_add_dr_scan(jtag_info->tap, 2, field, TAP_IDLE);
|
||||
|
||||
return jtag_execute_queue();
|
||||
}
|
||||
|
||||
/* Reads control register (internal to the debug unit) */
|
||||
static int adbg_ctrl_read(struct or1k_jtag *jtag_info, uint32_t regidx,
|
||||
uint32_t *data, int length_bits)
|
||||
{
|
||||
|
||||
int retval = adbg_select_ctrl_reg(jtag_info, regidx);
|
||||
if (retval != ERROR_OK) {
|
||||
LOG_ERROR("Error while calling adbg_select_ctrl_reg");
|
||||
return retval;
|
||||
}
|
||||
|
||||
int opcode_len;
|
||||
uint32_t opcode;
|
||||
|
||||
/* There is no 'read' command, We write a NOP to read */
|
||||
switch (jtag_info->or1k_jtag_module_selected) {
|
||||
case DC_WISHBONE:
|
||||
opcode = DBG_WB_CMD_NOP;
|
||||
opcode_len = DBG_WB_OPCODE_LEN;
|
||||
break;
|
||||
case DC_CPU0:
|
||||
opcode = DBG_CPU0_CMD_NOP;
|
||||
opcode_len = DBG_CPU0_OPCODE_LEN;
|
||||
break;
|
||||
case DC_CPU1:
|
||||
opcode = DBG_CPU1_CMD_NOP;
|
||||
opcode_len = DBG_CPU1_OPCODE_LEN;
|
||||
break;
|
||||
default:
|
||||
LOG_ERROR("Illegal debug chain selected (%i) while doing control read",
|
||||
jtag_info->or1k_jtag_module_selected);
|
||||
return ERROR_FAIL;
|
||||
}
|
||||
|
||||
/* Zero MSB = op for module, not top-level debug unit */
|
||||
uint32_t outdata = opcode & ~(0x1 << opcode_len);
|
||||
|
||||
struct scan_field field[2];
|
||||
|
||||
field[0].num_bits = length_bits;
|
||||
field[0].out_value = NULL;
|
||||
field[0].in_value = (uint8_t *)data;
|
||||
|
||||
field[1].num_bits = opcode_len + 1;
|
||||
field[1].out_value = (uint8_t *)&outdata;
|
||||
field[1].in_value = NULL;
|
||||
|
||||
jtag_add_dr_scan(jtag_info->tap, 2, field, TAP_IDLE);
|
||||
|
||||
return jtag_execute_queue();
|
||||
}
|
||||
|
||||
/* sends out a burst command to the selected module in the debug unit (MSB to LSB):
|
||||
* 1-bit module command
|
||||
* 4-bit opcode
|
||||
* 32-bit address
|
||||
* 16-bit length (of the burst, in words)
|
||||
*/
|
||||
static int adbg_burst_command(struct or1k_jtag *jtag_info, uint32_t opcode,
|
||||
uint32_t address, uint16_t length_words)
|
||||
{
|
||||
uint32_t data[2];
|
||||
|
||||
/* Set up the data */
|
||||
data[0] = length_words | (address << 16);
|
||||
/* MSB must be 0 to access modules */
|
||||
data[1] = ((address >> 16) | ((opcode & 0xf) << 16)) & ~(0x1 << 20);
|
||||
|
||||
struct scan_field field;
|
||||
|
||||
field.num_bits = 53;
|
||||
field.out_value = (uint8_t *)&data[0];
|
||||
field.in_value = NULL;
|
||||
|
||||
jtag_add_dr_scan(jtag_info->tap, 1, &field, TAP_IDLE);
|
||||
|
||||
return jtag_execute_queue();
|
||||
}
|
||||
|
||||
static int adbg_wb_burst_read(struct or1k_jtag *jtag_info, int size,
|
||||
int count, uint32_t start_address, uint8_t *data)
|
||||
{
|
||||
int retry_full_crc = 0;
|
||||
int retry_full_busy = 0;
|
||||
int retval;
|
||||
uint8_t opcode;
|
||||
|
||||
LOG_DEBUG("Doing burst read, word size %d, word count %d, start address 0x%08x",
|
||||
size, count, start_address);
|
||||
|
||||
/* Select the appropriate opcode */
|
||||
switch (jtag_info->or1k_jtag_module_selected) {
|
||||
case DC_WISHBONE:
|
||||
if (size == 1)
|
||||
opcode = DBG_WB_CMD_BREAD8;
|
||||
else if (size == 2)
|
||||
opcode = DBG_WB_CMD_BREAD16;
|
||||
else if (size == 4)
|
||||
opcode = DBG_WB_CMD_BREAD32;
|
||||
else {
|
||||
LOG_WARNING("Tried burst read with invalid word size (%d),"
|
||||
"defaulting to 4-byte words", size);
|
||||
opcode = DBG_WB_CMD_BREAD32;
|
||||
}
|
||||
break;
|
||||
case DC_CPU0:
|
||||
if (size == 4)
|
||||
opcode = DBG_CPU0_CMD_BREAD32;
|
||||
else {
|
||||
LOG_WARNING("Tried burst read with invalid word size (%d),"
|
||||
"defaulting to 4-byte words", size);
|
||||
opcode = DBG_CPU0_CMD_BREAD32;
|
||||
}
|
||||
break;
|
||||
case DC_CPU1:
|
||||
if (size == 4)
|
||||
opcode = DBG_CPU1_CMD_BREAD32;
|
||||
else {
|
||||
LOG_WARNING("Tried burst read with invalid word size (%d),"
|
||||
"defaulting to 4-byte words", size);
|
||||
opcode = DBG_CPU0_CMD_BREAD32;
|
||||
}
|
||||
break;
|
||||
default:
|
||||
LOG_ERROR("Illegal debug chain selected (%i) while doing burst read",
|
||||
jtag_info->or1k_jtag_module_selected);
|
||||
return ERROR_FAIL;
|
||||
}
|
||||
|
||||
int total_size_bytes = count * size;
|
||||
struct scan_field field;
|
||||
uint8_t *in_buffer = malloc(total_size_bytes + CRC_LEN + STATUS_BYTES);
|
||||
|
||||
retry_read_full:
|
||||
|
||||
/* Send the BURST READ command, returns TAP to idle state */
|
||||
retval = adbg_burst_command(jtag_info, opcode, start_address, count);
|
||||
if (retval != ERROR_OK)
|
||||
goto out;
|
||||
|
||||
field.num_bits = (total_size_bytes + CRC_LEN + STATUS_BYTES) * 8;
|
||||
field.out_value = NULL;
|
||||
field.in_value = in_buffer;
|
||||
|
||||
jtag_add_dr_scan(jtag_info->tap, 1, &field, TAP_IDLE);
|
||||
|
||||
retval = jtag_execute_queue();
|
||||
if (retval != ERROR_OK)
|
||||
goto out;
|
||||
|
||||
/* Look for the start bit in the first (STATUS_BYTES * 8) bits */
|
||||
int shift = find_status_bit(in_buffer, STATUS_BYTES);
|
||||
|
||||
/* We expect the status bit to be in the first byte */
|
||||
if (shift < 0) {
|
||||
if (retry_full_busy++ < MAX_READ_BUSY_RETRY) {
|
||||
LOG_WARNING("Burst read timed out");
|
||||
goto retry_read_full;
|
||||
} else {
|
||||
LOG_ERROR("Burst read failed");
|
||||
retval = ERROR_FAIL;
|
||||
goto out;
|
||||
}
|
||||
}
|
||||
|
||||
buffer_shr(in_buffer, total_size_bytes + CRC_LEN + STATUS_BYTES, shift);
|
||||
|
||||
uint32_t crc_read;
|
||||
memcpy(data, in_buffer, total_size_bytes);
|
||||
memcpy(&crc_read, &in_buffer[total_size_bytes], 4);
|
||||
|
||||
uint32_t crc_calc = 0xffffffff;
|
||||
for (int i = 0; i < total_size_bytes; i++)
|
||||
crc_calc = adbg_compute_crc(crc_calc, data[i], 8);
|
||||
|
||||
if (crc_calc != crc_read) {
|
||||
LOG_WARNING("CRC ERROR! Computed 0x%08x, read CRC 0x%08x", crc_calc, crc_read);
|
||||
if (retry_full_crc++ < MAX_READ_CRC_RETRY)
|
||||
goto retry_read_full;
|
||||
else {
|
||||
LOG_ERROR("Burst read failed");
|
||||
retval = ERROR_FAIL;
|
||||
goto out;
|
||||
}
|
||||
} else
|
||||
LOG_DEBUG("CRC OK!");
|
||||
|
||||
/* Now, read the error register, and retry/recompute as necessary */
|
||||
if (jtag_info->or1k_jtag_module_selected == DC_WISHBONE &&
|
||||
!(or1k_du_adv.options & ADBG_USE_HISPEED)) {
|
||||
|
||||
uint32_t err_data[2] = {0, 0};
|
||||
uint32_t addr;
|
||||
int bus_error_retries = 0;
|
||||
|
||||
/* First, just get 1 bit...read address only if necessary */
|
||||
retval = adbg_ctrl_read(jtag_info, DBG_WB_REG_ERROR, err_data, 1);
|
||||
if (retval != ERROR_OK)
|
||||
goto out;
|
||||
|
||||
/* Then we have a problem */
|
||||
if (err_data[0] & 0x1) {
|
||||
|
||||
retval = adbg_ctrl_read(jtag_info, DBG_WB_REG_ERROR, err_data, 33);
|
||||
if (retval != ERROR_OK)
|
||||
goto out;
|
||||
|
||||
addr = (err_data[0] >> 1) | (err_data[1] << 31);
|
||||
LOG_WARNING("WB bus error during burst read, address 0x%08x, retrying!", addr);
|
||||
|
||||
bus_error_retries++;
|
||||
if (bus_error_retries > MAX_BUS_ERRORS) {
|
||||
LOG_ERROR("Max WB bus errors reached during burst read");
|
||||
retval = ERROR_FAIL;
|
||||
goto out;
|
||||
}
|
||||
|
||||
/* Don't call retry_do(), a JTAG reset won't help a WB bus error */
|
||||
/* Write 1 bit, to reset the error register */
|
||||
err_data[0] = 1;
|
||||
retval = adbg_ctrl_write(jtag_info, DBG_WB_REG_ERROR, err_data, 1);
|
||||
if (retval != ERROR_OK)
|
||||
goto out;
|
||||
|
||||
goto retry_read_full;
|
||||
}
|
||||
}
|
||||
|
||||
out:
|
||||
free(in_buffer);
|
||||
|
||||
return retval;
|
||||
}
|
||||
|
||||
/* Set up and execute a burst write to a contiguous set of addresses */
|
||||
static int adbg_wb_burst_write(struct or1k_jtag *jtag_info, const uint8_t *data, int size,
|
||||
int count, unsigned long start_address)
|
||||
{
|
||||
int retry_full_crc = 0;
|
||||
int retval;
|
||||
uint8_t opcode;
|
||||
|
||||
LOG_DEBUG("Doing burst write, word size %d, word count %d,"
|
||||
"start address 0x%08lx", size, count, start_address);
|
||||
|
||||
/* Select the appropriate opcode */
|
||||
switch (jtag_info->or1k_jtag_module_selected) {
|
||||
case DC_WISHBONE:
|
||||
if (size == 1)
|
||||
opcode = DBG_WB_CMD_BWRITE8;
|
||||
else if (size == 2)
|
||||
opcode = DBG_WB_CMD_BWRITE16;
|
||||
else if (size == 4)
|
||||
opcode = DBG_WB_CMD_BWRITE32;
|
||||
else {
|
||||
LOG_DEBUG("Tried WB burst write with invalid word size (%d),"
|
||||
"defaulting to 4-byte words", size);
|
||||
opcode = DBG_WB_CMD_BWRITE32;
|
||||
}
|
||||
break;
|
||||
case DC_CPU0:
|
||||
if (size == 4)
|
||||
opcode = DBG_CPU0_CMD_BWRITE32;
|
||||
else {
|
||||
LOG_DEBUG("Tried CPU0 burst write with invalid word size (%d),"
|
||||
"defaulting to 4-byte words", size);
|
||||
opcode = DBG_CPU0_CMD_BWRITE32;
|
||||
}
|
||||
break;
|
||||
case DC_CPU1:
|
||||
if (size == 4)
|
||||
opcode = DBG_CPU1_CMD_BWRITE32;
|
||||
else {
|
||||
LOG_DEBUG("Tried CPU1 burst write with invalid word size (%d),"
|
||||
"defaulting to 4-byte words", size);
|
||||
opcode = DBG_CPU0_CMD_BWRITE32;
|
||||
}
|
||||
break;
|
||||
default:
|
||||
LOG_ERROR("Illegal debug chain selected (%i) while doing burst write",
|
||||
jtag_info->or1k_jtag_module_selected);
|
||||
return ERROR_FAIL;
|
||||
}
|
||||
|
||||
retry_full_write:
|
||||
|
||||
/* Send the BURST WRITE command, returns TAP to idle state */
|
||||
retval = adbg_burst_command(jtag_info, opcode, start_address, count);
|
||||
if (retval != ERROR_OK)
|
||||
return retval;
|
||||
|
||||
struct scan_field field[3];
|
||||
|
||||
/* Write a start bit so it knows when to start counting */
|
||||
uint8_t value = 1;
|
||||
field[0].num_bits = 1;
|
||||
field[0].out_value = &value;
|
||||
field[0].in_value = NULL;
|
||||
|
||||
uint32_t crc_calc = 0xffffffff;
|
||||
for (int i = 0; i < (count * size); i++)
|
||||
crc_calc = adbg_compute_crc(crc_calc, data[i], 8);
|
||||
|
||||
field[1].num_bits = count * size * 8;
|
||||
field[1].out_value = data;
|
||||
field[1].in_value = NULL;
|
||||
|
||||
field[2].num_bits = 32;
|
||||
field[2].out_value = (uint8_t *)&crc_calc;
|
||||
field[2].in_value = NULL;
|
||||
|
||||
jtag_add_dr_scan(jtag_info->tap, 3, field, TAP_DRSHIFT);
|
||||
|
||||
/* Read the 'CRC match' bit, and go to idle */
|
||||
field[0].num_bits = 1;
|
||||
field[0].out_value = NULL;
|
||||
field[0].in_value = &value;
|
||||
jtag_add_dr_scan(jtag_info->tap, 1, field, TAP_IDLE);
|
||||
|
||||
retval = jtag_execute_queue();
|
||||
if (retval != ERROR_OK)
|
||||
return retval;
|
||||
|
||||
if (!value) {
|
||||
LOG_WARNING("CRC ERROR! match bit after write is %i (computed CRC 0x%08x)", value, crc_calc);
|
||||
if (retry_full_crc++ < MAX_WRITE_CRC_RETRY)
|
||||
goto retry_full_write;
|
||||
else
|
||||
return ERROR_FAIL;
|
||||
} else
|
||||
LOG_DEBUG("CRC OK!\n");
|
||||
|
||||
/* Now, read the error register, and retry/recompute as necessary */
|
||||
if (jtag_info->or1k_jtag_module_selected == DC_WISHBONE &&
|
||||
!(or1k_du_adv.options & ADBG_USE_HISPEED)) {
|
||||
uint32_t addr;
|
||||
int bus_error_retries = 0;
|
||||
uint32_t err_data[2] = {0, 0};
|
||||
|
||||
/* First, just get 1 bit...read address only if necessary */
|
||||
retval = adbg_ctrl_read(jtag_info, DBG_WB_REG_ERROR, err_data, 1);
|
||||
if (retval != ERROR_OK)
|
||||
return retval;
|
||||
|
||||
/* Then we have a problem */
|
||||
if (err_data[0] & 0x1) {
|
||||
|
||||
retval = adbg_ctrl_read(jtag_info, DBG_WB_REG_ERROR, err_data, 33);
|
||||
if (retval != ERROR_OK)
|
||||
return retval;
|
||||
|
||||
addr = (err_data[0] >> 1) | (err_data[1] << 31);
|
||||
LOG_WARNING("WB bus error during burst write, address 0x%08x, retrying!", addr);
|
||||
|
||||
bus_error_retries++;
|
||||
if (bus_error_retries > MAX_BUS_ERRORS) {
|
||||
LOG_ERROR("Max WB bus errors reached during burst read");
|
||||
retval = ERROR_FAIL;
|
||||
return retval;
|
||||
}
|
||||
|
||||
/* Don't call retry_do(), a JTAG reset won't help a WB bus error */
|
||||
/* Write 1 bit, to reset the error register */
|
||||
err_data[0] = 1;
|
||||
retval = adbg_ctrl_write(jtag_info, DBG_WB_REG_ERROR, err_data, 1);
|
||||
if (retval != ERROR_OK)
|
||||
return retval;
|
||||
|
||||
goto retry_full_write;
|
||||
}
|
||||
}
|
||||
|
||||
return ERROR_OK;
|
||||
}
|
||||
|
||||
/* Currently hard set in functions to 32-bits */
|
||||
static int or1k_adv_jtag_read_cpu(struct or1k_jtag *jtag_info,
|
||||
uint32_t addr, int count, uint32_t *value)
|
||||
{
|
||||
if (!jtag_info->or1k_jtag_inited)
|
||||
or1k_adv_jtag_init(jtag_info);
|
||||
|
||||
int retval = adbg_select_module(jtag_info, DC_CPU0);
|
||||
if (retval != ERROR_OK)
|
||||
return retval;
|
||||
|
||||
return adbg_wb_burst_read(jtag_info, 4, count, addr, (uint8_t *)value);
|
||||
}
|
||||
|
||||
static int or1k_adv_jtag_write_cpu(struct or1k_jtag *jtag_info,
|
||||
uint32_t addr, int count, const uint32_t *value)
|
||||
{
|
||||
if (!jtag_info->or1k_jtag_inited)
|
||||
or1k_adv_jtag_init(jtag_info);
|
||||
|
||||
int retval = adbg_select_module(jtag_info, DC_CPU0);
|
||||
if (retval != ERROR_OK)
|
||||
return retval;
|
||||
|
||||
return adbg_wb_burst_write(jtag_info, (uint8_t *)value, 4, count, addr);
|
||||
}
|
||||
|
||||
static int or1k_adv_cpu_stall(struct or1k_jtag *jtag_info, int action)
|
||||
{
|
||||
if (!jtag_info->or1k_jtag_inited)
|
||||
or1k_adv_jtag_init(jtag_info);
|
||||
|
||||
int retval = adbg_select_module(jtag_info, DC_CPU0);
|
||||
if (retval != ERROR_OK)
|
||||
return retval;
|
||||
|
||||
uint32_t cpu_cr;
|
||||
retval = adbg_ctrl_read(jtag_info, DBG_CPU0_REG_STATUS, &cpu_cr, 2);
|
||||
if (retval != ERROR_OK)
|
||||
return retval;
|
||||
|
||||
if (action == CPU_STALL)
|
||||
cpu_cr |= DBG_CPU_CR_STALL;
|
||||
else
|
||||
cpu_cr &= ~DBG_CPU_CR_STALL;
|
||||
|
||||
retval = adbg_select_module(jtag_info, DC_CPU0);
|
||||
if (retval != ERROR_OK)
|
||||
return retval;
|
||||
|
||||
return adbg_ctrl_write(jtag_info, DBG_CPU0_REG_STATUS, &cpu_cr, 2);
|
||||
}
|
||||
|
||||
static int or1k_adv_is_cpu_running(struct or1k_jtag *jtag_info, int *running)
|
||||
{
|
||||
if (!jtag_info->or1k_jtag_inited)
|
||||
or1k_adv_jtag_init(jtag_info);
|
||||
|
||||
int retval = adbg_select_module(jtag_info, DC_CPU0);
|
||||
if (retval != ERROR_OK)
|
||||
return retval;
|
||||
|
||||
uint32_t cpu_cr = 0;
|
||||
retval = adbg_ctrl_read(jtag_info, DBG_CPU0_REG_STATUS, &cpu_cr, 2);
|
||||
if (retval != ERROR_OK)
|
||||
return retval;
|
||||
|
||||
if (cpu_cr & DBG_CPU_CR_STALL)
|
||||
*running = 0;
|
||||
else
|
||||
*running = 1;
|
||||
|
||||
return ERROR_OK;
|
||||
}
|
||||
|
||||
static int or1k_adv_cpu_reset(struct or1k_jtag *jtag_info, int action)
|
||||
{
|
||||
if (!jtag_info->or1k_jtag_inited)
|
||||
or1k_adv_jtag_init(jtag_info);
|
||||
|
||||
int retval = adbg_select_module(jtag_info, DC_CPU0);
|
||||
if (retval != ERROR_OK)
|
||||
return retval;
|
||||
|
||||
uint32_t cpu_cr;
|
||||
retval = adbg_ctrl_read(jtag_info, DBG_CPU0_REG_STATUS, &cpu_cr, 2);
|
||||
if (retval != ERROR_OK)
|
||||
return retval;
|
||||
|
||||
if (action == CPU_RESET)
|
||||
cpu_cr |= DBG_CPU_CR_RESET;
|
||||
else
|
||||
cpu_cr &= ~DBG_CPU_CR_RESET;
|
||||
|
||||
retval = adbg_select_module(jtag_info, DC_CPU0);
|
||||
if (retval != ERROR_OK)
|
||||
return retval;
|
||||
|
||||
return adbg_ctrl_write(jtag_info, DBG_CPU0_REG_STATUS, &cpu_cr, 2);
|
||||
}
|
||||
|
||||
static int or1k_adv_jtag_read_memory(struct or1k_jtag *jtag_info,
|
||||
uint32_t addr, uint32_t size, int count, uint8_t *buffer)
|
||||
{
|
||||
LOG_DEBUG("Reading WB%d at 0x%08x", size * 8, addr);
|
||||
|
||||
if (!jtag_info->or1k_jtag_inited)
|
||||
or1k_adv_jtag_init(jtag_info);
|
||||
|
||||
int retval = adbg_select_module(jtag_info, DC_WISHBONE);
|
||||
if (retval != ERROR_OK)
|
||||
return retval;
|
||||
|
||||
int block_count_left = count;
|
||||
uint32_t block_count_address = addr;
|
||||
uint8_t *block_count_buffer = (uint8_t *)buffer;
|
||||
|
||||
while (block_count_left) {
|
||||
|
||||
int blocks_this_round = (block_count_left > MAX_BURST_SIZE) ?
|
||||
MAX_BURST_SIZE : block_count_left;
|
||||
|
||||
retval = adbg_wb_burst_read(jtag_info, size, blocks_this_round,
|
||||
block_count_address, block_count_buffer);
|
||||
if (retval != ERROR_OK)
|
||||
return retval;
|
||||
|
||||
block_count_left -= blocks_this_round;
|
||||
block_count_address += size * MAX_BURST_SIZE;
|
||||
block_count_buffer += size * MAX_BURST_SIZE;
|
||||
}
|
||||
|
||||
return ERROR_OK;
|
||||
}
|
||||
|
||||
static int or1k_adv_jtag_write_memory(struct or1k_jtag *jtag_info,
|
||||
uint32_t addr, uint32_t size, int count, const uint8_t *buffer)
|
||||
{
|
||||
LOG_DEBUG("Writing WB%d at 0x%08x", size * 8, addr);
|
||||
|
||||
if (!jtag_info->or1k_jtag_inited)
|
||||
or1k_adv_jtag_init(jtag_info);
|
||||
|
||||
int retval = adbg_select_module(jtag_info, DC_WISHBONE);
|
||||
if (retval != ERROR_OK)
|
||||
return retval;
|
||||
|
||||
int block_count_left = count;
|
||||
uint32_t block_count_address = addr;
|
||||
uint8_t *block_count_buffer = (uint8_t *)buffer;
|
||||
|
||||
while (block_count_left) {
|
||||
|
||||
int blocks_this_round = (block_count_left > MAX_BURST_SIZE) ?
|
||||
MAX_BURST_SIZE : block_count_left;
|
||||
|
||||
retval = adbg_wb_burst_write(jtag_info, block_count_buffer,
|
||||
size, blocks_this_round,
|
||||
block_count_address);
|
||||
if (retval != ERROR_OK)
|
||||
return retval;
|
||||
|
||||
block_count_left -= blocks_this_round;
|
||||
block_count_address += size * MAX_BURST_SIZE;
|
||||
block_count_buffer += size * MAX_BURST_SIZE;
|
||||
}
|
||||
|
||||
return ERROR_OK;
|
||||
}
|
||||
|
||||
static struct or1k_du or1k_du_adv = {
|
||||
.name = "adv",
|
||||
.options = ADBG_USE_HISPEED,
|
||||
.or1k_jtag_init = or1k_adv_jtag_init,
|
||||
|
||||
.or1k_is_cpu_running = or1k_adv_is_cpu_running,
|
||||
.or1k_cpu_stall = or1k_adv_cpu_stall,
|
||||
.or1k_cpu_reset = or1k_adv_cpu_reset,
|
||||
|
||||
.or1k_jtag_read_cpu = or1k_adv_jtag_read_cpu,
|
||||
.or1k_jtag_write_cpu = or1k_adv_jtag_write_cpu,
|
||||
|
||||
.or1k_jtag_read_memory = or1k_adv_jtag_read_memory,
|
||||
.or1k_jtag_write_memory = or1k_adv_jtag_write_memory
|
||||
};
|
||||
|
||||
int or1k_du_adv_register(void)
|
||||
{
|
||||
list_add_tail(&or1k_du_adv.list, &du_list);
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -0,0 +1,43 @@
|
|||
/***************************************************************************
|
||||
* Copyright (C) 2012 by Franck Jullien *
|
||||
* elec4fun@gmail.com *
|
||||
* *
|
||||
* This program is free software; you can redistribute it and/or modify *
|
||||
* it under the terms of the GNU General Public License as published by *
|
||||
* the Free Software Foundation; either version 2 of the License, or *
|
||||
* (at your option) any later version. *
|
||||
* *
|
||||
* This program is distributed in the hope that it will be useful, *
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of *
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
|
||||
* GNU General Public License for more details. *
|
||||
* *
|
||||
* You should have received a copy of the GNU General Public License *
|
||||
* along with this program; if not, write to the *
|
||||
* Free Software Foundation, Inc., *
|
||||
* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
|
||||
***************************************************************************/
|
||||
|
||||
#ifndef _OR1K_TAP_H_
|
||||
#define _OR1K_TAP_H_
|
||||
|
||||
#ifdef HAVE_CONFIG_H
|
||||
#include "config.h"
|
||||
#endif
|
||||
|
||||
#include <helper/list.h>
|
||||
#include "or1k.h"
|
||||
|
||||
int or1k_tap_vjtag_register(void);
|
||||
int or1k_tap_mohor_register(void);
|
||||
|
||||
/* Linear list over all available or1k taps */
|
||||
extern struct list_head tap_list;
|
||||
|
||||
struct or1k_tap_ip {
|
||||
struct list_head list;
|
||||
int (*init)(struct or1k_jtag *jtag_info);
|
||||
const char *name;
|
||||
};
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,65 @@
|
|||
/***************************************************************************
|
||||
* Copyright (C) 2013 by Franck Jullien *
|
||||
* elec4fun@gmail.com *
|
||||
* *
|
||||
* This program is free software; you can redistribute it and/or modify *
|
||||
* it under the terms of the GNU General Public License as published by *
|
||||
* the Free Software Foundation; either version 2 of the License, or *
|
||||
* (at your option) any later version. *
|
||||
* *
|
||||
* This program is distributed in the hope that it will be useful, *
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of *
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
|
||||
* GNU General Public License for more details. *
|
||||
* *
|
||||
* You should have received a copy of the GNU General Public License *
|
||||
* along with this program; if not, write to the *
|
||||
* Free Software Foundation, Inc., *
|
||||
* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
|
||||
***************************************************************************/
|
||||
|
||||
#ifdef HAVE_CONFIG_H
|
||||
#include "config.h"
|
||||
#endif
|
||||
|
||||
#include "or1k_tap.h"
|
||||
#include "or1k.h"
|
||||
|
||||
#include <jtag/jtag.h>
|
||||
|
||||
#define OR1K_TAP_INST_DEBUG 0x8
|
||||
|
||||
static int or1k_tap_mohor_init(struct or1k_jtag *jtag_info)
|
||||
{
|
||||
LOG_DEBUG("Initialising OpenCores JTAG TAP");
|
||||
|
||||
/* Put TAP into state where it can talk to the debug interface
|
||||
* by shifting in correct value to IR.
|
||||
*/
|
||||
|
||||
/* Ensure TAP is reset - maybe not necessary*/
|
||||
jtag_add_tlr();
|
||||
|
||||
struct jtag_tap *tap = jtag_info->tap;
|
||||
struct scan_field field;
|
||||
uint8_t ir_value = OR1K_TAP_INST_DEBUG;
|
||||
|
||||
field.num_bits = tap->ir_length;
|
||||
field.out_value = &ir_value;
|
||||
field.in_value = NULL;
|
||||
|
||||
jtag_add_ir_scan(tap, &field, TAP_IDLE);
|
||||
|
||||
return jtag_execute_queue();
|
||||
}
|
||||
|
||||
static struct or1k_tap_ip mohor_tap = {
|
||||
.name = "mohor",
|
||||
.init = or1k_tap_mohor_init,
|
||||
};
|
||||
|
||||
int or1k_tap_mohor_register(void)
|
||||
{
|
||||
list_add_tail(&mohor_tap.list, &tap_list);
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -0,0 +1,310 @@
|
|||
/***************************************************************************
|
||||
* Copyright (C) 2013 by Franck Jullien *
|
||||
* elec4fun@gmail.com *
|
||||
* *
|
||||
* This program is free software; you can redistribute it and/or modify *
|
||||
* it under the terms of the GNU General Public License as published by *
|
||||
* the Free Software Foundation; either version 2 of the License, or *
|
||||
* (at your option) any later version. *
|
||||
* *
|
||||
* This program is distributed in the hope that it will be useful, *
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of *
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
|
||||
* GNU General Public License for more details. *
|
||||
* *
|
||||
* You should have received a copy of the GNU General Public License *
|
||||
* along with this program; if not, write to the *
|
||||
* Free Software Foundation, Inc., *
|
||||
* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
|
||||
***************************************************************************/
|
||||
|
||||
#ifdef HAVE_CONFIG_H
|
||||
#include "config.h"
|
||||
#endif
|
||||
|
||||
#include "or1k_tap.h"
|
||||
#include "or1k.h"
|
||||
|
||||
#include <jtag/jtag.h>
|
||||
|
||||
/* Contains constants relevant to the Altera Virtual JTAG
|
||||
* device, which are not included in the BSDL.
|
||||
* As of this writing, these are constant across every
|
||||
* device which supports virtual JTAG.
|
||||
*/
|
||||
|
||||
/* These are commands for the FPGA's IR. */
|
||||
#define ALTERA_CYCLONE_CMD_USER1 0x0E
|
||||
#define ALTERA_CYCLONE_CMD_USER0 0x0C
|
||||
|
||||
/* These defines are for the virtual IR (not the FPGA's)
|
||||
* The virtual TAP was defined in hardware to match the OpenCores native
|
||||
* TAP in both IR size and DEBUG command.
|
||||
*/
|
||||
#define ALT_VJTAG_IR_SIZE 4
|
||||
#define ALT_VJTAG_CMD_DEBUG 0x8
|
||||
|
||||
/* SLD node ID. */
|
||||
#define JTAG_TO_AVALON_NODE_ID 0x84
|
||||
#define VJTAG_NODE_ID 0x08
|
||||
#define SIGNAL_TAP_NODE_ID 0x00
|
||||
#define SERIAL_FLASH_LOADER_NODE_ID 0x04
|
||||
|
||||
#define VER(x) ((x >> 27) & 0x1f)
|
||||
#define NB_NODES(x) ((x >> 19) & 0xff)
|
||||
#define ID(x) ((x >> 19) & 0xff)
|
||||
#define MANUF(x) ((x >> 8) & 0x7ff)
|
||||
#define M_WIDTH(x) ((x >> 0) & 0xff)
|
||||
#define INST_ID(x) ((x >> 0) & 0xff)
|
||||
|
||||
/* tap instructions - Mohor JTAG TAP */
|
||||
#define OR1K_TAP_INST_IDCODE 0x2
|
||||
#define OR1K_TAP_INST_DEBUG 0x8
|
||||
|
||||
static char *id_to_string(unsigned char id)
|
||||
{
|
||||
switch (id) {
|
||||
case VJTAG_NODE_ID:
|
||||
return "Virtual JTAG";
|
||||
case JTAG_TO_AVALON_NODE_ID:
|
||||
return "JTAG to avalon bridge";
|
||||
case SIGNAL_TAP_NODE_ID:
|
||||
return "Signal TAP";
|
||||
case SERIAL_FLASH_LOADER_NODE_ID:
|
||||
return "Serial Flash Loader";
|
||||
}
|
||||
return "unknown";
|
||||
}
|
||||
|
||||
static unsigned char guess_addr_width(unsigned char number_of_nodes)
|
||||
{
|
||||
unsigned char width = 0;
|
||||
|
||||
while (number_of_nodes) {
|
||||
number_of_nodes >>= 1;
|
||||
width++;
|
||||
}
|
||||
|
||||
return width;
|
||||
}
|
||||
|
||||
static int or1k_tap_vjtag_init(struct or1k_jtag *jtag_info)
|
||||
{
|
||||
LOG_DEBUG("Initialising Altera Virtual JTAG TAP");
|
||||
|
||||
/* Put TAP into state where it can talk to the debug interface
|
||||
* by shifting in correct value to IR.
|
||||
*/
|
||||
|
||||
/* Ensure TAP is reset - maybe not necessary*/
|
||||
jtag_add_tlr();
|
||||
|
||||
/* You can use a custom JTAG controller to discover transactions
|
||||
* necessary to enumerate all Virtual JTAG megafunction instances
|
||||
* from your design atruntime. All SLD nodes and the virtual JTAG
|
||||
* registers that they contain are targeted by two Instruction Register
|
||||
* values, USER0 and USER1.
|
||||
*
|
||||
* The USER1 instruction targets the virtual IR of either the sld_hub
|
||||
* or a SLD node. That is,when the USER1 instruction is issued to
|
||||
* the device, the subsequent DR scans target a specific virtual
|
||||
* IR chain based on an address field contained within the DR scan.
|
||||
* The table below shows how the virtual IR, the DR target of the
|
||||
* USER1 instruction is interpreted.
|
||||
*
|
||||
* The VIR_VALUE in the table below is the virtual IR value for the
|
||||
* target SLD node. The width of this field is m bits in length,
|
||||
* where m is the length of the largest VIR for all of the SLD nodes
|
||||
* in the design. All SLD nodes with VIR lengths of fewer than m
|
||||
* bits must pad VIR_VALUE with zeros up to a length of m.
|
||||
*
|
||||
* -------------------------------+-------------------------------
|
||||
* m + n - 1 m | m -1 0
|
||||
* -------------------------------+-------------------------------
|
||||
* ADDR [(n – 1)..0] | VIR_VALUE [(m – 1)..0]
|
||||
* -------------------------------+-------------------------------
|
||||
*
|
||||
* The ADDR bits act as address values to signal the active SLD node
|
||||
* that the virtual IR shift targets. ADDR is n bits in length, where
|
||||
* n bits must be long enough to encode all SLD nodes within the design,
|
||||
* as shown below.
|
||||
*
|
||||
* n = CEIL(log2(Number of SLD_nodes +1))
|
||||
*
|
||||
* The SLD hub is always 0 in the address map.
|
||||
*
|
||||
* Discovery and enumeration of the SLD instances within a design
|
||||
* requires interrogation of the sld_hub to determine the dimensions
|
||||
* of the USER1 DR (m and n) and associating each SLD instance, specifically
|
||||
* the Virtual JTAG megafunction instances, with an address value
|
||||
* contained within the ADDR bits of the USER1 DR.
|
||||
*
|
||||
* The SLD hub contains the HUB IP Configuration Register and SLD_NODE_INFO
|
||||
* register for each SLD node in the design. The HUB IP configuration register provides
|
||||
* information needed to determine the dimensions of the USER1 DR chain. The
|
||||
* SLD_NODE_INFO register is used to determine the address mapping for Virtual
|
||||
* JTAG instance in your design. This register set is shifted out by issuing the
|
||||
* HUB_INFO instruction. Both the ADDR bits for the SLD hub and the HUB_INFO
|
||||
* instruction is 0 × 0.
|
||||
* Because m and n are unknown at this point, the DR register
|
||||
* (ADDR bits + VIR_VALUE) must be filled with zeros. Shifting a sequence of 64 zeroes
|
||||
* into the USER1 DR is sufficient to cover the most conservative case for m and n.
|
||||
*/
|
||||
|
||||
uint8_t t[4];
|
||||
struct scan_field field;
|
||||
struct jtag_tap *tap = jtag_info->tap;
|
||||
|
||||
/* Select VIR */
|
||||
buf_set_u32(t, 0, tap->ir_length, ALTERA_CYCLONE_CMD_USER1);
|
||||
field.num_bits = tap->ir_length;
|
||||
field.out_value = t;
|
||||
field.in_value = NULL;
|
||||
jtag_add_ir_scan(tap, &field, TAP_IDLE);
|
||||
|
||||
/* Select the SLD Hub */
|
||||
field.num_bits = 64;
|
||||
field.out_value = NULL;
|
||||
field.in_value = NULL;
|
||||
jtag_add_dr_scan(tap, 1, &field, TAP_IDLE);
|
||||
|
||||
/* HUB IP Configuration Register
|
||||
*
|
||||
* When the USER1 and HUB_INFO instruction sequence is issued, the
|
||||
* USER0 instruction must be applied to enable the target register
|
||||
* of the HUB_INFO instruction. The HUB IP configuration register
|
||||
* is shifted out using eight four-bit nibble scans of the DR register.
|
||||
* Each four-bit scan must pass through the UPDATE_DR state before
|
||||
* the next four-bit scan. The 8 scans are assembled into a 32-bit
|
||||
* value with the definitions shown in the table below.
|
||||
*
|
||||
* --------------------------------------------------------------------------------
|
||||
* NIBBLE7 | NIBBLE6 | NIBBLE5 | NIBBLE4 | NIBBLE3 | NIBBLE2 | NIBBLE1 | NIBBLE0
|
||||
* ----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+-----
|
||||
* | | | | | | | | | | | | | | |
|
||||
* ----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+-----
|
||||
* HUB IP version| N | ALTERA_MFG_ID (0x06E) | SUM (m, n)
|
||||
* --------------+-------------------+------------------------+--------------------
|
||||
*/
|
||||
|
||||
/* Select VDR */
|
||||
buf_set_u32(t, 0, tap->ir_length, ALTERA_CYCLONE_CMD_USER0);
|
||||
field.num_bits = tap->ir_length;
|
||||
field.out_value = t;
|
||||
field.in_value = NULL;
|
||||
jtag_add_ir_scan(tap, &field, TAP_IDLE);
|
||||
|
||||
int retval = jtag_execute_queue();
|
||||
if (retval != ERROR_OK)
|
||||
return retval;
|
||||
|
||||
uint8_t nibble;
|
||||
uint32_t hub_info = 0;
|
||||
|
||||
for (int i = 0; i < 8; i++) {
|
||||
field.num_bits = 4;
|
||||
field.out_value = NULL;
|
||||
field.in_value = &nibble;
|
||||
jtag_add_dr_scan(tap, 1, &field, TAP_IDLE);
|
||||
retval = jtag_execute_queue();
|
||||
if (retval != ERROR_OK)
|
||||
return retval;
|
||||
hub_info = ((hub_info >> 4) | ((nibble & 0xf) << 28));
|
||||
}
|
||||
|
||||
int nb_nodes = NB_NODES(hub_info);
|
||||
int m_width = M_WIDTH(hub_info);
|
||||
|
||||
LOG_DEBUG("SLD HUB Configuration register");
|
||||
LOG_DEBUG("------------------------------");
|
||||
LOG_DEBUG("m_width = %d", m_width);
|
||||
LOG_DEBUG("manufacturer_id = 0x%02x", MANUF(hub_info));
|
||||
LOG_DEBUG("nb_of_node = %d", nb_nodes);
|
||||
LOG_DEBUG("version = %d", VER(hub_info));
|
||||
LOG_DEBUG("VIR length = %d", guess_addr_width(nb_nodes) + m_width);
|
||||
|
||||
/* Because the number of SLD nodes is now known, the Nodes on the hub can be
|
||||
* enumerated by repeating the 8 four-bit nibble scans, once for each Node,
|
||||
* to yield the SLD_NODE_INFO register of each Node. The DR nibble shifts
|
||||
* are a continuation of the HUB_INFO DR shift used to shift out the Hub IP
|
||||
* Configuration register.
|
||||
*
|
||||
* The order of the Nodes as they are shifted out determines the ADDR
|
||||
* values for the Nodes, beginning with, for the first Node SLD_NODE_INFO
|
||||
* shifted out, up to and including, for the last node on the hub. The
|
||||
* tables below show the SLD_NODE_INFO register and a their functional descriptions.
|
||||
*
|
||||
* --------------+-----------+---------------+----------------
|
||||
* 31 27 | 26 19 | 18 8 | 7 0
|
||||
* --------------+-----------+---------------+----------------
|
||||
* Node Version | NODE ID | NODE MFG_ID | NODE INST ID
|
||||
*
|
||||
*/
|
||||
|
||||
int vjtag_node_address = -1;
|
||||
int node_index;
|
||||
uint32_t node_info = 0;
|
||||
for (node_index = 0; node_index < nb_nodes; node_index++) {
|
||||
|
||||
for (int i = 0; i < 8; i++) {
|
||||
field.num_bits = 4;
|
||||
field.out_value = NULL;
|
||||
field.in_value = &nibble;
|
||||
jtag_add_dr_scan(tap, 1, &field, TAP_IDLE);
|
||||
retval = jtag_execute_queue();
|
||||
if (retval != ERROR_OK)
|
||||
return retval;
|
||||
node_info = ((node_info >> 4) | ((nibble & 0xf) << 28));
|
||||
}
|
||||
|
||||
LOG_DEBUG("Node info register");
|
||||
LOG_DEBUG("--------------------");
|
||||
LOG_DEBUG("instance_id = %d", ID(node_info));
|
||||
LOG_DEBUG("manufacturer_id = 0x%02x", MANUF(node_info));
|
||||
LOG_DEBUG("node_id = %d (%s)", ID(node_info),
|
||||
id_to_string(ID(node_info)));
|
||||
LOG_DEBUG("version = %d", VER(node_info));
|
||||
|
||||
if (ID(node_info) == VJTAG_NODE_ID)
|
||||
vjtag_node_address = node_index + 1;
|
||||
}
|
||||
|
||||
if (vjtag_node_address < 0) {
|
||||
LOG_ERROR("No VJTAG TAP instance found !");
|
||||
return ERROR_FAIL;
|
||||
}
|
||||
|
||||
/* Select VIR */
|
||||
t[0] = ALTERA_CYCLONE_CMD_USER1;
|
||||
field.num_bits = tap->ir_length;
|
||||
field.out_value = t;
|
||||
field.in_value = NULL;
|
||||
jtag_add_ir_scan(tap, &field, TAP_IDLE);
|
||||
|
||||
/* Send the DEBUG command to the VJTAG IR */
|
||||
buf_set_u32(t, 0, field.num_bits, (vjtag_node_address << m_width) | ALT_VJTAG_CMD_DEBUG);
|
||||
field.num_bits = guess_addr_width(nb_nodes) + m_width;
|
||||
field.out_value = t;
|
||||
field.in_value = NULL;
|
||||
jtag_add_dr_scan(tap, 1, &field, TAP_IDLE);
|
||||
|
||||
/* Select the VJTAG DR */
|
||||
t[0] = ALTERA_CYCLONE_CMD_USER0;
|
||||
field.num_bits = tap->ir_length;
|
||||
field.out_value = t;
|
||||
field.in_value = NULL;
|
||||
jtag_add_ir_scan(tap, &field, TAP_IDLE);
|
||||
|
||||
return jtag_execute_queue();
|
||||
}
|
||||
|
||||
static struct or1k_tap_ip vjtag_tap = {
|
||||
.name = "vjtag",
|
||||
.init = or1k_tap_vjtag_init,
|
||||
};
|
||||
|
||||
int or1k_tap_vjtag_register(void)
|
||||
{
|
||||
list_add_tail(&vjtag_tap.list, &tap_list);
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -101,6 +101,7 @@ extern struct target_type hla_target;
|
|||
extern struct target_type nds32_v2_target;
|
||||
extern struct target_type nds32_v3_target;
|
||||
extern struct target_type nds32_v3m_target;
|
||||
extern struct target_type or1k_target;
|
||||
|
||||
static struct target_type *target_types[] = {
|
||||
&arm7tdmi_target,
|
||||
|
|
@ -128,6 +129,7 @@ static struct target_type *target_types[] = {
|
|||
&nds32_v2_target,
|
||||
&nds32_v3_target,
|
||||
&nds32_v3m_target,
|
||||
&or1k_target,
|
||||
NULL,
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -0,0 +1,42 @@
|
|||
# If you want to use the VJTAG TAP, you must set your FPGA TAP ID here
|
||||
set FPGATAPID 0x020b30dd
|
||||
# Choose your TAP core (VJTAG or MOHOR)
|
||||
set TAP_TYPE VJTAG
|
||||
# Set your chip name
|
||||
set CHIPNAME or1200
|
||||
|
||||
source [find target/or1k.cfg]
|
||||
|
||||
# Set the adapter speed
|
||||
adapter_khz 3000
|
||||
|
||||
# Enable the target description feature
|
||||
gdb_target_description enable
|
||||
|
||||
# Add a new register in the cpu register list. This register will be
|
||||
# included in the generated target descriptor file.
|
||||
# format is addreg [name] [address] [feature] [reg_group]
|
||||
addreg rtest 0x1234 org.gnu.gdb.or1k.group0 system
|
||||
|
||||
# Override default init_reset
|
||||
proc init_reset {mode} {
|
||||
soft_reset_halt
|
||||
resume
|
||||
}
|
||||
|
||||
# Target initialization
|
||||
init
|
||||
echo "Halting processor"
|
||||
halt
|
||||
|
||||
foreach name [target names] {
|
||||
set y [$name cget -endian]
|
||||
set z [$name cget -type]
|
||||
puts [format "Chip is %s, Endian: %s, type: %s" \
|
||||
$name $y $z]
|
||||
}
|
||||
|
||||
set c_blue "\033\[01;34m"
|
||||
set c_reset "\033\[0m"
|
||||
|
||||
puts [format "%sTarget ready...%s" $c_blue $c_reset]
|
||||
|
|
@ -0,0 +1,53 @@
|
|||
set _ENDIAN big
|
||||
|
||||
if { [info exists CHIPNAME] } {
|
||||
set _CHIPNAME $CHIPNAME
|
||||
} else {
|
||||
set _CHIPNAME or1k
|
||||
}
|
||||
|
||||
if { [info exists TAP_TYPE] } {
|
||||
set _TAP_TYPE $TAP_TYPE
|
||||
} else {
|
||||
puts "You need to select a tap type"
|
||||
shutdown
|
||||
}
|
||||
|
||||
# Configure the target
|
||||
if { [string compare $_TAP_TYPE "VJTAG"] == 0 } {
|
||||
if { [info exists FPGATAPID] } {
|
||||
set _FPGATAPID $FPGATAPID
|
||||
} else {
|
||||
puts "You need to set your FPGA JTAG ID"
|
||||
shutdown
|
||||
}
|
||||
|
||||
jtag newtap $_CHIPNAME cpu -irlen 10 -expected-id $_FPGATAPID
|
||||
|
||||
set _TARGETNAME $_CHIPNAME.cpu
|
||||
target create $_TARGETNAME or1k -endian $_ENDIAN -chain-position $_TARGETNAME
|
||||
|
||||
# Select the TAP core we are using
|
||||
tap_select vjtag
|
||||
} else {
|
||||
# OpenCores Mohor JTAG TAP ID
|
||||
set _CPUTAPID 0x14951185
|
||||
|
||||
jtag newtap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID
|
||||
|
||||
set _TARGETNAME $_CHIPNAME.cpu
|
||||
target create $_TARGETNAME or1k -endian $_ENDIAN -chain-position $_TARGETNAME
|
||||
|
||||
# Select the TAP core we are using
|
||||
tap_select mohor
|
||||
}
|
||||
|
||||
# Select the debug unit core we are using. This debug unit as an option.
|
||||
|
||||
proc ADBG_USE_HISPEED {} { return 1 }
|
||||
|
||||
# If ADBG_USE_HISPEED is set (options bit 1), status bits will be skipped
|
||||
# on burst reads and writes to improve download speeds.
|
||||
# This option must match the RTL configured option.
|
||||
|
||||
du_select adv [ADBG_USE_HISPEED]
|
||||
Loading…
Reference in New Issue