riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity
2,487 Commits 90 Branches 49 Tags 38 MiB
Commit Graph

2487 Commits

Author SHA1 Message Date
Clifford Wolf 8197169f8d Added techmap rules for $sr, $dffsr and $dlatch 2013-10-18 12:29:21 +02:00
Clifford Wolf e0f693cbb0 Added $_SR_[PN][PN]_, $_DFFSR_[PN][PN][PN]_, $_DLATCH_[PN]_ 2013-10-18 12:13:34 +02:00
Clifford Wolf 5998c101a4 Added $sr, $dffsr and $dlatch cell types 2013-10-18 11:56:16 +02:00
Clifford Wolf 9bc703b964 Improved way of connecting ports in techmap pass 2013-10-17 22:19:38 +02:00
Clifford Wolf 8cc53ef72c Only prefer connected signals iff they have public names 2013-10-17 22:10:55 +02:00
Clifford Wolf 30b0de006f Added -buf, -true and -false options to blif backend 2013-10-17 21:37:18 +02:00
Clifford Wolf 95dbacefbf Fixed bug in synthesis of memories that are never written 2013-10-17 21:00:37 +02:00
Clifford Wolf c20571ca5e Avoid re-arranging signals on register outputs 2013-10-17 20:48:40 +02:00
Clifford Wolf f5c0ed6c79 Fixed detection of major wires in opt_clean 2013-10-17 02:41:59 +02:00
Clifford Wolf 96e7abad48 Added iopadmap pass 2013-10-16 16:16:06 +02:00
Clifford Wolf b6db2d9b33 Moved dfflibmap from passes/dfflibmap to passes/techmap 2013-10-16 15:32:26 +02:00
Clifford Wolf 5745d3de9a Added map, par and bitgen to xlinx7 example 2013-10-16 10:57:18 +02:00
Clifford Wolf 845590aa8e Fixed parsing or liberty file statements such as 'clocked_on : "(!CLK)";' 
Patch by Tim Edwards
 2013-10-16 06:32:35 +02:00
Clifford Wolf a12d39bc86 Added recommended apt-get commands to README 2013-10-11 22:25:23 +02:00
Clifford Wolf a97520785a Fixed minisat include 2013-10-11 21:17:01 +02:00
Clifford Wolf 02efafa7f1 Pinned ABC revision to 0f9e5488ced3 2013-10-03 16:03:30 +02:00
Clifford Wolf 5dce6379aa Improvements in EDIF backend 2013-09-17 13:07:12 +02:00
Clifford Wolf dc767d4e4c Added additional options to BLIF backend 2013-09-15 13:33:33 +02:00
Clifford Wolf 0ec5542ab4 Added BLIF backend 2013-09-15 13:13:01 +02:00
Clifford Wolf 28069e8a10 A couple of small fixes in SPICE backend 2013-09-15 12:19:06 +02:00
Clifford Wolf 288ba9618a Moved common techlib files to techlibs/common 2013-09-15 11:52:57 +02:00
Clifford Wolf 647c23b7b7 Updated manual 2013-09-15 11:41:05 +02:00
Clifford Wolf 2c9bd23801 Added spice testbench to techlibs/cmos 2013-09-14 13:29:11 +02:00
Clifford Wolf bbe5aa446b Added spice backend 2013-09-14 11:23:45 +02:00
Clifford Wolf 70476e2431 Merge branch 'master' of github.com:cliffordwolf/yosys 2013-09-03 19:10:25 +02:00
Clifford Wolf 73914d1a41 Added -selected option to various backends 2013-09-03 19:10:11 +02:00
Clifford Wolf 09e200797a Encode large (>32 bits) parameters as hex string in edif backend 2013-08-28 08:48:49 +02:00
Clifford Wolf 2feee7415d Improved edif backend 2013-08-27 14:22:11 +02:00
Clifford Wolf 6685ad436e Added mapping to techlibs/xilinx7 testbench (exposes EDIF backend todos) 2013-08-27 13:12:26 +02:00
Clifford Wolf 5059b31660 Added simple xilinx7 technology mapping files 2013-08-22 20:31:04 +02:00
Clifford Wolf 39ee561169 More explicit integer output in verilog backend 2013-08-22 20:31:04 +02:00
Clifford Wolf 4f4cb2307f Added correct encoding of identifiers in EDIF backend 2013-08-22 14:30:33 +02:00
Clifford Wolf aba8639a3f Added edif backend (still under construction) 2013-08-22 11:34:55 +02:00
Clifford Wolf 8409956c0c Merge pull request #10 from hansiglaser/master 
fixed Verilog parser filename and line numbering issue with include files
 2013-08-21 09:47:06 -07:00
Clifford Wolf f8107ab7fc Some minor documentation fixes 2013-08-21 12:16:44 +02:00
Johann Glaser f352205635 fixed Verilog parser filename and line numbering issue with include files 2013-08-21 09:20:59 +02:00
Clifford Wolf 459e8964fd Merge pull request #9 from hansiglaser/master 
Added support for include directories with the new '-I' argument of the 'read_verilog' command
 2013-08-20 09:38:31 -07:00
Johann Glaser a99c224157 Added support for include directories with the new '-I' argument of the 
'read_verilog' command
 2013-08-20 15:48:16 +02:00
Clifford Wolf 8e31a92407 Merge pull request #8 from hansiglaser/master 
Added support for notif0/notif1 primitives
 2013-08-20 03:36:34 -07:00
Johann Glaser 6c4cbc03c2 Added support for notif0/notif1 primitives 2013-08-20 11:23:59 +02:00
Clifford Wolf e3aa0514f2 Added cleaning of old version_* files to version_* make rule 2013-08-20 10:13:43 +02:00
Clifford Wolf 485e870bcd Added version info to yosys command and added -V option 2013-08-20 09:48:12 +02:00
Clifford Wolf 1af1cebb64 Minor fixes in abc build instructions and abc pass 2013-08-20 09:46:05 +02:00
Clifford Wolf 0003743432 Fixed width and sign detection for ** operator 2013-08-19 20:58:01 +02:00
Clifford Wolf 8656b1c08f Added support for bufif0/bufif1 primitives 2013-08-19 19:50:04 +02:00
Clifford Wolf 4214561890 Improved ast dumping (ast/verilog frontend) 2013-08-19 19:49:14 +02:00
Clifford Wolf a860efa8ac Implemented same div-by-zero behavior as found in other synthesis tools 2013-08-15 21:00:06 +02:00
Clifford Wolf 78658199e6 Fixed signed div/mod in const eval (rounding and stuff) 2013-08-15 18:23:42 +02:00
Clifford Wolf 457dc09cdc Added ezsat api for creation of anonymous vectors 2013-08-15 14:40:26 +02:00
Clifford Wolf 2f3da54f26 Added sat -ignore_div_by_zero switch 2013-08-15 11:40:01 +02:00