mirror of https://github.com/YosysHQ/yosys.git
Updated manual
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@ -72,8 +72,9 @@ in different stages of the synthesis.
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\node[process] (astfe) [below of=ast, node distance=5em] {AST Frontend};
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\node[data] (rtlil) [below of=astfe, node distance=5em, xshift=7.5em] {RTLIL};
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\node[process] (pass) [right of=rtlil, node distance=5em, xshift=7.5em] {Passes};
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\node[process] (vlbe) [below of=rtlil, node distance=5em, xshift=-7.5em] {Verilog Backend};
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\node[process] (ilangbe) [below of=rtlil, node distance=5em, xshift=+7.5em] {ILANG Backend};
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\node[process] (vlbe) [below of=rtlil, node distance=7em, xshift=-13em] {Verilog Backend};
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\node[process] (ilangbe) [below of=rtlil, node distance=7em, xshift=0em] {ILANG Backend};
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\node[process, dashed, fill=green!5] (otherbe) [below of=rtlil, node distance=7em, xshift=+13em] {Other Backends};
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\draw[-latex] (vlog) -- (ast);
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\draw[-latex] (vhdl) -- (ast);
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@ -83,6 +84,7 @@ in different stages of the synthesis.
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\draw[latex-latex] (rtlil) -- (pass);
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\draw[-latex] (rtlil) -- (vlbe);
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\draw[-latex] (rtlil) -- (ilangbe);
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\draw[-latex] (rtlil) -- (otherbe);
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\end{tikzpicture}
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\caption{Yosys simplified data flow (ellipses: data structures, rectangles: program modules)}
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\label{fig:Overview_flow}
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@ -21,6 +21,9 @@ library to a target architecture.
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but keeps using yosys's internal gate library. This option is ignored if
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the -script option is also used.
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-lut <width>
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generate netlist using luts of (max) the specified width.
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-nocleanup
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when this option is used, the temporary files created by this pass
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are not removed. this is useful for debugging.
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@ -50,6 +53,39 @@ to 'cd <celltype>'.
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This is just a shortcut for 'select -clear'.
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\end{lstlisting}
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\section{clean -- remove unused cells and wires}
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\label{cmd:clean}
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\begin{lstlisting}[numbers=left,frame=single]
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clean [options] [selection]
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This is identical to 'opt_clean', but less verbose.
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When commands are seperated using the ';;' token, this command will be executed
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between the commands.
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When commands are seperated using the ';;;' token, this command will be executed
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in -purge mode between the commands.
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\end{lstlisting}
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\section{design -- save, restore and reset current design}
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\label{cmd:design}
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\begin{lstlisting}[numbers=left,frame=single]
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design -reset
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Clear the current design.
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design -save <name>
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Save the current design under the given name.
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design -load <name>
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Reset the current design and load the design previously saved under the given
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name.
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\end{lstlisting}
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\section{dfflibmap -- technology mapping of flip-flops}
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\label{cmd:dfflibmap}
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\begin{lstlisting}[numbers=left,frame=single]
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@ -176,6 +212,20 @@ pass is very simmilar to the 'techmap' pass. The only difference is that this
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pass is using the current design as mapping library.
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\end{lstlisting}
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\section{freduce -- perform functional reduction}
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\label{cmd:freduce}
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\begin{lstlisting}[numbers=left,frame=single]
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freduce [options] [selection]
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This pass performs functional reduction in the circuit. I.e. if two nodes are
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equivialent, they are merged to one node and one of the redundant drivers is
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removed.
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-try
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do not issue an error when the analysis fails.
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(usually beacause of logic loops in the design)
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\end{lstlisting}
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\section{fsm -- extract and optimize finite state machines}
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\label{cmd:fsm}
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\begin{lstlisting}[numbers=left,frame=single]
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@ -586,11 +636,11 @@ representation of a design in yosys's internal format.)
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Load modules from a verilog file to the current design. A large subset of
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Verilog-2005 is supported.
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-dump_ast
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dump abstract syntax tree (after simplification)
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-dump_ast1
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dump abstract syntax tree (before simplification)
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-dump_ast_diff
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dump ast differences before and after simplification
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-dump_ast2
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dump abstract syntax tree (after simplification)
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-dump_vlog
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dump ast as verilog code (after simplification)
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@ -636,6 +686,10 @@ Verilog-2005 is supported.
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-Dname[=definition]
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define the preprocessor symbol 'name' and set its optional value
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'definition'
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-Idir
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add 'dir' to the directories which are used when searching include
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files
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\end{lstlisting}
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\section{rename -- rename object in the design}
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@ -645,6 +699,12 @@ Verilog-2005 is supported.
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Rename the specified object. Note that selection patterns are not supported
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by this command.
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rename -enumerate [selection]
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Assign short auto-generated names to all selected wires and cells with private
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names.
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\end{lstlisting}
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\section{sat -- solve a SAT problem in the circuit}
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@ -669,6 +729,9 @@ and additional constraints passed as parameters.
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show the model for the specified signal. if no -show option is
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passed then a set of signals to be shown is automatically selected.
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-ignore_div_by_zero
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ignore all solutions that involve a division by zero
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The following options can be used to set up a sequential problem:
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-seq <N>
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@ -707,7 +770,7 @@ is passed, a temporal induction proof is performed.
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scatter [selection]
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This command adds additional intermediate nets on all cell ports. This is used
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for testing the correct use of the SigMap halper in passes. If you don't know
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for testing the correct use of the SigMap helper in passes. If you don't know
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what this means: don't worry -- you only need this pass when testing your own
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extensions to Yosys.
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@ -948,7 +1011,7 @@ to a graphics file (usually SVG or PostScript).
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more than one library.
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-prefix <prefix>
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generate <prefix>.dot and <prefix>.ps instead of ~/.yosys_show.{dot,ps}
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generate <prefix>.* instead of ~/.yosys_show.*
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-color <color> <wire>
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assign the specified color to the specified wire. The object can be
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@ -1037,6 +1100,10 @@ file.
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transforms the internal RTL cells to the internal gate
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library.
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-opt
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run 'opt' pass on all cells from map file before using them and run
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'opt_const' on all replacement cells before mapping recursively.
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When a module in the map file has the 'celltype' attribute set, it will match
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cells with a type that match the text value of this attribute.
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@ -1076,6 +1143,17 @@ value after initialization. This can e.g. be used to force a reset signal
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low in order to explore more inner states in a state machine.
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\end{lstlisting}
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\section{write\_edif -- write design to EDIF netlist file}
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\label{cmd:write_edif}
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\begin{lstlisting}[numbers=left,frame=single]
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write_edif [options] [filename]
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Write the current design to an EDIF netlist file.
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-top top_module
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set the specified module as design top module
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\end{lstlisting}
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\section{write\_ilang -- write design to ilang file}
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\label{cmd:write_ilang}
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\begin{lstlisting}[numbers=left,frame=single]
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@ -1083,6 +1161,9 @@ low in order to explore more inner states in a state machine.
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Write the current design to an 'ilang' file. (ilang is a text representation
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of a design in yosys's internal format.)
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-selected
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only write selected parts of the design.
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\end{lstlisting}
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\section{write\_intersynth -- write design to InterSynth netlist file}
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@ -1102,9 +1183,37 @@ a tool for Coarse-Grain Example-Driven Interconnect Synthesis.
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inputs or outputs. This option can be used multiple times to specify
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more than one library.
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-selected
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only write selected modules. modules must be selected entirely or
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not at all.
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http://www.clifford.at/intersynth/
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\end{lstlisting}
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\section{write\_spice -- write design to SPICE netlist file}
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\label{cmd:write_spice}
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\begin{lstlisting}[numbers=left,frame=single]
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write_spice [options] [filename]
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Write the current design to an SPICE netlist file.
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-big_endian
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generate multi-bit ports in MSB first order
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(default is LSB first)
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-neg net_name
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set the net name for constant 0 (default: Vss)
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-pos net_name
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set the net name for constant 1 (default: Vdd)
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-nc_prefix
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prefix for not-connected nets (default: _NC)
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-top top_module
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set the specified module as design top module
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\end{lstlisting}
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\section{write\_verilog -- write design to verilog file}
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\label{cmd:write_verilog}
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\begin{lstlisting}[numbers=left,frame=single]
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usually modules with the 'placeholder' attribute are ignored. with
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this option set only the modules with the 'placeholder' attribute
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are written to the output file.
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-selected
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only write selected modules. modules must be selected entirely or
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not at all.
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\end{lstlisting}
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@ -1,22 +1,59 @@
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#!/bin/bash
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fast_mode=false
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update_mode=false
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set -- $(getopt fu "$@")
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while [ $# -gt 0 ]; do
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case "$1" in
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-f)
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fast_mode=true
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;;
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-u)
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update_mode=true
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;;
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--)
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shift
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break
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;;
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-*)
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echo "$0: error - unrecognized option $1" 1>&2
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exit 1
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;;
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*)
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break
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esac
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shift
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done
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PDFTEX_OPT="-shell-escape -halt-on-error"
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md5sum *.aux *.bbl *.blg > autoloop.old
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if $update_mode; then
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make -C ..
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../yosys -p 'help -write-tex-command-reference-manual'
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fi
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if ! $fast_mode; then
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md5sum *.aux *.bbl *.blg > autoloop.old
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fi
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set -ex
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pdflatex $PDFTEX_OPT manual.tex
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bibtex manual.aux
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bibtex weblink.aux
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while
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md5sum *.aux *.bbl *.blg > autoloop.new
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! cmp autoloop.old autoloop.new
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do
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cp autoloop.new autoloop.old
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pdflatex $PDFTEX_OPT manual.tex
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done
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if ! $fast_mode; then
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bibtex manual.aux
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bibtex weblink.aux
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rm -f autoloop.old
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rm -f autoloop.new
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while
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md5sum *.aux *.bbl *.blg > autoloop.new
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! cmp autoloop.old autoloop.new
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do
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cp autoloop.new autoloop.old
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pdflatex $PDFTEX_OPT manual.tex
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done
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rm -f autoloop.old
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rm -f autoloop.new
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fi
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