mirror of https://github.com/YosysHQ/yosys.git
Fixed signed div/mod in const eval (rounding and stuff)
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@ -366,7 +366,10 @@ RTLIL::Const RTLIL::const_div(const RTLIL::Const &arg1, const RTLIL::Const &arg2
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BigInteger b = const2big(arg2, signed2, undef_bit_pos);
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if (b.isZero())
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return RTLIL::Const(RTLIL::State::Sx, result_len);
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return big2const(a / b, result_len >= 0 ? result_len : std::max(arg1.bits.size(), arg2.bits.size()), std::min(undef_bit_pos, 0));
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bool result_neg = (a.getSign() == BigInteger::negative) != (b.getSign() == BigInteger::negative);
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a = a.getSign() == BigInteger::negative ? -a : a;
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b = b.getSign() == BigInteger::negative ? -b : b;
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return big2const(result_neg ? -(a / b) : (a / b), result_len >= 0 ? result_len : std::max(arg1.bits.size(), arg2.bits.size()), std::min(undef_bit_pos, 0));
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}
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RTLIL::Const RTLIL::const_mod(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len)
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@ -376,7 +379,10 @@ RTLIL::Const RTLIL::const_mod(const RTLIL::Const &arg1, const RTLIL::Const &arg2
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BigInteger b = const2big(arg2, signed2, undef_bit_pos);
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if (b.isZero())
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return RTLIL::Const(RTLIL::State::Sx, result_len);
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return big2const(a % b, result_len >= 0 ? result_len : std::max(arg1.bits.size(), arg2.bits.size()), std::min(undef_bit_pos, 0));
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bool result_neg = a.getSign() == BigInteger::negative;
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a = a.getSign() == BigInteger::negative ? -a : a;
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b = b.getSign() == BigInteger::negative ? -b : b;
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return big2const(result_neg ? -(a % b) : (a % b), result_len >= 0 ? result_len : std::max(arg1.bits.size(), arg2.bits.size()), std::min(undef_bit_pos, 0));
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}
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RTLIL::Const RTLIL::const_pow(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len)
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