mirror of https://github.com/YosysHQ/yosys.git
Merge pull request #8 from hansiglaser/master
Added support for notif0/notif1 primitives
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commit
8e31a92407
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@ -498,7 +498,7 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage)
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}
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children.clear();
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if (str == "bufif0" || str == "bufif1")
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if (str == "bufif0" || str == "bufif1" || str == "notif0" || str == "notif1")
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{
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if (children_list.size() != 3)
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log_error("Invalid number of arguments for primitive `%s' at %s:%d!\n",
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@ -506,12 +506,16 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage)
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std::vector<RTLIL::State> z_const(1, RTLIL::State::Sz);
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AstNode *mux_input = children_list.at(1);
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if (str == "notif0" || str == "notif1") {
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mux_input = new AstNode(AST_BIT_NOT, mux_input);
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}
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AstNode *node = new AstNode(AST_TERNARY, children_list.at(2));
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if (str == "bufif0") {
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node->children.push_back(AstNode::mkconst_bits(z_const, false));
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node->children.push_back(children_list.at(1));
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node->children.push_back(mux_input);
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} else {
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node->children.push_back(children_list.at(1));
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node->children.push_back(mux_input);
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node->children.push_back(AstNode::mkconst_bits(z_const, false));
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}
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@ -169,7 +169,7 @@ namespace VERILOG_FRONTEND {
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}
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<STRING>. { yymore(); }
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and|nand|or|nor|xor|xnor|not|buf|bufif0|bufif1 {
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and|nand|or|nor|xor|xnor|not|buf|bufif0|bufif1|notif0|notif1 {
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frontend_verilog_yylval.string = new std::string(yytext);
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return TOK_PRIMITIVE;
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}
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