Clifford Wolf
|
34f2b84fb6
|
Fixed handling of parameters and localparams in functions
|
2015-11-11 10:54:35 +01:00 |
Clifford Wolf
|
207736b4ee
|
Import more std:: stuff into Yosys namespace
|
2015-10-25 19:30:49 +01:00 |
Clifford Wolf
|
e51dcc83d0
|
Fixed complexity of assigning to vectors in constant functions
|
2015-10-01 12:15:35 +02:00 |
Clifford Wolf
|
9caeadf797
|
Fixed detection of unconditional $readmem[hb]
|
2015-09-30 15:46:51 +02:00 |
Clifford Wolf
|
f9d7df0869
|
Bugfixes in $readmem[hb]
|
2015-09-25 13:49:48 +02:00 |
Clifford Wolf
|
b2544cfcf7
|
Fixed segfault in AstNode::asReal
|
2015-09-25 12:38:01 +02:00 |
Clifford Wolf
|
924d9d6e86
|
Added read-enable to memory model
|
2015-09-25 12:23:11 +02:00 |
Clifford Wolf
|
1b8cb9940e
|
Fixed AstNode::mkconst_bits() segfault on zero-sized constant
|
2015-09-24 11:21:20 +02:00 |
Clifford Wolf
|
089c1e176f
|
Bugfix in handling of multi-dimensional memories
|
2015-09-23 07:56:17 +02:00 |
Clifford Wolf
|
559929e341
|
Warning for $display/$write outside initial block
|
2015-09-23 07:16:03 +02:00 |
Clifford Wolf
|
6176f4d081
|
Fixed multi-level prefix resolving
|
2015-09-22 20:52:02 +02:00 |
Andrew Zonenberg
|
c469f22144
|
Improvements to $display system task
|
2015-09-19 10:33:37 +02:00 |
Clifford Wolf
|
9db05d17fe
|
Added AST_INITIAL checks for $finish and $display
|
2015-09-18 09:50:57 +02:00 |
Andrew Zonenberg
|
7141f65533
|
Initial implementation of $display()
|
2015-09-18 09:36:46 +02:00 |
Andrew Zonenberg
|
e446e651cb
|
Initial implementation of $finish()
|
2015-09-18 09:30:25 +02:00 |
Clifford Wolf
|
eb38722e98
|
Fixed handling of memory read without address
|
2015-08-22 14:46:42 +02:00 |
Larry Doolittle
|
6c00704a5e
|
Another block of spelling fixes
Smaller this time
|
2015-08-14 23:27:05 +02:00 |
Larry Doolittle
|
022f570563
|
Keep gcc from complaining about uninitialized variables
|
2015-08-14 23:26:49 +02:00 |
Clifford Wolf
|
84bf862f7c
|
Spell check (by Larry Doolittle)
|
2015-08-14 10:56:05 +02:00 |
Clifford Wolf
|
8d6d5c30d9
|
Added WORDS parameter to $meminit
|
2015-07-31 10:40:09 +02:00 |
Clifford Wolf
|
4513ff1b85
|
Fixed nested mem2reg
|
2015-07-29 16:37:08 +02:00 |
Clifford Wolf
|
6c84341f22
|
Fixed trailing whitespaces
|
2015-07-02 11:14:30 +02:00 |
Clifford Wolf
|
13983e8318
|
Fixed handling of parameters with reversed range
|
2015-06-08 14:03:06 +02:00 |
Clifford Wolf
|
99b8746d27
|
Fixed signedness of genvar expressions
|
2015-05-29 20:08:00 +02:00 |
Clifford Wolf
|
422794c584
|
Const-fold parameter defs on-demand in AstNode::detectSignWidthWorker()
|
2015-03-01 11:20:22 +01:00 |
Clifford Wolf
|
1f1deda888
|
Added non-std verilog assume() statement
|
2015-02-26 18:47:39 +01:00 |
Clifford Wolf
|
d5ce9a32ef
|
Added deep recursion warning to AST simplify
|
2015-02-20 10:33:20 +01:00 |
Clifford Wolf
|
dc1a0f06fc
|
Parser support for complex delay expressions
|
2015-02-20 10:21:36 +01:00 |
Clifford Wolf
|
c2ba4fb2fd
|
Convert floating point cell parameters to strings
|
2015-02-18 23:35:23 +01:00 |
Clifford Wolf
|
e9368a1d7e
|
Various fixes for memories with offsets
|
2015-02-14 14:21:15 +01:00 |
Clifford Wolf
|
7f1a1759d7
|
Added "read_verilog -nomeminit" and "nomeminit" attribute
|
2015-02-14 11:21:12 +01:00 |
Clifford Wolf
|
a8e9d37c14
|
Creating $meminit cells in verilog front-end
|
2015-02-14 10:49:30 +01:00 |
Clifford Wolf
|
cd919abdf1
|
Added AstNode::simplify() recursion counter
|
2015-02-13 12:33:12 +01:00 |
Clifford Wolf
|
234a45a3d5
|
Ignore explicit assignments to constants in HDL code
|
2015-02-08 00:58:03 +01:00 |
Clifford Wolf
|
c8305e3a6d
|
Fixed a bug with autowire bit size
(removed leftover from when we tried to auto-size the wires)
|
2015-02-08 00:48:23 +01:00 |
Clifford Wolf
|
2a9ad48eb6
|
Added ENABLE_NDEBUG makefile options
|
2015-01-24 12:16:46 +01:00 |
Clifford Wolf
|
df9d096a7d
|
Ignoring more system task and functions
|
2015-01-15 13:08:19 +01:00 |
Clifford Wolf
|
a588a4a5c9
|
Fixed handling of "input foo; reg [0:0] foo;"
|
2015-01-15 12:53:12 +01:00 |
Clifford Wolf
|
8e8e791fb5
|
Consolidate "Blocking assignment to memory.." msgs for the same line
|
2015-01-15 12:41:52 +01:00 |
Clifford Wolf
|
eefe78be09
|
Fixed memory->start_offset handling
|
2015-01-01 12:56:01 +01:00 |
Clifford Wolf
|
0bb6b24c11
|
Added global yosys_celltypes
|
2014-12-29 14:30:33 +01:00 |
Clifford Wolf
|
90bc71dd90
|
dict/pool changes in ast
|
2014-12-29 03:11:50 +01:00 |
Clifford Wolf
|
137f35373f
|
Changed more code to dict<> and pool<>
|
2014-12-28 19:24:24 +01:00 |
Clifford Wolf
|
12ca6538a4
|
Fixed mem2reg warning message
|
2014-12-27 03:26:30 +01:00 |
Clifford Wolf
|
a6c96b986b
|
Added Yosys::{dict,nodict,vector} container types
|
2014-12-26 10:53:21 +01:00 |
Clifford Wolf
|
edb3c9d0c4
|
Renamed extend() to extend_xx(), changed most users to extend_u0()
|
2014-12-24 09:51:17 +01:00 |
Clifford Wolf
|
fe829bdbdc
|
Added log_warning() API
|
2014-11-09 10:44:23 +01:00 |
Clifford Wolf
|
37aa2e02db
|
AST simplifier: optimize constant AST_CASE nodes before recursively descending
|
2014-10-29 08:29:51 +01:00 |
Clifford Wolf
|
c4a2b3c1e9
|
Improvements in $readmem[bh] implementation
|
2014-10-26 23:29:36 +01:00 |
Clifford Wolf
|
70b2efdb05
|
Added support for $readmemh/$readmemb
|
2014-10-26 20:33:10 +01:00 |
Clifford Wolf
|
26cbe4a4e5
|
Fixed constant "cond ? string1 : string2" with strings of different size
|
2014-10-25 18:23:53 +02:00 |
Clifford Wolf
|
750c615e7f
|
minor indenting corrections
|
2014-10-19 18:42:03 +02:00 |
Parviz Palangpour
|
de8adb8ec5
|
Builds on Mac 10.9.2 with LLVM 3.5.
|
2014-10-19 11:14:43 -05:00 |
Clifford Wolf
|
84ffe04075
|
Fixed various VS warnings
|
2014-10-18 15:20:38 +02:00 |
William Speirs
|
fda52f05f2
|
Wrapped math in int constructor
|
2014-10-17 11:28:14 +02:00 |
Clifford Wolf
|
6b05a9e807
|
Fixed handling of invalid array access in mem2reg code
|
2014-10-16 00:44:23 +02:00 |
Clifford Wolf
|
35fbc0b35f
|
Do not the 'z' modifier in format string (another win32 fix)
|
2014-10-11 11:42:08 +02:00 |
Clifford Wolf
|
4569a747f8
|
Renamed SIZE() to GetSize() because of name collision on Win32
|
2014-10-10 17:07:24 +02:00 |
Clifford Wolf
|
f9a307a50b
|
namespace Yosys
|
2014-09-27 16:17:53 +02:00 |
Clifford Wolf
|
48b00dccea
|
Another $clog2 bugfix
|
2014-09-08 12:25:23 +02:00 |
Clifford Wolf
|
680eaaac41
|
Fixed $clog2 (off by one error)
|
2014-09-06 19:31:04 +02:00 |
Clifford Wolf
|
deff416ea7
|
Fixed assignment of out-of bounds array element
|
2014-09-06 17:58:27 +02:00 |
Ruben Undheim
|
79cbf9067c
|
Corrected spelling mistakes found by lintian
|
2014-09-06 08:47:06 +02:00 |
Clifford Wolf
|
8927aa6148
|
Removed $bu0 cell type
|
2014-09-04 02:07:52 +02:00 |
Clifford Wolf
|
98442e019d
|
Added emscripten (emcc) support to build system and some build fixes
|
2014-08-22 16:20:22 +02:00 |
Clifford Wolf
|
74af3a2b70
|
Archibald Rust and Clifford Wolf: ffi-based dpi_call()
|
2014-08-22 14:22:09 +02:00 |
Clifford Wolf
|
ad146c2582
|
Fixed small memory leak in ast simplify
|
2014-08-21 17:33:40 +02:00 |
Clifford Wolf
|
6c5cafcd8b
|
Added support for DPI function with different names in C and Verilog
|
2014-08-21 17:22:04 +02:00 |
Clifford Wolf
|
085c8e873d
|
Added AstNode::asInt()
|
2014-08-21 17:11:51 +02:00 |
Clifford Wolf
|
490d7a5bf2
|
Fixed memory leak in DPI function calls
|
2014-08-21 13:09:47 +02:00 |
Clifford Wolf
|
7bfc4ae120
|
Added Verilog/AST support for DPI functions (dpi_call() still unimplemented)
|
2014-08-21 12:43:51 +02:00 |
Clifford Wolf
|
38addd4c67
|
Added support for global tasks and functions
|
2014-08-21 12:42:28 +02:00 |
Clifford Wolf
|
640d9fc551
|
Added "via_celltype" attribute on task/func
|
2014-08-18 14:29:30 +02:00 |
Clifford Wolf
|
acb435b6cf
|
Added const folding of AST_CASE to AST simplifier
|
2014-08-18 00:02:30 +02:00 |
Clifford Wolf
|
64713647a9
|
Improved AST ProcessGenerator performance
|
2014-08-17 02:17:49 +02:00 |
Clifford Wolf
|
d491fd8c19
|
Use stackmap<> in AST ProcessGenerator
|
2014-08-17 00:57:24 +02:00 |
Clifford Wolf
|
83e2698e10
|
AST ProcessGenerator: replaced subst_*_{from,to} with subst_*_map
|
2014-08-16 19:31:59 +02:00 |
Clifford Wolf
|
c7afbd9d8e
|
Fixed bug in "read_verilog -ignore_redef"
|
2014-08-15 01:53:22 +02:00 |
Clifford Wolf
|
978a933b6a
|
Added RTLIL::SigSpec::to_sigbit_map()
|
2014-08-14 23:14:47 +02:00 |
Clifford Wolf
|
c83b990458
|
Changed the AST genWidthRTLIL subst interface to use a std::map
|
2014-08-14 23:02:07 +02:00 |
Clifford Wolf
|
85e3cc12ac
|
Fixed handling of task outputs
|
2014-08-14 22:26:10 +02:00 |
Clifford Wolf
|
1bf7a18fec
|
Added module->ports
|
2014-08-14 16:22:52 +02:00 |
Clifford Wolf
|
d259abbda2
|
Added AST_MULTIRANGE (arrays with more than 1 dimension)
|
2014-08-06 15:52:54 +02:00 |
Clifford Wolf
|
91dd87e60b
|
Improved scope resolution of local regs in Verilog+AST frontend
|
2014-08-05 12:15:53 +02:00 |
Clifford Wolf
|
0129d41efa
|
Fixed AST handling of variables declared inside a functions main block
|
2014-08-05 08:35:51 +02:00 |
Clifford Wolf
|
768eb846c4
|
More bugfixes related to new RTLIL::IdString
|
2014-08-02 18:14:21 +02:00 |
Clifford Wolf
|
b9bd22b8c8
|
More cleanups related to RTLIL::IdString usage
|
2014-08-02 13:19:57 +02:00 |
Clifford Wolf
|
14412e6c95
|
Preparations for RTLIL::IdString redesign: cleanup of existing code
|
2014-08-02 00:45:25 +02:00 |
Clifford Wolf
|
bd74ed7da4
|
Replaced sha1 implementation
|
2014-08-01 19:01:10 +02:00 |
Clifford Wolf
|
cdae8abe16
|
Renamed port access function on RTLIL::Cell, added param access functions
|
2014-07-31 16:38:54 +02:00 |
Clifford Wolf
|
e6d33513a5
|
Added module->design and cell->module, wire->module pointers
|
2014-07-31 14:11:39 +02:00 |
Clifford Wolf
|
1cb25c05b3
|
Moved some stuff to kernel/yosys.{h,cc}, using Yosys:: namespace
|
2014-07-31 13:19:47 +02:00 |
Clifford Wolf
|
397b00252d
|
Added $shift and $shiftx cell types (needed for correct part select behavior)
|
2014-07-29 16:35:13 +02:00 |
Clifford Wolf
|
48822e79a3
|
Removed left over debug code
|
2014-07-28 19:38:30 +02:00 |
Clifford Wolf
|
ec58965967
|
Fixed part selects of parameters
|
2014-07-28 19:24:28 +02:00 |
Clifford Wolf
|
a03297a7df
|
Set results of out-of-bounds static bit/part select to undef
|
2014-07-28 16:09:50 +02:00 |
Clifford Wolf
|
55521c085a
|
Fixed RTLIL code generator for part select of parameter
|
2014-07-28 15:31:19 +02:00 |
Clifford Wolf
|
0598bc8708
|
Fixed width detection for part selects
|
2014-07-28 15:19:34 +02:00 |
Clifford Wolf
|
27a872d1e7
|
Added support for "upto" wires to Verilog front- and back-end
|
2014-07-28 14:25:03 +02:00 |
Clifford Wolf
|
3c45277ee0
|
Added wire->upto flag for signals such as "wire [0:7] x;"
|
2014-07-28 12:12:13 +02:00 |
Clifford Wolf
|
7bd2d1064f
|
Using log_assert() instead of assert()
|
2014-07-28 11:27:48 +02:00 |
Clifford Wolf
|
ee65dea738
|
Fixed signdness detection of expressions with bit- and part-selects
|
2014-07-28 10:10:08 +02:00 |
Clifford Wolf
|
c4bdba78cb
|
Added proper Design->addModule interface
|
2014-07-27 21:12:09 +02:00 |
Clifford Wolf
|
10e5791c5e
|
Refactoring: Renamed RTLIL::Design::modules to modules_
|
2014-07-27 11:18:30 +02:00 |
Clifford Wolf
|
f9946232ad
|
Refactoring: Renamed RTLIL::Module::wires to wires_
|
2014-07-27 01:49:51 +02:00 |
Clifford Wolf
|
946ddff9ce
|
Changed a lot of code to the new RTLIL::Wire constructors
|
2014-07-26 20:12:50 +02:00 |
Clifford Wolf
|
f8fdc47d33
|
Manual fixes for new cell connections API
|
2014-07-26 15:58:23 +02:00 |
Clifford Wolf
|
b7dda72302
|
Changed users of cell->connections_ to the new API (sed command)
git grep -l 'connections_' | xargs sed -i -r -e '
s/(->|\.)connections_\["([^"]*)"\] = (.*);/\1set("\2", \3);/g;
s/(->|\.)connections_\["([^"]*)"\]/\1get("\2")/g;
s/(->|\.)connections_.at\("([^"]*)"\)/\1get("\2")/g;
s/(->|\.)connections_.push_back/\1connect/g;
s/(->|\.)connections_/\1connections()/g;'
|
2014-07-26 15:58:23 +02:00 |
Clifford Wolf
|
cc4f10883b
|
Renamed RTLIL::{Module,Cell}::connections to connections_
|
2014-07-26 11:58:03 +02:00 |
Clifford Wolf
|
2bec47a404
|
Use only module->addCell() and module->remove() to create and delete cells
|
2014-07-25 17:56:19 +02:00 |
Clifford Wolf
|
309d64d46a
|
Fixed two memory leaks in ast simplify
|
2014-07-25 13:24:10 +02:00 |
Clifford Wolf
|
6aa792c864
|
Replaced more old SigChunk programming patterns
|
2014-07-24 23:10:58 +02:00 |
Clifford Wolf
|
20a7965f61
|
Various small fixes (from gcc compiler warnings)
|
2014-07-23 20:45:27 +02:00 |
Clifford Wolf
|
c094c53de8
|
Removed RTLIL::SigSpec::optimize()
|
2014-07-23 20:32:28 +02:00 |
Clifford Wolf
|
115dd959d9
|
SigSpec refactoring: More cleanups of old SigSpec use pattern
|
2014-07-22 23:50:21 +02:00 |
Clifford Wolf
|
28b3fd05fa
|
SigSpec refactoring: change RTLIL::SigSpec::chunks() to be read-only, created interim RTLIL::SigSpec::chunks_rw()
|
2014-07-22 20:58:44 +02:00 |
Clifford Wolf
|
7bffde6abd
|
SigSpec refactoring: change RTLIL::SigSpec::size() to be read-only
|
2014-07-22 20:39:38 +02:00 |
Clifford Wolf
|
4b4048bc5f
|
SigSpec refactoring: using the accessor functions everywhere
|
2014-07-22 20:39:37 +02:00 |
Clifford Wolf
|
a233762a81
|
SigSpec refactoring: renamed chunks and width to __chunks and __width
|
2014-07-22 20:39:37 +02:00 |
Clifford Wolf
|
9b183539af
|
Implemented dynamic bit-/part-select for memory writes
|
2014-07-17 16:49:23 +02:00 |
Clifford Wolf
|
5867f6bcdc
|
Added support for bit/part select to mem2reg rewriter
|
2014-07-17 13:49:32 +02:00 |
Clifford Wolf
|
6d69d4aaa8
|
Added support for constant bit- or part-select for memory writes
|
2014-07-17 13:13:21 +02:00 |
Clifford Wolf
|
543551b80a
|
changes in verilog frontend for new $mem/$memwr WR_EN interface
|
2014-07-16 12:49:50 +02:00 |
Clifford Wolf
|
55a1b8dbac
|
Fixed processing of initial values for block-local variables
|
2014-07-11 13:05:53 +02:00 |
Clifford Wolf
|
076182c34e
|
Fixed handling of mixed real/int ternary expressions
|
2014-06-25 10:05:36 +02:00 |
Clifford Wolf
|
4fc43d1932
|
More found_real-related fixes to AstNode::detectSignWidthWorker
|
2014-06-24 15:08:48 +02:00 |
Clifford Wolf
|
65b2e9c064
|
fixed signdness detection for expressions with reals
|
2014-06-21 21:41:13 +02:00 |
Clifford Wolf
|
80e4594695
|
Added AstNode::MEM2REG_FL_CMPLX_LHS
|
2014-06-17 21:39:25 +02:00 |
Clifford Wolf
|
798ff88855
|
Improved handling of relational op of real values
|
2014-06-17 12:47:51 +02:00 |
Clifford Wolf
|
6c17d4f242
|
Improved ternary support for real values
|
2014-06-16 15:12:24 +02:00 |
Clifford Wolf
|
82bbd2f077
|
Use undef (x/z vs. NaN) rules for real values from IEEE Std 1800-2012
|
2014-06-16 15:05:37 +02:00 |
Clifford Wolf
|
5bfe865cec
|
Added found_real feature to AstNode::detectSignWidth
|
2014-06-16 15:00:57 +02:00 |
Clifford Wolf
|
4d1df128fa
|
Improved AstNode::realAsConst for large numbers
|
2014-06-15 09:27:09 +02:00 |
Clifford Wolf
|
48dc6ab98d
|
Improved AstNode::asReal for large integers
|
2014-06-15 08:38:31 +02:00 |
Clifford Wolf
|
149fe83a8d
|
improved (fixed) conversion of real values to bit vectors
|
2014-06-14 21:00:51 +02:00 |
Clifford Wolf
|
d5765b5e14
|
Fixed relational operators for const real expressions
|
2014-06-14 19:33:58 +02:00 |
Clifford Wolf
|
f3b4a9dd24
|
Added support for math functions
|
2014-06-14 13:36:23 +02:00 |
Clifford Wolf
|
9bd7d5c468
|
Added handling of real-valued parameters/localparams
|
2014-06-14 12:00:47 +02:00 |
Clifford Wolf
|
fc7b6d172a
|
Implemented more real arithmetic
|
2014-06-14 11:27:05 +02:00 |
Clifford Wolf
|
442a8e2875
|
Implemented basic real arithmetic
|
2014-06-14 08:51:22 +02:00 |
Clifford Wolf
|
9dd16fa41c
|
Added real->int convertion in ast genrtlil
|
2014-06-14 07:44:19 +02:00 |
Clifford Wolf
|
7ef0da32cd
|
Added Verilog lexer and parser support for real values
|
2014-06-13 11:29:23 +02:00 |
Clifford Wolf
|
e275e8eef9
|
Add support for cell arrays
|
2014-06-07 11:48:50 +02:00 |
Clifford Wolf
|
0b1ce63a19
|
Added support for repeat stmt in const functions
|
2014-06-07 10:47:53 +02:00 |
Clifford Wolf
|
7c8a7b2131
|
further improved const function support
|
2014-06-07 00:02:05 +02:00 |
Clifford Wolf
|
76da2fe172
|
improved const function support
|
2014-06-06 22:55:02 +02:00 |
Clifford Wolf
|
5c10d2ee36
|
fix functions with no block (but single statement, loop, etc.)
|
2014-06-06 21:29:23 +02:00 |
Clifford Wolf
|
ab54ce17c8
|
improved ast simplify of const functions
|
2014-06-06 17:40:45 +02:00 |
Clifford Wolf
|
b5cd7a0179
|
added while and repeat support to verilog parser
|
2014-06-06 17:40:04 +02:00 |
Clifford Wolf
|
09805ee9ec
|
Include id2ast pointers when dumping AST
|
2014-03-05 19:56:31 +01:00 |