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190 Commits

Author SHA1 Message Date
Clifford Wolf 1202f7aa4b Renamed "stdcells.v" to "techmap.v" 2014-07-31 02:32:00 +02:00
Clifford Wolf 10e5791c5e Refactoring: Renamed RTLIL::Design::modules to modules_ 2014-07-27 11:18:30 +02:00
Clifford Wolf 4c4b602156 Refactoring: Renamed RTLIL::Module::cells to cells_ 2014-07-27 01:51:45 +02:00
Clifford Wolf f9946232ad Refactoring: Renamed RTLIL::Module::wires to wires_ 2014-07-27 01:49:51 +02:00
Clifford Wolf b7dda72302 Changed users of cell->connections_ to the new API (sed command) 
git grep -l 'connections_' | xargs sed -i -r -e '
	s/(->|\.)connections_\["([^"]*)"\] = (.*);/\1set("\2", \3);/g;
	s/(->|\.)connections_\["([^"]*)"\]/\1get("\2")/g;
	s/(->|\.)connections_.at\("([^"]*)"\)/\1get("\2")/g;
	s/(->|\.)connections_.push_back/\1connect/g;
	s/(->|\.)connections_/\1connections()/g;'
 2014-07-26 15:58:23 +02:00
Clifford Wolf cc4f10883b Renamed RTLIL::{Module,Cell}::connections to connections_ 2014-07-26 11:58:03 +02:00
Clifford Wolf 3ec785b881 Fixed manual/CHAPTER_Prog/stubnets.cc 2014-07-23 19:36:43 +02:00
Clifford Wolf a62c21c9c6 Removed RTLIL::SigSpec::expand() method 2014-07-23 19:34:51 +02:00
Clifford Wolf 73e0e13d2f Changed the $mem/$memwr WR_EN input to a per-data-bit enable signal 2014-07-16 11:38:02 +02:00
Clifford Wolf 1c81ab49e7 small changes in presentation 2014-07-02 06:16:31 +02:00
Clifford Wolf d26561cc44 Tiny fix in presentation 2014-06-29 09:27:03 +02:00
Clifford Wolf 3a3f5d5923 Progress in presentation 2014-06-29 09:14:49 +02:00
Clifford Wolf 3e96ce8680 Progress in presentation 2014-06-26 22:05:39 +02:00
Clifford Wolf a7aea17959 Progress in presentation 2014-06-22 12:50:29 +02:00
Clifford Wolf 072604f30f fixed typo 2014-06-21 21:13:18 +02:00
Clifford Wolf b18fa95d2f Progress in presentation 2014-06-21 16:33:33 +02:00
Clifford Wolf 1a487303a0 Progress in presentation 2014-06-14 16:45:16 +02:00
Clifford Wolf 51a615b26d Progress in presentation 2014-05-06 14:42:04 +02:00
Anthony J. Bentley 154c9f8b51 Typos and grammar fixes through chapter 4. 2014-05-02 03:08:40 -06:00
Anthony J. Bentley 9c1e578afe Typos and grammar fixes through chapter 2. 2014-04-11 02:42:59 -06:00
Anthony J. Bentley 66a5da5edc POSIX find requires a path argument. 2014-04-04 16:51:27 -06:00
Clifford Wolf 79edcd4318 Progress in presentation 2014-02-21 14:59:59 +01:00
Clifford Wolf 2aff7b2a47 Progress in presentation 2014-02-21 02:13:02 +01:00
Clifford Wolf 9351e4d3ca Progress in presentation 2014-02-20 23:44:28 +01:00
Clifford Wolf b0e84802ec Progress in presentation 2014-02-20 20:44:41 +01:00
Clifford Wolf 98940260e1 Progress in presentation 2014-02-20 12:46:29 +01:00
Clifford Wolf 3d9da919d8 Progress in presentation 2014-02-18 19:51:03 +01:00
Clifford Wolf 0fbc1a59dd Progress in presentation 2014-02-17 09:45:04 +01:00
Clifford Wolf 37cbb1ca60 Progress in presentation 2014-02-16 22:31:53 +01:00
Clifford Wolf f08c71b96c Progress in presentation 2014-02-16 17:56:19 +01:00
Clifford Wolf aeb36b0b8b Progress in presentation 2014-02-16 14:32:56 +01:00
Clifford Wolf 9c29969bbc Progress in presentation 2014-02-16 13:45:47 +01:00
Clifford Wolf 4bd2d47e45 Improved "make manual" and "make clean" 2014-02-11 12:55:58 +01:00
Clifford Wolf fc3b3c4ec3 Added $slice and $concat cell types 2014-02-07 17:44:57 +01:00
Clifford Wolf 821156b6cf presentation progress 2014-02-06 14:01:43 +01:00
Clifford Wolf 7e9ba60df8 presentation progress 2014-02-05 20:06:34 +01:00
Clifford Wolf 3b5c462273 presentation progress 2014-02-05 15:06:13 +01:00
Clifford Wolf 9f6364c1c4 presentation progress 2014-02-05 13:12:50 +01:00
Clifford Wolf e0c867db53 presentation progress 2014-02-04 23:00:48 +01:00
Clifford Wolf 03d63dd861 presentation progress 2014-02-04 16:51:12 +01:00
Clifford Wolf 9e938aa32a presentation progress 2014-02-04 00:57:11 +01:00
Clifford Wolf 6c3d767976 presentation progress 2014-02-03 16:26:27 +01:00
Clifford Wolf a6750b3753 Added TRANSPARENT parameter to $memrd (and RD_TRANSPARENT to $mem) 2014-02-03 13:01:45 +01:00
Clifford Wolf 982c9da011 presentation progress 2014-02-02 22:26:26 +01:00
Clifford Wolf 6983d3f10b presentation progress 2014-02-02 17:57:14 +01:00
Clifford Wolf 0f88e28693 presentation progress 2014-02-02 13:30:49 +01:00
Clifford Wolf 9334c34170 presentation progress 2014-02-02 13:06:28 +01:00
Clifford Wolf 1c8f6f21b4 Progress on presentation 2014-01-31 12:48:31 +01:00
Clifford Wolf 36a808c572 presentation progress 2014-01-30 15:25:09 +01:00
Clifford Wolf 34b39ec28a presentation progress 2014-01-29 15:56:58 +01:00
Clifford Wolf cbe77bf844 presentation progress 2014-01-29 12:15:38 +01:00
Clifford Wolf 961b791272 presentation progress 2014-01-28 20:28:22 +01:00
Clifford Wolf 2cb47355d4 Renamed manual/FILES_* directories 2014-01-28 06:55:47 +01:00
Clifford Wolf 842ca2f011 Progress on presentation 2014-01-28 06:51:50 +01:00
Clifford Wolf a3ac6b6f47 Progress on presentation 2014-01-27 20:42:35 +01:00
Clifford Wolf fb4c3dff33 Added first presentation slides 2014-01-27 17:08:19 +01:00
Ahmed Irfan b7adf4c7a0 Merge branch 'master' of https://github.com/cliffordwolf/yosys into btor 2014-01-20 09:58:04 +01:00
Clifford Wolf 1e67099b77 Added $assert cell 2014-01-19 14:03:40 +01:00
Ahmed Irfan 06482c046b Merge branch 'master' of https://github.com/cliffordwolf/yosys into btor 2014-01-03 10:54:54 +01:00
Ahmed Irfan 5da334fc2e makefile 2014-01-03 10:54:30 +01:00
Clifford Wolf fb2bf934dc Added correct handling of $memwr priority 2014-01-03 00:22:17 +01:00
Clifford Wolf 74d0de3b74 Updated manual/command-reference-manual.tex 2013-12-28 12:14:47 +01:00
Clifford Wolf fe8ec32a1c Added new cell types to manual 2013-12-28 12:10:32 +01:00
Clifford Wolf 6069715c9e Finished AppNote 011 2013-12-08 15:12:32 +01:00
Clifford Wolf 0bd08688b8 Progress on AppNote 011 2013-12-08 15:08:51 +01:00
Clifford Wolf 1d000f9372 Progress on AppNote 011 2013-12-07 18:03:49 +01:00
Clifford Wolf 97aa421ad8 Progress on AppNote 011 2013-12-07 15:11:50 +01:00
Clifford Wolf cd0324decd Progress on AppNote 011 2013-12-07 11:58:55 +01:00
Clifford Wolf 8311492475 Fixed bug in example prog in appnote 011 2013-12-05 18:15:14 +01:00
Clifford Wolf 0f4055d4c6 Progress on AppNote 011 2013-12-02 12:54:21 +01:00
Clifford Wolf 73e28f0e39 Progress on AppNote 011 2013-12-01 14:07:44 +01:00
Clifford Wolf 7295b25955 Progress on AppNote 011 2013-11-29 16:42:49 +01:00
Clifford Wolf e23a0072ec Progress on AppNote 011 2013-11-29 12:51:16 +01:00
Clifford Wolf f89ecbc100 Progress on AppNote 011 2013-11-28 23:09:03 +01:00
Clifford Wolf 9595eca181 More progress on AppNote 011 2013-11-28 17:39:16 +01:00
Clifford Wolf 6dfb66d262 Started writing appnote 011 2013-11-28 13:48:38 +01:00
Clifford Wolf a4edecb0ca Updated command-reference-manual.tex 2013-11-23 20:09:47 +01:00
Clifford Wolf db8ce0fe95 AppNote 010 typo fixes and corrections 2013-11-23 20:04:51 +01:00
Clifford Wolf e216e0e291 AppNote 010 progress 2013-11-23 18:52:41 +01:00
Clifford Wolf 9ab850e45e Making prograss on Appnote 010 2013-11-23 05:46:51 +01:00
Clifford Wolf 3c023054bc Progress on AppNote 010 2013-11-22 19:08:29 +01:00
Clifford Wolf bf501b9ba3 Started to write on AppNote 010: Verilog to BLIF 2013-11-22 17:33:59 +01:00
Clifford Wolf 7b9ca46f8d Updated command-reference-manual.tex 2013-11-22 15:02:40 +01:00
Clifford Wolf 7ea7342c18 Large improvements in yosys-config 2013-11-19 23:04:27 +01:00
Clifford Wolf 288ba9618a Moved common techlib files to techlibs/common 2013-09-15 11:52:57 +02:00
Clifford Wolf 647c23b7b7 Updated manual 2013-09-15 11:41:05 +02:00
Clifford Wolf 3f5d7df603 Added stubnets example to manual prog chapter 2013-08-07 02:19:35 +02:00
Clifford Wolf 98906b211c Fixed comments in manual rtlil/ilang syntax 2013-07-25 15:01:02 +02:00
Clifford Wolf 36c39cbd04 Added RTLIL and Liberty syntax highlighting to manual 2013-07-25 14:00:16 +02:00
Clifford Wolf 61ed6b32d1 Added Yosys Manual 2013-07-20 15:19:12 +02:00