mirror of https://github.com/YosysHQ/yosys.git
Progress in presentation
This commit is contained in:
Clifford Wolf
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3e96ce8680
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@ -94,7 +94,7 @@ tool for interactive design investigation.
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\subsubsection{Selecting by object property or type}
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\begin{frame}[fragile]{\subsubsecname}
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Special pattern can be used to select by object property or type. For example:
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Special patterns can be used to select by object property or type. For example:
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\bigskip
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\begin{lstlisting}[xleftmargin=0.5cm, basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=ys]
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@ -113,7 +113,7 @@ reference to the {\tt select} command.
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\subsubsection{Combining selection}
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\begin{frame}[fragile]{\subsubsecname}
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When more than one selection expression is used in one statement they are
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When more than one selection expression is used in one statement, then they are
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pushed on a stack. The final elements on the stack are combined into a union:
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\medskip
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@ -169,7 +169,7 @@ See {\tt help select} for full documentation of this expressions.
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\subsubsection{Incremental selection}
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\begin{frame}[fragile]{\subsubsecname}
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Sometime a selection can most easily described by a series of add/delete operations.
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Sometimes a selection can most easily be described by a series of add/delete operations.
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The commands {\tt select -add} and {\tt select -del} respectively add or remove objects
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from the current selection instead of overwriting it.
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@ -28,7 +28,7 @@ from other tools).
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\begin{itemize}
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\item
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The selection mechanism (see slides ``Using Selections''), especially pattern such
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The selection mechanism (see slides ``Using Selections''), especially patterns such
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as {\tt \%ci} and {\tt \%co}, can be used to figure out how parts of the design
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are connected.
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@ -53,9 +53,9 @@ read_verilog scrambler.v
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hierarchy; proc;;
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cd scrambler
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submod -name xorshift32 xs %c %ci %D \
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%c %ci:+[D] %D %ci*:-$dff \
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xs %co %ci %d
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submod -name xorshift32 \
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xs %c %ci %D %c %ci:+[D] %D \
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%ci*:-$dff xs %co %ci %d
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\end{lstlisting}
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\end{columns}
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@ -12,7 +12,7 @@
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\begin{frame}{\subsecname}
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\begin{itemize}
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\item Reading and elaborating the design
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\item High-level synthesis and optimization
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\item Higher-level synthesis and optimization
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\begin{itemize}
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\item Converting {\tt always}-blocks to logic and registers
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\item Perform coarse-grain optimizations (resource sharing, const folding, ...)
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@ -21,7 +21,7 @@
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\end{itemize}
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\item Convert remaining logic to bit-level logic functions
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\item Perform optimizations on bit-level logic functions
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\item Map bit-level logic and register to gates from cell library
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\item Map bit-level logic gates and registers to cell library
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\item Write results to output file
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\end{itemize}
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\end{frame}
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@ -64,8 +64,8 @@ all needed variations of parametric modules.
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#
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hierarchy
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# recommended form. fail if parts of the design hierarchy are missing. remove
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# everything that is unreachable by the top module. mark the top module.
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# recommended form. fails if parts of the design hierarchy are missing, removes
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# everything that is unreachable from the top module, and marks the top module.
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#
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hierarchy -check -top top_module
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\end{lstlisting}
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@ -253,7 +253,7 @@ memory_dff
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# into one multi-port memory cell.
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memory_collect
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# this takes the multi-port memory cells and transforms it to address decoder
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# this takes the multi-port memory cell and transforms it to address decoder
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# logic and registers. This step is skipped if "memory" is called with -nomap.
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memory_map
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\end{lstlisting}
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@ -279,7 +279,7 @@ memory -nomap; techmap -map my_memory_map.v; memory_map
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\end{frame}
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\begin{frame}[t, fragile]{\subsecname{} -- Example 2/2}
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\vbox to 0cm{\hfill\includegraphics[width=7.5cm,trim=0cm 0cm 0cm -6cm]{PRESENTATION_ExSyn/memory_02.pdf}\vss}
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\vbox to 0cm{\hfill\includegraphics[width=7.5cm,trim=0cm 0cm 0cm -5cm]{PRESENTATION_ExSyn/memory_02.pdf}\vss}
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\vskip-1cm
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\begin{columns}
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\column[t]{5cm}
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@ -303,11 +303,11 @@ fsm_detect # unless got option -nodetect
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fsm_extract
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fsm_opt
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opt_clean
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clean
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fsm_opt
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fsm_expand # if got option -expand
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opt_clean # if got option -expand
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clean # if got option -expand
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fsm_opt # if got option -expand
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fsm_recode # unless got option -norecode
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@ -366,7 +366,7 @@ When {\tt techmap} is used without a map file, it uses a built-in map file
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to map all RTL cell types to a generic library of built-in logic gates and registers.
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\bigskip
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\begin{block}{The build-in logic gate types are:}
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\begin{block}{The built-in logic gate types are:}
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{\tt \$\_INV\_ \$\_AND\_ \$\_OR\_ \$\_XOR\_ \$\_MUX\_}
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\end{block}
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@ -496,7 +496,7 @@ the next part (Section 3, ``Advanced Synthesis'') of this presentation.}
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\begin{itemize}
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\item Yosys provides commands for each phase of the synthesis.
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\item Each command solves a (more or less) simple problem.
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\item Complex command are often only front-ends to simple commands.
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\item Complex commands are often only front-ends to simple commands.
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\item {\tt proc; opt; memory; opt; fsm; opt; techmap; opt; abc;;}
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\end{itemize}
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@ -5,6 +5,7 @@
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\sectionpage
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\end{frame}
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\iffalse
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%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
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\subsection{Representations of (digital) Circuits}
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@ -51,6 +52,7 @@
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\end{frame}
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%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
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\fi
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\subsection{Levels of Abstraction for Digital Circuits}
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@ -74,7 +76,7 @@
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\only<6>{Physical Gate Level}%
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\only<7>{Switch Level}}
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\only<1>{
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Overall view of the circuit: E.g. block-diagrams or instruction-set architecture descriptions
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Overall view of the circuit. E.g. block-diagrams or instruction-set architecture descriptions.
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}%
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\only<2>{
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Functional implementation of circuit in high-level programming language (C, C++, SystemC, Matlab, Python, etc.).
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@ -94,7 +96,7 @@
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\only<6>{
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Netlist of cells that actually are available on the target architecture
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(such as CMOS gates in an ASCI or LUTs in an FPGA). Optimized for
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area and/or and/or speed (static timing or number of logic levels).
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area, power, and/or speed (static timing or number of logic levels).
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}%
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\only<7>{
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Netlist of individual transistors.
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@ -179,8 +181,8 @@ as Qflow\footnote[frame]{\url{http://opencircuitdesign.com/qflow/}} for ASIC des
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This scripts contain three types of commands:
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\begin{itemize}
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\item {\bf Frontends}, that read input files (usually Verilog).
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\item {\bf Passes}, that perform transformation on the design in memory.
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\item {\bf Backends}, that write the design in memory to a file (various formats are available, e.g. Verilog, BLIF, EDIF, SPICE, BTOR, etc.).
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\item {\bf Passes}, that perform transformations on the design in memory.
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\item {\bf Backends}, that write the design in memory to a file (various formats are available: Verilog, BLIF, EDIF, SPICE, BTOR, \dots).
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\end{itemize}
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\bigskip
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@ -247,26 +249,23 @@ as Qflow\footnote[frame]{\url{http://opencircuitdesign.com/qflow/}} for ASIC des
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%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
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\subsection{Example Problem}
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\subsection{Example Project}
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\begin{frame}[fragile]{\subsecname{} -- Verilog Source: \tt counter.v}
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\lstinputlisting[xleftmargin=1cm, language=Verilog]{PRESENTATION_Intro/counter.v}
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\end{frame}
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\begin{frame}[fragile]{\subsecname{} -- Cell Library: \tt mycells.lib}
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\begin{columns}
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\column[t]{5cm}
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\lstinputlisting[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=liberty, lastline=20]{PRESENTATION_Intro/mycells.lib}
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\column[t]{5cm}
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\lstinputlisting[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=liberty, firstline=21]{PRESENTATION_Intro/mycells.lib}
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\end{columns}
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\begin{frame}[t]{\subsecname}
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The following slides cover an example project. This project contains three files:
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\begin{itemize}
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\item A simple ASIC synthesis script
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\item A digital design written in Verilog
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\item A simple CMOS cell library
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\end{itemize}
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\vfill
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Direct link to the files: \\ \footnotesize
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\url{https://github.com/cliffordwolf/yosys/tree/master/manual/PRESENTATION_Intro}
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\end{frame}
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%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
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\subsection{Example Synthesis Script}
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\begin{frame}[t]{\subsecname}
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\begin{frame}[t]{\subsecname{} -- Synthesis Script}
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\setbeamercolor{alerted text}{fg=white,bg=red}
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@ -283,9 +282,6 @@ as Qflow\footnote[frame]{\url{http://opencircuitdesign.com/qflow/}} for ASIC des
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\medskip
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{\color{YosysGreen}\# mapping to internal cell library}\\
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\boxalert<9>{techmap}; \boxalert<10>{opt}
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\bigskip
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\it continued\dots
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\end{minipage}
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\begin{minipage}[t]{5cm}
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\tt\scriptsize
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@ -327,7 +323,7 @@ as Qflow\footnote[frame]{\url{http://opencircuitdesign.com/qflow/}} for ASIC des
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}%
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\only<2>{
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Elaborate the design hierarchy. Should always be the first
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command after reading the design.
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command after reading the design. Can re-run AST front-end.
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}%
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\only<3>{
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Convert ``processes'' (the internal representation of behavioral
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@ -373,6 +369,21 @@ as Qflow\footnote[frame]{\url{http://opencircuitdesign.com/qflow/}} for ASIC des
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%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
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\begin{frame}[fragile]{\subsecname{} -- Verilog Source: \tt counter.v}
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\lstinputlisting[xleftmargin=1cm, language=Verilog]{PRESENTATION_Intro/counter.v}
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\end{frame}
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\begin{frame}[fragile]{\subsecname{} -- Cell Library: \tt mycells.lib}
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\begin{columns}
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\column[t]{5cm}
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\lstinputlisting[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=liberty, lastline=20]{PRESENTATION_Intro/mycells.lib}
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\column[t]{5cm}
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\lstinputlisting[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=liberty, firstline=21]{PRESENTATION_Intro/mycells.lib}
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\end{columns}
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\end{frame}
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%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
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\subsection{Running the Synthesis Script}
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\begin{frame}[t, fragile]{\subsecname{} -- Step 1/4}
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@ -410,8 +421,8 @@ abc -liberty mycells.lib
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clean
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\end{verbatim}
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\vfill
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\includegraphics[width=\linewidth,trim=0 0cm 0 0cm]{PRESENTATION_Intro/counter_03.pdf}
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\vfill\hfil
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\includegraphics[width=10cm,trim=0 0cm 0 0cm]{PRESENTATION_Intro/counter_03.pdf}
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\end{frame}
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%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
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@ -422,7 +433,7 @@ clean
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Command reference:
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\begin{itemize}
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\item Use ``{\tt help}'' for a command list and ``{\tt help \it command}'' for details.
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\item Or run ``{\tt yosys -H}'' and ``{\tt yosys -h \it command}''.
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\item Or run ``{\tt yosys -H}'' or ``{\tt yosys -h \it command}''.
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\item Or go to \url{http://www.clifford.at/yosys/documentation.html}.
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\end{itemize}
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@ -560,7 +571,7 @@ endmodule
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module cam(clk, wr_enable, wr_addr, wr_data, rd_data, rd_addr, rd_match);
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parameter WIDTH = 8;
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parameter DEPTH = 16;
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localparam ADDR_BITS = $clog2(DEPTH);
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localparam ADDR_BITS = $clog2(DEPTH-1);
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input clk, wr_enable;
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input [ADDR_BITS-1:0] wr_addr;
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@ -595,7 +606,7 @@ Contiously checking the correctness of Yosys and making sure that new features
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do not break old ones is a high priority in Yosys.
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\bigskip
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There are two external test suites build for Yosys: VlogHammer and yosys-bigsim
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Two external test suites have been built for Yosys: VlogHammer and yosys-bigsim
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(see next slides)
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\bigskip
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@ -608,8 +619,8 @@ the internal state after each command.
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\begin{frame}[fragile]{\subsecname{} -- VlogHammer}
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VlogHammer is a Verilog regression test suite developed to test the different
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subsystems in Yosys by comparing them to each other and the implementations
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generated by some proprietary tools (Xilinx Vivado, Xilinx XST, Altera Quartus II, ...).
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subsystems in Yosys by comparing them to each other and to the output created
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by some other tools (Xilinx Vivado, Xilinx XST, Altera Quartus II, ...).
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\bigskip
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Yosys Subsystems tested: Verilog frontend, const folding, const eval, technology mapping,
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@ -624,8 +635,8 @@ assign y11 = (~&(-{(-3'sd3),($unsigned($signed($unsigned({p0,b4,b1}))))}));
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\end{lstlisting}
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\bigskip
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Some bugs in Yosys where found and fixed thanks to VlogHammer. Over 20 bugs in
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the proprietary tools used as external reference where found and reported.
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Some bugs in Yosys where found and fixed thanks to VlogHammer. Over 50 bugs in
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the other tools used as external reference where found and reported so far.
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\end{frame}
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\begin{frame}{\subsecname{} -- yosys-bigsim}
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@ -634,7 +645,7 @@ benches. yosys-bigsim compares the testbench outpus of simulations of the origin
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Verilog code and synthesis results.
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\bigskip
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The following designs are part of yosys-bigsim:
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The following designs are included in yosys-bigsim (excerpt):
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\begin{itemize}
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\item {\tt openmsp430} -- an MSP430 compatible 16 bit CPU
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\item {\tt aes\_5cycle\_2stage} -- an AES encryption core
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@ -651,6 +662,19 @@ The following designs are part of yosys-bigsim:
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\subsection{Benefits of Open Source HDL Synthesis}
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\begin{frame}{\subsecname}
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\begin{itemize}
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\item Cost (also applies to ``free as in free beer'' solutions)
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\item Availablity and Reproducability
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\item Framework- and all-in-one-aspects
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\item Educational Tool
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\end{itemize}
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\bigskip
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Yosys is open source under the ISC license.
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\end{frame}
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\begin{frame}{\subsecname{} -- 1/3}
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\begin{itemize}
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\item Cost (also applies to ``free as in free beer'' solutions): \smallskip\par
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@ -688,14 +712,13 @@ learn a new tool for each of this applications.
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\begin{frame}{\subsecname{} -- 3/3}
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\begin{itemize}
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\item Educational Tool: \smallskip\par
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Propritaery synthesis tools are at times where secretive about their inner
|
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workings. They often are ``black boxes'' where a design goes in and synthesis
|
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results come out. Yosys is very open about its internals and it is easy to
|
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observe the different steps of synthesis.
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Propritaery synthesis tools are at times very secretive about their inner
|
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workings. They often are ``black boxes''. Yosys is very open about its
|
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internals and it is easy to observe the different steps of synthesis.
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\end{itemize}
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\bigskip
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\begin{block}{BTW: Yosys is licensed under the ISC license:}
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\begin{block}{Yosys is licensed under the ISC license:}
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Permission to use, copy, modify, and/or distribute this software for any
|
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purpose with or without fee is hereby granted, provided that the above
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copyright notice and this permission notice appear in all copies.
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@ -743,24 +766,24 @@ but also formal verification, reverse engineering, ...}
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%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
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\subsection{What the Yosys project needs from you}
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\subsection{Yosys needs you}
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\begin{frame}{\subsecname}
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We need you as an active user:
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\dots as an active user:
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\begin{itemize}
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\item Use Yosys for on your own designs
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\item Use Yosys for on your own projects
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\item .. even if you are not using it as final synthesis tool
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\item Join the discussion on the Subreddit
|
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\item Report bugs and send in feature requests
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\end{itemize}
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\bigskip
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We need you as a developer:
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\dots as a developer:
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\begin{itemize}
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\item Use Yosys as environment for your research work
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\item Use Yosys as environment for your (research) work
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\item .. you might also want to look into ABC for logic-level stuff
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\item Fork the project on github or create loadable plugins
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\item We desperately need a VHDL frontend or a VHDL-to-Verilog converter
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\item We need a VHDL frontend or a good VHDL-to-Verilog converter
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\end{itemize}
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\end{frame}
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|
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@ -2,17 +2,18 @@
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read_verilog counter.v
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hierarchy -check -top counter
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show -stretch -format pdf -prefix counter_00
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show -notitle -stretch -format pdf -prefix counter_00
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# the high-level stuff
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proc; opt; memory; opt; fsm; opt
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show -stretch -format pdf -prefix counter_01
|
||||
show -notitle -stretch -format pdf -prefix counter_01
|
||||
|
||||
# mapping to internal cell library
|
||||
techmap; splitnets -ports; opt
|
||||
techmap; opt
|
||||
|
||||
show -stretch -format pdf -prefix counter_02
|
||||
splitnets -ports;;
|
||||
show -notitle -stretch -format pdf -prefix counter_02
|
||||
|
||||
# mapping flip-flops to mycells.lib
|
||||
dfflibmap -liberty mycells.lib
|
||||
|
|
@ -23,4 +24,4 @@ abc -liberty mycells.lib
|
|||
# cleanup
|
||||
clean
|
||||
|
||||
show -stretch -lib mycells.v -format pdf -prefix counter_03
|
||||
show -notitle -stretch -lib mycells.v -format pdf -prefix counter_03
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
|
||||
\section{Programming Yosys Extensions}
|
||||
\section{Writing Yosys extensions in C++}
|
||||
|
||||
\begin{frame}
|
||||
\sectionpage
|
||||
|
|
@ -43,8 +43,9 @@
|
|||
\subsection{Simplified RTLIL Entity-Relationship Diagram}
|
||||
|
||||
\begin{frame}{\subsecname}
|
||||
Between passses and frontends/backends the design in stored in Yosys' internal RTLIL (RTL Intermediate Language) format. For
|
||||
writing Yosys extensions it is key to understand this format.
|
||||
Between passses and frontends/backends the design is stored in Yosys' internal
|
||||
RTLIL (RTL Intermediate Language) format. For writing Yosys extensions it is
|
||||
key to understand this format.
|
||||
|
||||
\bigskip
|
||||
\begin{center}
|
||||
|
|
@ -71,7 +72,8 @@ writing Yosys extensions it is key to understand this format.
|
|||
\subsection{RTLIL without memories and processes}
|
||||
|
||||
\begin{frame}[fragile]{\subsecname}
|
||||
After the command {\tt proc} and {\tt memory} (or {\tt memory -nomap}), we are left with a much simpler version of RTLIL:
|
||||
After the commands {\tt proc} and {\tt memory} (or {\tt memory -nomap}), we are
|
||||
left with a much simpler version of RTLIL:
|
||||
|
||||
\begin{center}
|
||||
\begin{tikzpicture}[scale=0.6, every node/.style={transform shape}]
|
||||
|
|
@ -85,7 +87,7 @@ After the command {\tt proc} and {\tt memory} (or {\tt memory -nomap}), we are l
|
|||
\end{center}
|
||||
|
||||
\bigskip
|
||||
Many command simply choose to only work on this simpler version:
|
||||
Many commands simply choose to only work on this simpler version:
|
||||
\begin{lstlisting}[xleftmargin=0.5cm, basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont]
|
||||
if (module->processes.size() != 0 || module->memories.size() != 0)
|
||||
log_error("This command does not operate on modules with processes "
|
||||
|
|
@ -256,7 +258,7 @@ a {\tt RTLIL::SigChunk}:
|
|||
\begin{lstlisting}[xleftmargin=1cm, basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=C++]
|
||||
struct RTLIL::SigChunk {
|
||||
RTLIL::Wire *wire;
|
||||
RTLIL::Const data; // only used if wire == NULL, LSB at index 0
|
||||
RTLIL::Const data; // only used if wire == NULL
|
||||
int width, offset;
|
||||
...
|
||||
};
|
||||
|
|
@ -276,7 +278,7 @@ manipulate instances of {\tt RTLIL::SigSpec}.
|
|||
\subsubsection{The RTLIL::Cell Structure}
|
||||
|
||||
\begin{frame}[t, fragile]{\subsubsecname (1/2)}
|
||||
The {\tt RTLIL::Cell} strcut represents an instance of a module or library cell.
|
||||
The {\tt RTLIL::Cell} struct represents an instance of a module or library cell.
|
||||
|
||||
\smallskip
|
||||
The ports of the cell
|
||||
|
|
@ -310,7 +312,7 @@ $_DLATCHSR_NPN_ $_DLATCHSR_NPP_ $_DLATCHSR_PNN_ $_DLATCHSR_PNP_ $_DLATCHSR_PPN_
|
|||
\end{frame}
|
||||
|
||||
\begin{frame}[t, fragile]{\subsubsecname (2/2)}
|
||||
Simulation models (i.e. {\it documentation\/}) for the internal cell library:
|
||||
Simulation models (i.e. {\it documentation\/} :-) for the internal cell library:
|
||||
|
||||
\smallskip
|
||||
\hskip2em {\tt yosys/techlibs/common/simlib.v} and \\
|
||||
|
|
@ -318,11 +320,11 @@ Simulation models (i.e. {\it documentation\/}) for the internal cell library:
|
|||
|
||||
\bigskip
|
||||
The lower-case cell types (such as {\tt \$and}) are parameterized cells of variable
|
||||
width. This so-called {\it RTL cells\/} are the cells described in {\tt simlib.v}.
|
||||
width. This so-called {\it RTL Cells\/} are the cells described in {\tt simlib.v}.
|
||||
|
||||
\bigskip
|
||||
The upper-case cell types (such as {\tt \$\_AND\_}) single-bit cells that are not
|
||||
parameterized. This so-called {\it internal Logic Gates} are the cells described
|
||||
The upper-case cell types (such as {\tt \$\_AND\_}) are single-bit cells that are not
|
||||
parameterized. This so-called {\it Internal Logic Gates} are the cells described
|
||||
in {\tt simcells.v}.
|
||||
|
||||
\bigskip
|
||||
|
|
|
|||
|
|
@ -81,7 +81,7 @@
|
|||
|
||||
\title{Yosys Open SYnthesis Suite}
|
||||
\author{Clifford Wolf}
|
||||
\institute{http://www.clifford.at/}
|
||||
\institute{http://www.clifford.at/yosys/}
|
||||
|
||||
\usetheme{Madrid}
|
||||
\usecolortheme{seagull}
|
||||
|
|
@ -133,7 +133,7 @@ Outline of this presentation:
|
|||
\item Yosys by example: synthesis
|
||||
\item Yosys by example: advanced synthesis
|
||||
\item Yosys by example: beyond synthesis
|
||||
\item Programming Yosys extensions
|
||||
\item Writing Yosys extensions in C++
|
||||
\end{itemize}
|
||||
\end{frame}
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue