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presentation progress

This commit is contained in:
Clifford Wolf 2014-01-29 15:56:58 +01:00
parent cbe77bf844
commit 34b39ec28a
2 changed files with 36 additions and 4 deletions
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32
manual/PRESENTATION_Intro.tex
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@ -374,3 +374,35 @@ clean
\includegraphics[width=\linewidth,trim=0 0cm 0 0cm]{PRESENTATION_Intro/counter_03.pdf}
\end{frame}
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
\subsection{More Yosys Commands}
\begin{frame}{\subsecname{} -- TBD}
TBD
\end{frame}
\subsection{More Verilog Examples}
\begin{frame}{\subsecname{} -- TBD}
TBD
\end{frame}
\subsection{Verification}
\begin{frame}{\subsecname{} -- VlogHammer}
TBD
\end{frame}
\begin{frame}{\subsecname{} -- yosys-bigsim}
TBD
\end{frame}
\subsection{Benefits of Open Source HDL Synthesis}
\begin{frame}{\subsecname}
TBD
\end{frame}
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%

8
manual/PRESENTATION_Intro/counter.ys
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@ -2,17 +2,17 @@
read_verilog counter.v
hierarchy -check -top counter
show -format pdf -prefix counter_00
show -stretch -format pdf -prefix counter_00
# the high-level stuff
proc; opt; memory; opt; fsm; opt
show -format pdf -prefix counter_01
show -stretch -format pdf -prefix counter_01
# mapping to internal cell library
techmap; splitnets -ports; opt
show -format pdf -prefix counter_02
show -stretch -format pdf -prefix counter_02
# mapping flip-flops to mycells.lib
dfflibmap -liberty mycells.lib
@ -23,4 +23,4 @@ abc -liberty mycells.lib
# cleanup
clean
show -lib mycells.v -format pdf -prefix counter_03
show -stretch -lib mycells.v -format pdf -prefix counter_03