mirror of https://github.com/YosysHQ/yosys.git
Progress in presentation
This commit is contained in:
Clifford Wolf
parent
9351e4d3ca
commit
2aff7b2a47
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@ -561,6 +561,157 @@ $\downarrow$ & $\downarrow$ \\
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TBD
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\end{frame}
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\subsubsection{Example: DSP48\_MACC}
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\begin{frame}[fragile]{\subsubsecname{} -- ?/?}
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\hfil\begin{tabular}{cc}
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{\tt test1} & {\tt test2} \\
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\fbox{\hbox to 5cm {\lstinputlisting[linewidth=5cm, basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, firstline=1, lastline=6, language=verilog]{PRESENTATION_ExAdv/macc_xilinx_test.v}}} &
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\fbox{\hbox to 5cm {\lstinputlisting[linewidth=5cm, basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, firstline=8, lastline=13, language=verilog]{PRESENTATION_ExAdv/macc_xilinx_test.v}}} \\
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$\downarrow$ & $\downarrow$ \\
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\end{tabular}
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\vskip-0.5cm
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\begin{lstlisting}[linewidth=5cm, basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=ys]
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read_verilog macc_xilinx_test.v
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hierarchy -check
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\end{lstlisting}
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\vskip-0.5cm
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\hfil\begin{tabular}{cc}
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$\downarrow$ & $\downarrow$ \\
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\fbox{\includegraphics[width=5cm,trim=1.5cm 1.5cm 1.5cm 1.5cm]{PRESENTATION_ExAdv/macc_xilinx_test1a.pdf}} &
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\fbox{\includegraphics[width=5cm,trim=1.5cm 1.5cm 1.5cm 1.5cm]{PRESENTATION_ExAdv/macc_xilinx_test2a.pdf}} \\
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\end{tabular}
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\end{frame}
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\begin{frame}[fragile]{\subsubsecname{} -- ?/?}
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\hfil\begin{tabular}{cc}
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{\tt test1} & {\tt test2} \\
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\fbox{\includegraphics[width=5cm,trim=1.5cm 1.5cm 1.5cm 1.5cm]{PRESENTATION_ExAdv/macc_xilinx_test1a.pdf}} &
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\fbox{\includegraphics[width=5cm,trim=1.5cm 1.5cm 1.5cm 1.5cm]{PRESENTATION_ExAdv/macc_xilinx_test2a.pdf}} \\
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$\downarrow$ & $\downarrow$ \\
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\end{tabular}
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\vskip-0.2cm
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\begin{lstlisting}[linewidth=5cm, basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=ys]
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techmap -map macc_xilinx_swap_map.v ;;
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\end{lstlisting}
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\vskip-0.2cm
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\hfil\begin{tabular}{cc}
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$\downarrow$ & $\downarrow$ \\
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\fbox{\includegraphics[width=5cm,trim=1.5cm 1.5cm 1.5cm 1.5cm]{PRESENTATION_ExAdv/macc_xilinx_test1b.pdf}} &
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\fbox{\includegraphics[width=5cm,trim=1.5cm 1.5cm 1.5cm 1.5cm]{PRESENTATION_ExAdv/macc_xilinx_test2b.pdf}} \\
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\end{tabular}
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\end{frame}
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\begin{frame}[t, fragile]{\subsubsecname{} -- ?/?}
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Wrapping in {\tt test1}:
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\begin{columns}
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\column[t]{5cm}
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\vbox to 0cm{\fbox{\includegraphics[width=4.5cm,trim=1.5cm 1.5cm 1.5cm 1.5cm]{PRESENTATION_ExAdv/macc_xilinx_test1b.pdf}}\vss}
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\column[t]{6cm}
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\begin{lstlisting}[linewidth=5cm, basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=ys]
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techmap -map macc_xilinx_wrap_map.v
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connwrappers -unsigned $__mul_wrapper \
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Y Y_WIDTH \
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-unsigned $__add_wrapper \
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Y Y_WIDTH ;;
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\end{lstlisting}
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\end{columns}
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\vskip1cm
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\hfil\includegraphics[width=\linewidth,trim=1.5cm 1.5cm 1.5cm 1.5cm]{PRESENTATION_ExAdv/macc_xilinx_test1c.pdf}
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\end{frame}
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\begin{frame}[t, fragile]{\subsubsecname{} -- ?/?}
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Wrapping in {\tt test2}:
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\begin{columns}
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\column[t]{5cm}
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\vbox to 0cm{\fbox{\includegraphics[width=4.5cm,trim=1.5cm 1.5cm 1.5cm 1.5cm]{PRESENTATION_ExAdv/macc_xilinx_test2b.pdf}}\vss}
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\column[t]{6cm}
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\begin{lstlisting}[linewidth=5cm, basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=ys]
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techmap -map macc_xilinx_wrap_map.v
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connwrappers -unsigned $__mul_wrapper \
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Y Y_WIDTH \
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-unsigned $__add_wrapper \
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Y Y_WIDTH ;;
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\end{lstlisting}
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\end{columns}
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\vskip1cm
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\hfil\includegraphics[width=\linewidth,trim=1.5cm 1.5cm 1.5cm 1.5cm]{PRESENTATION_ExAdv/macc_xilinx_test2c.pdf}
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\end{frame}
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\begin{frame}[t, fragile]{\subsubsecname{} -- ?/?}
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Extract in {\tt test1}:
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\begin{columns}
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\column[t]{4.5cm}
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\vbox to 0cm{
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\begin{lstlisting}[linewidth=5cm, basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=ys]
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design -push
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read_verilog macc_xilinx_xmap.v
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techmap -map macc_xilinx_swap_map.v
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techmap -map macc_xilinx_wrap_map.v;;
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design -save __macc_xilinx_xmap
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design -pop
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\end{lstlisting}
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\vss}
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\column[t]{5.5cm}
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\vskip-1cm
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\begin{lstlisting}[linewidth=5.5cm, basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=ys]
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extract -constports -ignore_parameters \
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-map %__macc_xilinx_xmap \
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-swap $__add_wrapper A,B ;;
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\end{lstlisting}
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\vbox to 0cm{\fbox{\includegraphics[width=4.5cm,trim=1.5cm 1.5cm 1.5cm 1.5cm]{PRESENTATION_ExAdv/macc_xilinx_test1c.pdf}}\vss}
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\end{columns}
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\vskip2cm
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\hfil\includegraphics[width=11cm,trim=1.5cm 1.5cm 1.5cm 1.5cm]{PRESENTATION_ExAdv/macc_xilinx_test1d.pdf}
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\end{frame}
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\begin{frame}[t, fragile]{\subsubsecname{} -- ?/?}
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Extract in {\tt test2}:
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\begin{columns}
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\column[t]{4.5cm}
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\vbox to 0cm{
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\begin{lstlisting}[linewidth=5cm, basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=ys]
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design -push
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read_verilog macc_xilinx_xmap.v
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techmap -map macc_xilinx_swap_map.v
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techmap -map macc_xilinx_wrap_map.v;;
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design -save __macc_xilinx_xmap
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design -pop
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\end{lstlisting}
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\vss}
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\column[t]{5.5cm}
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\vskip-1cm
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\begin{lstlisting}[linewidth=5.5cm, basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=ys]
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extract -constports -ignore_parameters \
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-map %__macc_xilinx_xmap \
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-swap $__add_wrapper A,B ;;
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\end{lstlisting}
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\vbox to 0cm{\fbox{\includegraphics[width=4.5cm,trim=1.5cm 1.5cm 1.5cm 1.5cm]{PRESENTATION_ExAdv/macc_xilinx_test2c.pdf}}\vss}
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\end{columns}
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\vskip2cm
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\hfil\includegraphics[width=11cm,trim=1.5cm 1.5cm 1.5cm 1.5cm]{PRESENTATION_ExAdv/macc_xilinx_test2d.pdf}
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\end{frame}
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\begin{frame}[t, fragile]{\subsubsecname{} -- ?/?}
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Unwrap in {\tt test2}:
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\hfil\begin{tikzpicture}
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\node at (1,-1.7) {\begin{lstlisting}[linewidth=5.5cm, frame=single, basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=ys]
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techmap -map macc_xilinx_unwrap_map.v ;;
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\end{lstlisting}};
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\node at (0,0) {\includegraphics[width=11cm,trim=1.5cm 1.5cm 1.5cm 1.5cm]{PRESENTATION_ExAdv/macc_xilinx_test2d.pdf}};
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\node at (0,-4) {\includegraphics[width=11cm,trim=1.5cm 1.5cm 1.5cm 1.5cm]{PRESENTATION_ExAdv/macc_xilinx_test2e.pdf}};
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\draw[-latex] (4,-0.7) .. controls (5,-1.7) .. (4,-2.7);
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\end{tikzpicture}
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\end{frame}
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%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
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\subsection{Automatic design changes}
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@ -1,6 +1,6 @@
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all: select.pdf red_or3x1.pdf sym_mul.pdf mymul.pdf mulshift.pdf addshift.pdf \
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macc_simple_xmap.pdf
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macc_simple_xmap.pdf macc_xilinx_xmap.pdf
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select.pdf: select.v select.ys
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../../yosys select.ys
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@ -23,3 +23,6 @@ addshift.pdf: addshift_*
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macc_simple_xmap.pdf: macc_simple_*.v macc_simple_test.ys
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../../yosys macc_simple_test.ys
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macc_xilinx_xmap.pdf: macc_xilinx_*.v macc_xilinx_test.ys
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../../yosys macc_xilinx_test.ys
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@ -8,6 +8,7 @@ show -prefix macc_simple_test_00b -format pdf -notitle -lib macc_simple_xmap.v
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#################################################
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design -reset
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read_verilog macc_simple_test_01.v
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hierarchy -check -top test;;
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@ -1,13 +1,13 @@
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module test1(a, b, c, d, e, f, y);
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input [19:0] a, b, c;
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input [15:0] d, e, f;
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output [41:0] y;
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assign y = a*b + c*d + e*f;
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input [19:0] a, b, c;
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input [15:0] d, e, f;
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output [41:0] y;
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assign y = a*b + c*d + e*f;
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endmodule
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module test2(a, b, c, d, e, f, y);
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input [19:0] a, b, c;
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input [15:0] d, e, f;
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output [41:0] y;
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assign y = a*b + (c*d + e*f);
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input [19:0] a, b, c;
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input [15:0] d, e, f;
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output [41:0] y;
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assign y = a*b + (c*d + e*f);
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endmodule
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@ -3,21 +3,21 @@ read_verilog -lib -icells macc_xilinx_unwrap_map.v
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read_verilog -lib -icells macc_xilinx_xmap.v
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hierarchy -check ;;
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show -prefix macc_xilinx_test1_a -format pdf -notitle test1
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show -prefix macc_xilinx_test2_a -format pdf -notitle test2
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show -prefix macc_xilinx_test1a -format pdf -notitle test1
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show -prefix macc_xilinx_test2a -format pdf -notitle test2
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techmap -map macc_xilinx_swap_map.v;;
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show -prefix macc_xilinx_test1_b -format pdf -notitle test1
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show -prefix macc_xilinx_test2_b -format pdf -notitle test2
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show -prefix macc_xilinx_test1b -format pdf -notitle test1
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show -prefix macc_xilinx_test2b -format pdf -notitle test2
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techmap -map macc_xilinx_wrap_map.v
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connwrappers -unsigned $__mul_wrapper Y Y_WIDTH \
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-unsigned $__add_wrapper Y Y_WIDTH;;
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show -prefix macc_xilinx_test1_c -format pdf -notitle test1
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show -prefix macc_xilinx_test2_c -format pdf -notitle test2
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show -prefix macc_xilinx_test1c -format pdf -notitle test1
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show -prefix macc_xilinx_test2c -format pdf -notitle test2
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design -push
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read_verilog macc_xilinx_xmap.v
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@ -30,11 +30,14 @@ extract -constports -ignore_parameters \
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-map %__macc_xilinx_xmap \
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-swap $__add_wrapper A,B ;;
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show -prefix macc_xilinx_test1_d -format pdf -notitle test1
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show -prefix macc_xilinx_test2_d -format pdf -notitle test2
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show -prefix macc_xilinx_test1d -format pdf -notitle test1
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show -prefix macc_xilinx_test2d -format pdf -notitle test2
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techmap -map macc_xilinx_unwrap_map.v;;
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show -prefix macc_xilinx_test1_e -format pdf -notitle test1
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show -prefix macc_xilinx_test2_e -format pdf -notitle test2
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show -prefix macc_xilinx_test1e -format pdf -notitle test1
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show -prefix macc_xilinx_test2e -format pdf -notitle test2
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design -load
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show -prefix macc_xilinx_xmap -format pdf -notitle
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