riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

Progress in presentation

This commit is contained in:
Clifford Wolf 2014-02-20 23:44:28 +01:00
parent 4e43cb7317
commit 9351e4d3ca
4 changed files with 51 additions and 11 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

9
manual/PRESENTATION_ExAdv/macc_xilinx_test.v
View File

@ -1,6 +1,13 @@
module test(a, b, c, d, e, f, y);
module test1(a, b, c, d, e, f, y);
input [19:0] a, b, c;
input [15:0] d, e, f;
output [41:0] y;
assign y = a*b + c*d + e*f;
endmodule
module test2(a, b, c, d, e, f, y);
input [19:0] a, b, c;
input [15:0] d, e, f;
output [41:0] y;
assign y = a*b + (c*d + e*f);
endmodule

31
manual/PRESENTATION_ExAdv/macc_xilinx_test.ys
View File

@ -1,17 +1,40 @@
read_verilog macc_xilinx_test.v
read_verilog -lib -icells macc_xilinx_unwrap_map.v
hierarchy -check -top test;;
read_verilog -lib -icells macc_xilinx_xmap.v
hierarchy -check ;;
show -prefix macc_xilinx_test_a -format pdf -notitle
show -prefix macc_xilinx_test1_a -format pdf -notitle test1
show -prefix macc_xilinx_test2_a -format pdf -notitle test2
techmap -map macc_xilinx_swap_map.v;;
show -prefix macc_xilinx_test_b -format pdf -notitle
show -prefix macc_xilinx_test1_b -format pdf -notitle test1
show -prefix macc_xilinx_test2_b -format pdf -notitle test2
techmap -map macc_xilinx_wrap_map.v
connwrappers -unsigned $__mul_wrapper Y Y_WIDTH \
-unsigned $__add_wrapper Y Y_WIDTH;;
show -prefix macc_xilinx_test_c -format pdf -notitle
show -prefix macc_xilinx_test1_c -format pdf -notitle test1
show -prefix macc_xilinx_test2_c -format pdf -notitle test2
design -push
read_verilog macc_xilinx_xmap.v
techmap -map macc_xilinx_swap_map.v
techmap -map macc_xilinx_wrap_map.v;;
design -save __macc_xilinx_xmap
design -pop
extract -constports -ignore_parameters \
-map %__macc_xilinx_xmap \
-swap $__add_wrapper A,B ;;
show -prefix macc_xilinx_test1_d -format pdf -notitle test1
show -prefix macc_xilinx_test2_d -format pdf -notitle test2
techmap -map macc_xilinx_unwrap_map.v;;
show -prefix macc_xilinx_test1_e -format pdf -notitle test1
show -prefix macc_xilinx_test2_e -format pdf -notitle test2

12
manual/PRESENTATION_ExAdv/macc_xilinx_unwrap_map.v
View File

@ -7,9 +7,9 @@ parameter A_WIDTH = 1;
parameter B_WIDTH = 1;
parameter Y_WIDTH = 1;
input [A_WIDTH-1:0] A;
input [B_WIDTH-1:0] B;
output [Y_WIDTH-1:0] Y;
input [24:0] A;
input [17:0] B;
output [47:0] Y;
wire [A_WIDTH-1:0] A_ORIG = A;
wire [B_WIDTH-1:0] B_ORIG = B;
@ -38,9 +38,9 @@ parameter A_WIDTH = 1;
parameter B_WIDTH = 1;
parameter Y_WIDTH = 1;
input [A_WIDTH-1:0] A;
input [B_WIDTH-1:0] B;
output [Y_WIDTH-1:0] Y;
input [47:0] A;
input [47:0] B;
output [47:0] Y;
wire [A_WIDTH-1:0] A_ORIG = A;
wire [B_WIDTH-1:0] B_ORIG = B;

10
manual/PRESENTATION_ExAdv/macc_xilinx_xmap.v Normal file
View File

@ -0,0 +1,10 @@
module DSP48_MACC (a, b, c, y);
input [24:0] a;
input [17:0] b;
input [47:0] c;
output [47:0] y;
assign y = a*b + c;
endmodule