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Progress in presentation

This commit is contained in:
Clifford Wolf 2014-02-21 14:59:59 +01:00
parent 038eac7414
commit 79edcd4318
6 changed files with 113 additions and 32 deletions
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117
manual/PRESENTATION_ExAdv.tex
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@ -491,15 +491,13 @@ For example:
\end{lstlisting}
This circuit contains two cells in the RTL representation: one multiplier and
one adder.
\medskip
Coarse grain synthesis is mapping this circuit to a single multiply-add cell
of the target architecture, for example using an FPGA DSP core.
one adder. In some architectures this circuit can be implemented using
a single circuit element, for example an FPGA DSP core. Coarse grain synthesis
is this mapping of groups of circuit elements to larger components.
\bigskip
Fine-grain synthesis would be matching the circuit to smaller elements, such
as LUTs, gates, or half- and full-adders.
Fine-grain synthesis would be matching the circuit elements to smaller
components, such as LUTs, gates, or half- and full-adders.
\end{frame}
\subsubsection{The extract pass}
@ -558,12 +556,101 @@ $\downarrow$ & $\downarrow$ \\
\subsubsection{The wrap-extract-unwrap method}
\begin{frame}{\subsubsecname}
TBD
\scriptsize
Often a coarse-grain element has a constant bit-width, but can be used to
implement oprations with a smaller bit-width. For example, a 18x25-bit multiplier
can also be used to implement 16x20-bit multiplication.
\bigskip
A way of mapping such elements in coarse grain synthesis is the wrap-extract-unwrap method:
\begin{itemize}
\item {\bf wrap} \\
Identify candidate-cells in the circuit and wrap them in a cell with a constant
wider bit-width using {\tt techmap}. The wrappers use the same parameters as the original cell, so
the information about the original width of the ports is preserved. \\
Then use the {\tt connwrappers} command to connect up the bit-extended in- and
outputs of the wrapper cells.
\item {\bf extract} \\
Now all operations are encoded using the same bit-width as the coarse grain element. The {\tt
extract} command can be used to replace circuits with cells of the target architecture.
\item {\bf unwrap} \\
The remaining wrapper cell can be unwrapped using {\tt techmap}.
\end{itemize}
\bigskip
The following sides detail an example that shows how to map MACC operations of
arbitrary size to MACC cells with a 18x25-bit multiplier and a 48-bit adder (such as
the Xilinx DSP48 cells).
\end{frame}
\subsubsection{Example: DSP48\_MACC}
\begin{frame}[fragile]{\subsubsecname{} -- ?/?}
\begin{frame}[t, fragile]{\subsubsecname{} -- 1/13}
Preconditioning: {\tt macc\_xilinx\_swap\_map.v} \\
Make sure {\tt A} is the smaller port on all multipliers
\begin{columns}
\column{5cm}
\lstinputlisting[basicstyle=\ttfamily\fontsize{7pt}{8pt}\selectfont, language=verilog, lastline=15]{PRESENTATION_ExAdv/macc_xilinx_swap_map.v}
\column{5cm}
\lstinputlisting[basicstyle=\ttfamily\fontsize{7pt}{8pt}\selectfont, language=verilog, firstline=16]{PRESENTATION_ExAdv/macc_xilinx_swap_map.v}
\end{columns}
\end{frame}
\begin{frame}[t, fragile]{\subsubsecname{} -- 2/13}
Wrapping multipliers: {\tt macc\_xilinx\_wrap\_map.v}
\begin{columns}
\column[t]{5cm}
\lstinputlisting[basicstyle=\ttfamily\fontsize{7pt}{8pt}\selectfont, language=verilog, lastline=23]{PRESENTATION_ExAdv/macc_xilinx_wrap_map.v}
\column[t]{5cm}
\lstinputlisting[basicstyle=\ttfamily\fontsize{7pt}{8pt}\selectfont, language=verilog, firstline=24, lastline=46]{PRESENTATION_ExAdv/macc_xilinx_wrap_map.v}
\end{columns}
\end{frame}
\begin{frame}[t, fragile]{\subsubsecname{} -- 3/13}
Wrapping adders: {\tt macc\_xilinx\_wrap\_map.v}
\begin{columns}
\column[t]{5cm}
\lstinputlisting[basicstyle=\ttfamily\fontsize{7pt}{8pt}\selectfont, language=verilog, firstline=48, lastline=67]{PRESENTATION_ExAdv/macc_xilinx_wrap_map.v}
\column[t]{5cm}
\lstinputlisting[basicstyle=\ttfamily\fontsize{7pt}{8pt}\selectfont, language=verilog, firstline=68, lastline=89]{PRESENTATION_ExAdv/macc_xilinx_wrap_map.v}
\end{columns}
\end{frame}
\begin{frame}[t, fragile]{\subsubsecname{} -- 4/13}
Extract: {\tt macc\_xilinx\_xmap.v}
\lstinputlisting[xleftmargin=0.5cm, basicstyle=\ttfamily\fontsize{7pt}{8pt}\selectfont, language=verilog, firstline=1, lastline=17]{PRESENTATION_ExAdv/macc_xilinx_xmap.v}
.. simply use the same wrapping commands on this module as on the design to create a template for the {\tt extract} command.
\end{frame}
\begin{frame}[t, fragile]{\subsubsecname{} -- 5/13}
Unwrapping multipliers: {\tt macc\_xilinx\_unwrap\_map.v}
\begin{columns}
\column[t]{5cm}
\lstinputlisting[basicstyle=\ttfamily\fontsize{7pt}{8pt}\selectfont, language=verilog, firstline=1, lastline=17]{PRESENTATION_ExAdv/macc_xilinx_unwrap_map.v}
\column[t]{5cm}
\lstinputlisting[basicstyle=\ttfamily\fontsize{7pt}{8pt}\selectfont, language=verilog, firstline=18, lastline=30]{PRESENTATION_ExAdv/macc_xilinx_unwrap_map.v}
\end{columns}
\end{frame}
\begin{frame}[t, fragile]{\subsubsecname{} -- 6/13}
Unwrapping adders: {\tt macc\_xilinx\_unwrap\_map.v}
\begin{columns}
\column[t]{5cm}
\lstinputlisting[basicstyle=\ttfamily\fontsize{7pt}{8pt}\selectfont, language=verilog, firstline=32, lastline=48]{PRESENTATION_ExAdv/macc_xilinx_unwrap_map.v}
\column[t]{5cm}
\lstinputlisting[basicstyle=\ttfamily\fontsize{7pt}{8pt}\selectfont, language=verilog, firstline=49, lastline=61]{PRESENTATION_ExAdv/macc_xilinx_unwrap_map.v}
\end{columns}
\end{frame}
\begin{frame}[fragile]{\subsubsecname{} -- 7/13}
\hfil\begin{tabular}{cc}
{\tt test1} & {\tt test2} \\
\fbox{\hbox to 5cm {\lstinputlisting[linewidth=5cm, basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, firstline=1, lastline=6, language=verilog]{PRESENTATION_ExAdv/macc_xilinx_test.v}}} &
@ -583,7 +670,7 @@ $\downarrow$ & $\downarrow$ \\
\end{tabular}
\end{frame}
\begin{frame}[fragile]{\subsubsecname{} -- ?/?}
\begin{frame}[fragile]{\subsubsecname{} -- 8/13}
\hfil\begin{tabular}{cc}
{\tt test1} & {\tt test2} \\
\fbox{\includegraphics[width=5cm,trim=1.5cm 1.5cm 1.5cm 1.5cm]{PRESENTATION_ExAdv/macc_xilinx_test1a.pdf}} &
@ -602,7 +689,7 @@ $\downarrow$ & $\downarrow$ \\
\end{tabular}
\end{frame}
\begin{frame}[t, fragile]{\subsubsecname{} -- ?/?}
\begin{frame}[t, fragile]{\subsubsecname{} -- 9/13}
Wrapping in {\tt test1}:
\begin{columns}
\column[t]{5cm}
@ -622,7 +709,7 @@ connwrappers -unsigned $__mul_wrapper \
\hfil\includegraphics[width=\linewidth,trim=1.5cm 1.5cm 1.5cm 1.5cm]{PRESENTATION_ExAdv/macc_xilinx_test1c.pdf}
\end{frame}
\begin{frame}[t, fragile]{\subsubsecname{} -- ?/?}
\begin{frame}[t, fragile]{\subsubsecname{} -- 10/13}
Wrapping in {\tt test2}:
\begin{columns}
\column[t]{5cm}
@ -642,7 +729,7 @@ connwrappers -unsigned $__mul_wrapper \
\hfil\includegraphics[width=\linewidth,trim=1.5cm 1.5cm 1.5cm 1.5cm]{PRESENTATION_ExAdv/macc_xilinx_test2c.pdf}
\end{frame}
\begin{frame}[t, fragile]{\subsubsecname{} -- ?/?}
\begin{frame}[t, fragile]{\subsubsecname{} -- 11/13}
Extract in {\tt test1}:
\begin{columns}
\column[t]{4.5cm}
@ -670,7 +757,7 @@ extract -constports -ignore_parameters \
\hfil\includegraphics[width=11cm,trim=1.5cm 1.5cm 1.5cm 1.5cm]{PRESENTATION_ExAdv/macc_xilinx_test1d.pdf}
\end{frame}
\begin{frame}[t, fragile]{\subsubsecname{} -- ?/?}
\begin{frame}[t, fragile]{\subsubsecname{} -- 12/13}
Extract in {\tt test2}:
\begin{columns}
\column[t]{4.5cm}
@ -698,7 +785,7 @@ extract -constports -ignore_parameters \
\hfil\includegraphics[width=11cm,trim=1.5cm 1.5cm 1.5cm 1.5cm]{PRESENTATION_ExAdv/macc_xilinx_test2d.pdf}
\end{frame}
\begin{frame}[t, fragile]{\subsubsecname{} -- ?/?}
\begin{frame}[t, fragile]{\subsubsecname{} -- 13/13}
Unwrap in {\tt test2}:
\hfil\begin{tikzpicture}

4
manual/PRESENTATION_ExAdv/macc_xilinx_swap_map.v
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@ -1,4 +1,3 @@
(* techmap_celltype = "$mul" *)
module mul_swap_ports (A, B, Y);
@ -12,7 +11,7 @@ input [A_WIDTH-1:0] A;
input [B_WIDTH-1:0] B;
output [Y_WIDTH-1:0] Y;
wire _TECHMAP_FAIL_ = A_WIDTH >= B_WIDTH;
wire _TECHMAP_FAIL_ = A_WIDTH <= B_WIDTH;
\$mul #(
.A_SIGNED(B_SIGNED),
@ -27,4 +26,3 @@ wire _TECHMAP_FAIL_ = A_WIDTH >= B_WIDTH;
);
endmodule

2
manual/PRESENTATION_ExAdv/macc_xilinx_test.ys
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@ -38,6 +38,6 @@ techmap -map macc_xilinx_unwrap_map.v;;
show -prefix macc_xilinx_test1e -format pdf -notitle test1
show -prefix macc_xilinx_test2e -format pdf -notitle test2
design -load
design -load __macc_xilinx_xmap
show -prefix macc_xilinx_xmap -format pdf -notitle

6
manual/PRESENTATION_ExAdv/macc_xilinx_unwrap_map.v
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@ -1,4 +1,3 @@
module \$__mul_wrapper (A, B, Y);
parameter A_SIGNED = 0;
@ -7,8 +6,8 @@ parameter A_WIDTH = 1;
parameter B_WIDTH = 1;
parameter Y_WIDTH = 1;
input [24:0] A;
input [17:0] B;
input [17:0] A;
input [24:0] B;
output [47:0] Y;
wire [A_WIDTH-1:0] A_ORIG = A;
@ -60,4 +59,3 @@ assign Y = Y_ORIG;
);
endmodule

12
manual/PRESENTATION_ExAdv/macc_xilinx_wrap_map.v
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@ -1,4 +1,3 @@
(* techmap_celltype = "$mul" *)
module mul_wrap (A, B, Y);
@ -12,8 +11,8 @@ input [A_WIDTH-1:0] A;
input [B_WIDTH-1:0] B;
output [Y_WIDTH-1:0] Y;
wire [24:0] A_25 = A;
wire [17:0] B_18 = B;
wire [17:0] A_18 = A;
wire [24:0] B_25 = B;
wire [47:0] Y_48;
assign Y = Y_48;
@ -26,7 +25,7 @@ initial begin
_TECHMAP_FAIL_ <= 1;
if (A_WIDTH < 4 || B_WIDTH < 4)
_TECHMAP_FAIL_ <= 1;
if (A_WIDTH > 25 || B_WIDTH > 18)
if (A_WIDTH > 18 || B_WIDTH > 25)
_TECHMAP_FAIL_ <= 1;
if (A_WIDTH*B_WIDTH < 100)
_TECHMAP_FAIL_ <= 1;
@ -39,8 +38,8 @@ end
.B_WIDTH(B_WIDTH),
.Y_WIDTH(Y_WIDTH)
) _TECHMAP_REPLACE_ (
.A(A_25),
.B(B_18),
.A(A_18),
.B(B_25),
.Y(Y_48)
);
@ -88,4 +87,3 @@ end
);
endmodule

4
manual/PRESENTATION_ExAdv/macc_xilinx_xmap.v
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@ -1,7 +1,7 @@
module DSP48_MACC (a, b, c, y);
input [24:0] a;
input [17:0] b;
input [17:0] a;
input [24:0] b;
input [47:0] c;
output [47:0] y;