presentation progress

manual/PRESENTATION_ExAdv.tex

@@ -21,6 +21,7 @@ This section contains 4 subsections:
 
 \begin{frame}
 \subsectionpage
+\subsectionpagesuffix
 \end{frame}
 
 \subsubsection{TBD}
@@ -35,6 +36,7 @@ TBD
 
 \begin{frame}
 \subsectionpage
+\subsectionpagesuffix
 \end{frame}
 
 \subsubsection{TBD}
@@ -49,6 +51,7 @@ TBD
 
 \begin{frame}
 \subsectionpage
+\subsectionpagesuffix
 \end{frame}
 
 \subsubsection{TBD}
@@ -63,6 +66,7 @@ TBD
 
 \begin{frame}
 \subsectionpage
+\subsectionpagesuffix
 \end{frame}
 
 \subsubsection{TBD}

manual/PRESENTATION_ExOth.tex

@@ -20,6 +20,7 @@ This section contains 3 subsections:
 
 \begin{frame}
 \subsectionpage
+\subsectionpagesuffix
 \end{frame}
 
 \subsubsection{TBD}
@@ -34,6 +35,7 @@ TBD
 
 \begin{frame}
 \subsectionpage
+\subsectionpagesuffix
 \end{frame}
 
 \subsubsection{TBD}
@@ -48,6 +50,7 @@ TBD
 
 \begin{frame}
 \subsectionpage
+\subsectionpagesuffix
 \end{frame}
 
 \subsubsection{TBD}

manual/PRESENTATION_ExSyn.tex

@@ -348,7 +348,7 @@ Finally the {\tt fsm\_map} command can be used to convert the (optimized) {\tt
 \begin{frame}[t]{\subsecname}
 \vbox to 0cm{\includegraphics[width=12cm,trim=-18cm 0cm 0cm -34cm]{PRESENTATION_ExSyn/techmap_01.pdf}\vss}
 \vskip-0.8cm
-The {\tt techmap} command replaces cells with an implementations given as
+The {\tt techmap} command replaces cells with implementations given as
 verilog source. For example implementing a 32 bit adder using 16 bit adders:
 
 \vbox to 0cm{

manual/PRESENTATION_Intro.tex

@@ -1,5 +1,5 @@
 
-\section{Introduction}
+\section{Introduction to Yosys}
 
 \begin{frame}
 \sectionpage
@@ -578,7 +578,9 @@ endmodule
 \end{lstlisting}
 \end{frame}
 
-\subsection{Verification}
+%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
+
+\subsection{Verification of Yosys}
 
 \begin{frame}{\subsecname}
 Contiously checking the correctness of Yosys and making sure that new features
@@ -694,3 +696,43 @@ copyright notice and this permission notice appear in all copies.
 
 %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
 
+\subsection{Typical Applications for Yosys}
+
+\begin{frame}{\subsecname}
+\begin{itemize}
+\item Synthesis of final production designs
+\item Pre-production synthesis (trial runs before investing in other tools)
+\item Convertion of full-featured Verilog to simple Verilog
+\item Convertion of Verilog to other formats (BLIF, BTOR, etc)
+\item Demonstrating synthesis algorithms (e.g. for educational purposes)
+\item Framework for experimenting with new algorithms
+\item Framework for building custom flows\footnote[frame]{Not limited to synthesis
+but also formal verification, reverse engineering, ...}
+\end{itemize}
+\end{frame}
+
+%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
+
+\subsection{Documentation, Downloads, Contatcs}
+
+\begin{frame}{\subsecname}
+\begin{itemize}
+\item Website: \\
+\smallskip\hskip1cm\url{http://www.clifford.at/yosys/}
+
+\bigskip
+\item Manual, Command Reference, Appliction Notes: \\
+\smallskip\hskip1cm\url{http://www.clifford.at/yosys/documentation.html}
+
+\bigskip
+\item Instead of a mailing list we have a SubReddit: \\
+\smallskip\hskip1cm\url{http://www.reddit.com/r/yosys/}
+
+\bigskip
+\item Direct link to the source code: \\
+\smallskip\hskip1cm\url{https://github.com/cliffordwolf/yosys}
+\end{itemize}
+\end{frame}
+
+%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
+

manual/presentation.tex

@@ -60,6 +60,16 @@
 \begin{boxalertenv}#2{#1}\end{boxalertenv}%
 }}
 
+\newcommand{\subsectionpagesuffix}{
+\vfill\begin{centering}
+{\usebeamerfont{subsection name}\usebeamercolor[fg]{subsection name}of \sectionname~\insertsectionnumber}
+\vskip1em\par
+\setbeamercolor{graybox}{bg=gray}
+\begin{beamercolorbox}[sep=8pt,center,bg=gray]{graybox}
+\usebeamerfont{subsection title}\insertsection\par
+\end{beamercolorbox}
+\end{centering}}
+
 \title{Yosys Open SYnthesis Suite}
 \author{Clifford Wolf}
 \institute{http://www.clifford.at/}