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@ -79,7 +79,20 @@ external viewer can be used.
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\section{Introduction to the {\tt show} command}
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\FIXME
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The {\tt show} command generates a circuit diagram for the design in its
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current state. Various options can be used to change the appearance of the
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circuit diagram, set the name and format for the output file, and so forth.
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When called without any special options, it saves the circuit diagram in
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a temporary file and launches {\tt yosys-svgviewer} to display the diagram.
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Subsequent calls to {\tt show} re-use the {\tt yosys-svgviewer} instance
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(if still running).
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Fig.~\ref{example_src} shows a simple synthesis script and Verilog file that
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demonstrates the usage of {\tt show} in a simple setting. Note that {\tt show}
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is called with the {\tt -pause} option, that halts execution of the Yosys
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script until the user presses the Enter key. The {\tt show -pause} command
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also allows the user to enter an interactive shell to further investigate the
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circuit before continuing synthesis.
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\begin{figure}[b]
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\begin{lstlisting}
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@ -99,18 +112,110 @@ module example(input clk, a, b, c,
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y <= c ? a + b : 2'd0;
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endmodule
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\end{lstlisting}
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\caption{Synthesis script with added show commands and example code}
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\caption{Yosys script with {\tt show} commands and example design}
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\label{example_src}
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\end{figure}
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\begin{figure}[b]
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So this script, when executed, will show the design after each of the three
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synthesis commands. The generated circuit diagrams are shown in Fig.~\ref{example_out}.
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The first diagram (from top to bottom) shows the design directly after being
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read by the Verilog front-end. Input and output ports are visualized using
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octagonal shapes. Cells are visualized as rectangles with inputs on the left
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and outputs on the right side. The cell labels are two lines long: The first line
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contains the cell name (or a {\tt \_<number\_} placeholder for cells without
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a name from the original Verilog, such as cells created from Verilog
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expressions) and the second line contains the cell type. Internal cell types
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are prefixed with a dollar sign. The Yosys manual contains a chapter on the
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internal cell library used in Yosys.
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Constants are shown as ellipses with the constant value as label. The syntax
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{\tt <bit\_width>'<bits>} is used for for constants that are not 32-bit wide
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and/or contain bits that are not 0 or 1 (but {\tt x} or {\tt z}). Ordinary
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32-bit constants are written using decimal numbers.
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Single-bit signals are shown as thin arrows pointing from the driver to the
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load. Signals that are multiple bits wide are shown as think arrows.
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Finally {\it processes\/} are shown in boxes with round corners. Processes
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are Yosys' internal representation of the decision-trees and synchronization
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events modelled in a Verilog {\tt always}-block. The label reads {\tt PROC} in the
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first line and contains the source code location of the original {\tt
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always}-block in the 2nd line. Not how the multiplexer from the {\tt ?:}-expression
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is represented as a {\tt \$mux} cell but the multiplexer from the {\tt if}-statement
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is yet still hidden within the process.
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\medskip
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The {\tt proc} command transforms the process from the first diagram into a
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multiplexer and a d-type flip-flip, which brings us to the 2nd diagram.
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Note that the auto-generated numbers for the cells have changed since the first
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diagram, because they are just placeholders . We will cover how to avoid this
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later in this document.
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\begin{figure}[b!]
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\includegraphics[width=\linewidth]{APPNOTE_011_Design_Investigation/example_00.pdf}
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\includegraphics[width=\linewidth]{APPNOTE_011_Design_Investigation/example_01.pdf}
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\includegraphics[width=\linewidth]{APPNOTE_011_Design_Investigation/example_02.pdf}
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\caption{\tt Output of the three show commands from Fig.~\ref{example_src}}
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\caption{Output of the three {\tt show} commands from Fig.~\ref{example_src}}
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\label{example_out}
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\end{figure}
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Also note that the design now contains two instances of a {\tt BUF}-node. The
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Rhombus shape to the right is a dangling wire. (Wire nodes are only shown if
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they are dangling or have names assigned from the Verilog input.) This are
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artefacts left behind by the {\tt proc}-command. It is quite usual to see such
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artefacts after calling commands that perform changes in the design, as most
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commands only care about doing the transformation in a foolproof way, not about
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cleaning up after them. The next call to {\tt clean} (or {\tt opt}, which
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includes {\tt clean} as one of its operations) will clean up this artefacts.
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This operation is so common in Yosys scripts that it can simply be abbreviated
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by using the {\tt ;;} token, which doubles as separator for commands. Unless
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one wants to specifically analyze this artefacts left behind some operations,
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it is therefore recommended to call {\tt clean} before calling {\tt show}.
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\medskip
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In this script we directly call {\tt opt} as next step, which finally leads us to
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the 3rd diagram in Fig.~\ref{example_out}. Here we see that the {\tt opt} command
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not only has removed the artifacts left behind by {\tt proc}, but also determined
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correctly that it can remove the first {\tt \$mux} cell without changing the behavior
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of the circuit.
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\begin{figure}[b!]
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\includegraphics[width=\linewidth,trim=0 2cm 0 0]{APPNOTE_011_Design_Investigation/splice.pdf}
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\caption{Output of {\tt yosys -p 'proc; opt; show' splice.v}}
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\label{example_src}
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\end{figure}
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\begin{figure}[b!]
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\begin{lstlisting}
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module splice_demo(a, b, c, d, e, f, x, y);
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input [1:0] a, b, c, d, e, f;
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output [1:0] x = {a[0], a[1]};
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output [11:0] y;
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assign {y[11:4], y[1:0], y[3:2]} =
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{a, b, -{c, d}, ~{e, f}};
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endmodule
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\end{lstlisting}
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\caption{\tt splice.v}
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\label{example_src}
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\end{figure}
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\FIXME{} --- Splicing, Cell libraries
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\section{Navigating the design}
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\FIXME{} --- cd and ls, multi-page diagrams, select, cones and boolean operations
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\section{Advanced investigation techniques}
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\FIXME{} --- dump, eval, sat
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\begin{thebibliography}{9}
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@ -1,3 +1,4 @@
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example_00.dot
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example_01.dot
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example_02.dot
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splice.dot
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@ -1,6 +1,8 @@
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#!/bin/bash
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../../yosys example.ys
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sed -i '/^label=/ d;' example_*.dot
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../../yosys -p 'proc; opt; show -format dot -prefix splice' splice.v
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sed -i '/^label=/ d;' example_*.dot splice.dot
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dot -Tpdf -o example_00.pdf example_00.dot
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dot -Tpdf -o example_01.pdf example_01.dot
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dot -Tpdf -o example_02.pdf example_02.dot
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dot -Tpdf -o splice.pdf splice.dot
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@ -0,0 +1,9 @@
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module splice_demo(a, b, c, d, e, f, x, y);
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input [1:0] a, b, c, d, e, f;
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output [1:0] x = {a[0], a[1]};
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output [11:0] y;
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assign {y[11:4], y[1:0], y[3:2]} = {a, b, -{c, d}, ~{e, f}};
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endmodule
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