mirror of https://github.com/YosysHQ/yosys.git
presentation progress
This commit is contained in:
Clifford Wolf
parent
2cb47355d4
commit
961b791272
|
|
@ -29,10 +29,24 @@
|
|||
\only<2>{Physical Layout}%
|
||||
\only<3>{Netlists}%
|
||||
\only<4>{Hardware Description Languages (HDLs)}}
|
||||
\only<1>{TBD}
|
||||
\only<2>{TBD}
|
||||
\only<3>{TBD}
|
||||
\only<4>{TBD}
|
||||
\only<1>{
|
||||
Graphical representation of the circtuit topology. Circuit elements
|
||||
are represented by symbols and electrical connections by lines. The gometric
|
||||
layout is for readability only.
|
||||
}%
|
||||
\only<2>{
|
||||
The actual physical geometry of the device (PCB or ASIC manufracturing masks).
|
||||
This is the final product of the design process.
|
||||
}%
|
||||
\only<3>{
|
||||
A list of circuit elements and a list of connections. This is the raw circuit
|
||||
topology.
|
||||
}%
|
||||
\only<4>{
|
||||
Computer languages (like programming languages) that can be used to describe
|
||||
circuits. HDLs are much more powerful in describing huge circuits than
|
||||
schematic diagrams.
|
||||
}%
|
||||
\end{block}
|
||||
\end{frame}
|
||||
|
||||
|
|
@ -93,5 +107,214 @@
|
|||
\subsection{Digital Circuit Synthesis}
|
||||
|
||||
\begin{frame}{\subsecname}
|
||||
Synthesis Tools (such as Yosys) can transform HDL code to circuits:
|
||||
|
||||
\bigskip
|
||||
\begin{center}
|
||||
\begin{tikzpicture}[scale=0.8, every node/.style={transform shape}]
|
||||
\tikzstyle{lvl} = [draw, fill=MyBlue, rectangle, minimum height=2em, minimum width=15em]
|
||||
\node[lvl] (sys) {System Level};
|
||||
\node[lvl] (hl) [below of=sys] {High Level};
|
||||
\node[lvl] (beh) [below of=hl] {Behavioral Level};
|
||||
\node[lvl] (rtl) [below of=beh] {Register-Transfer Level (RTL)};
|
||||
\node[lvl] (lg) [below of=rtl] {Logical Gate Level};
|
||||
\node[lvl] (pg) [below of=lg] {Physical Gate Level};
|
||||
\node[lvl] (sw) [below of=pg] {Switch Level};
|
||||
|
||||
\draw[dotted] (sys.east) -- ++(1,0) coordinate (sysx);
|
||||
\draw[dotted] (hl.east) -- ++(1,0) coordinate (hlx);
|
||||
\draw[dotted] (beh.east) -- ++(1,0) coordinate (behx);
|
||||
\draw[dotted] (rtl.east) -- ++(1,0) coordinate (rtlx);
|
||||
\draw[dotted] (lg.east) -- ++(1,0) coordinate (lgx);
|
||||
\draw[dotted] (pg.east) -- ++(1,0) coordinate (pgx);
|
||||
\draw[dotted] (sw.east) -- ++(1,0) coordinate (swx);
|
||||
|
||||
\draw[gray,|->] (sysx) -- node[right] {System Design} (hlx);
|
||||
\draw[|->|] (hlx) -- node[right] {High Level Synthesis (HLS)} (behx);
|
||||
\draw[->|] (behx) -- node[right] {Behavioral Synthesis} (rtlx);
|
||||
\draw[->|] (rtlx) -- node[right] {RTL Synthesis} (lgx);
|
||||
\draw[->|] (lgx) -- node[right] {Logic Synthesis} (pgx);
|
||||
\draw[gray,->|] (pgx) -- node[right] {Cell Library} (swx);
|
||||
|
||||
\draw[dotted] (behx) -- ++(4,0) coordinate (a);
|
||||
\draw[dotted] (pgx) -- ++(4,0) coordinate (b);
|
||||
\draw[|->|] (a) -- node[right] {Yosys} (b);
|
||||
\end{tikzpicture}
|
||||
\end{center}
|
||||
\end{frame}
|
||||
|
||||
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
|
||||
|
||||
\subsection{What Yosys can and can't do}
|
||||
|
||||
\begin{frame}{\subsecname}
|
||||
|
||||
Things Yosys can do:
|
||||
\begin{itemize}
|
||||
\item Read and process (most of) modern Verilog-2005 code.
|
||||
\item Perform all kinds of operations on netlist (RTL, Logic, Gate).
|
||||
\item Perform logic optimiziations and gate mapping with ABC\footnote{\url{http://www.eecs.berkeley.edu/~alanmi/abc/}}.
|
||||
\end{itemize}
|
||||
|
||||
\bigskip
|
||||
Things Yosys can't do:
|
||||
\begin{itemize}
|
||||
\item Process high-level languages such as C/C++/SystemC.
|
||||
\item Create physical layouts (place\&route).
|
||||
\end{itemize}
|
||||
|
||||
\bigskip
|
||||
A typical flow combines Yosys with with a low-level implementation tool, such
|
||||
as Qflow\footnote{\url{http://opencircuitdesign.com/qflow/}} for ASIC designs.
|
||||
|
||||
\end{frame}
|
||||
|
||||
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
|
||||
|
||||
\subsection{Yosys Data- and Control-Flow}
|
||||
|
||||
\begin{frame}{\subsecname}
|
||||
A (usually short) synthesis script controlls Yosys.
|
||||
|
||||
This scripts contain three types of commands:
|
||||
\begin{itemize}
|
||||
\item {\bf Frontends}, that read input files (usually Verilog).
|
||||
\item {\bf Passes}, that perform transformation on the design in memory.
|
||||
\item {\bf Backends}, that write the design in memory to a file (various formats are available, e.g. Verilog, BLIF, EDIF, SPICE, BTOR, etc.).
|
||||
\end{itemize}
|
||||
|
||||
\bigskip
|
||||
\begin{center}
|
||||
\begin{tikzpicture}[scale=0.6, every node/.style={transform shape}]
|
||||
\path (-1.5,3) coordinate (cursor);
|
||||
\draw[-latex] ($ (cursor) + (0,-1.5) $) -- ++(1,0);
|
||||
\draw[fill=orange!10] ($ (cursor) + (1,-3) $) rectangle node[rotate=90] {Frontend} ++(1,3) coordinate (cursor);
|
||||
\draw[-latex] ($ (cursor) + (0,-1.5) $) -- ++(1,0);
|
||||
\draw[fill=green!10] ($ (cursor) + (1,-3) $) rectangle node[rotate=90] {Pass} ++(1,3) coordinate (cursor);
|
||||
\draw[-latex] ($ (cursor) + (0,-1.5) $) -- ++(1,0);
|
||||
\draw[fill=green!10] ($ (cursor) + (1,-3) $) rectangle node[rotate=90] {Pass} ++(1,3) coordinate (cursor);
|
||||
\draw[-latex] ($ (cursor) + (0,-1.5) $) -- ++(1,0);
|
||||
\draw[fill=green!10] ($ (cursor) + (1,-3) $) rectangle node[rotate=90] {Pass} ++(1,3) coordinate (cursor);
|
||||
\draw[-latex] ($ (cursor) + (0,-1.5) $) -- ++(1,0);
|
||||
\draw[fill=orange!10] ($ (cursor) + (1,-3) $) rectangle node[rotate=90] {Backend} ++(1,3) coordinate (cursor);
|
||||
\draw[-latex] ($ (cursor) + (0,-1.5) $) -- ++(1,0);
|
||||
|
||||
\path (-3,-0.5) coordinate (cursor);
|
||||
\draw (cursor) -- node[below] {HDL} ++(3,0) coordinate (cursor);
|
||||
\draw[|-|] (cursor) -- node[below] {Internal Format (RTLIL)} ++(8,0) coordinate (cursor);
|
||||
\draw (cursor) -- node[below] {Netlist} ++(3,0);
|
||||
|
||||
\path (-3,3.5) coordinate (cursor);
|
||||
\draw[-] (cursor) -- node[above] {High-Level} ++(3,0) coordinate (cursor);
|
||||
\draw[-] (cursor) -- ++(8,0) coordinate (cursor);
|
||||
\draw[->] (cursor) -- node[above] {Low-Level} ++(3,0);
|
||||
\end{tikzpicture}
|
||||
\end{center}
|
||||
\end{frame}
|
||||
|
||||
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
|
||||
|
||||
\subsection{Example Synthesis Script}
|
||||
|
||||
\begin{frame}[t]{\subsecname}
|
||||
|
||||
\setbeamercolor{alerted text}{fg=white,bg=red}
|
||||
|
||||
\begin{minipage}[t]{6cm}
|
||||
\tt\scriptsize
|
||||
\# read design\\
|
||||
\boxalert<1>{read\_verilog mydesign.v}\\
|
||||
\boxalert<2>{hierarchy -check -top mytop}
|
||||
|
||||
\medskip
|
||||
\# the high-level stuff\\
|
||||
\boxalert<3>{proc}; \boxalert<4>{opt}; \boxalert<5>{memory}; \boxalert<6>{opt}; \boxalert<7>{fsm}; \boxalert<8>{opt}
|
||||
|
||||
\medskip
|
||||
\# mapping to internal cell library\\
|
||||
\boxalert<9>{techmap}; \boxalert<10>{opt}
|
||||
|
||||
\bigskip
|
||||
\it continued\dots
|
||||
\end{minipage}
|
||||
\begin{minipage}[t]{5cm}
|
||||
\tt\scriptsize
|
||||
\# mapping flip-flops to mycells.lib\\
|
||||
\boxalert<11>{dfflibmap -liberty mycells.lib}
|
||||
|
||||
\medskip
|
||||
\# mapping logic to mycells.lib\\
|
||||
\boxalert<12>{abc -liberty mycells.lib}
|
||||
|
||||
\medskip
|
||||
\# cleanup\\
|
||||
\boxalert<13>{clean}
|
||||
|
||||
\medskip
|
||||
\# write synthesized design\\
|
||||
\boxalert<14>{write\_verilog synth.v}
|
||||
\end{minipage}
|
||||
|
||||
\vskip1cm
|
||||
|
||||
\begin{block}{Command: \tt
|
||||
\only<1>{read\_verilog mydesign.v}%
|
||||
\only<2>{hierarchy -check -top mytop}%
|
||||
\only<3>{proc}%
|
||||
\only<4>{opt}%
|
||||
\only<5>{memory}%
|
||||
\only<6>{opt}%
|
||||
\only<7>{fsm}%
|
||||
\only<8>{opt}%
|
||||
\only<9>{techmap}%
|
||||
\only<10>{opt}%
|
||||
\only<11>{dfflibmap -liberty mycells.lib}%
|
||||
\only<12>{abc -liberty mycells.lib}%
|
||||
\only<13>{clean}%
|
||||
\only<14>{write\_verilog synth.v}}
|
||||
\only<1>{
|
||||
TBD
|
||||
}%
|
||||
\only<2>{
|
||||
TBD
|
||||
}%
|
||||
\only<3>{
|
||||
TBD
|
||||
}%
|
||||
\only<4>{
|
||||
TBD
|
||||
}%
|
||||
\only<5>{
|
||||
TBD
|
||||
}%
|
||||
\only<6>{
|
||||
TBD
|
||||
}%
|
||||
\only<7>{
|
||||
TBD
|
||||
}%
|
||||
\only<8>{
|
||||
TBD
|
||||
}%
|
||||
\only<9>{
|
||||
TBD
|
||||
}%
|
||||
\only<10>{
|
||||
TBD
|
||||
}%
|
||||
\only<11>{
|
||||
TBD
|
||||
}%
|
||||
\only<12>{
|
||||
TBD
|
||||
}%
|
||||
\only<13>{
|
||||
TBD
|
||||
}%
|
||||
\only<14>{
|
||||
TBD
|
||||
}%
|
||||
\end{block}
|
||||
|
||||
\end{frame}
|
||||
|
||||
|
|
|
|||
|
|
@ -50,6 +50,14 @@
|
|||
morestring=[b]",
|
||||
}
|
||||
|
||||
\newenvironment{boxalertenv}{\begin{altenv}%
|
||||
{\usebeamertemplate{alerted text begin}\usebeamercolor[fg]{alerted text}\usebeamerfont{alerted text}\setlength{\fboxsep}{1pt}\colorbox{bg}}
|
||||
{\usebeamertemplate{alerted text end}}{\color{.}}{}}{\end{altenv}}
|
||||
|
||||
\newcommand<>{\boxalert}[1]{{%
|
||||
\begin{boxalertenv}#2{#1}\end{boxalertenv}%
|
||||
}}
|
||||
|
||||
\title{Yosys Open SYnthesis Suite}
|
||||
\author{Clifford Wolf}
|
||||
\institute{http://www.clifford.at/}
|
||||
|
|
@ -59,6 +67,8 @@
|
|||
\beamertemplatenavigationsymbolsempty
|
||||
|
||||
\definecolor{YosysGreen}{RGB}{85,136,102}
|
||||
\definecolor{MyBlue}{RGB}{85,130,180}
|
||||
|
||||
\setbeamercolor{title}{fg=black,bg=YosysGreen!70}
|
||||
\setbeamercolor{titlelike}{fg=black,bg=YosysGreen!70}
|
||||
\setbeamercolor{frametitle}{fg=black,bg=YosysGreen!70}
|
||||
|
|
|
|||
Loading…
Reference in New Issue