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presentation progress

This commit is contained in:
Clifford Wolf 2014-02-02 22:26:26 +01:00
parent 9d0b69edaa
commit 982c9da011
19 changed files with 199 additions and 45 deletions
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100
manual/PRESENTATION_ExSyn.tex
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@ -103,36 +103,35 @@ a call to {\tt proc} is the first command in the actual synthesis procedure
after design elaboration.
\end{frame}
\begin{frame}[fragile]{\subsecname{} -- Example 1/TBD}
\begin{columns}
\column[t]{5cm}
\lstinputlisting[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=verilog]{PRESENTATION_ExSyn/proc_00.v}
\column[t]{5cm}
\lstinputlisting[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, frame=single]{PRESENTATION_ExSyn/proc_00.ys}
\end{columns}
% \includegraphics[width=\linewidth,trim=0 0cm 0 0cm]{PRESENTATION_ExSyn/proc_00.pdf}
\hfil\includegraphics[width=8cm,trim=0 0cm 0 0cm]{PRESENTATION_ExSyn/proc_00.pdf}
\end{frame}
\begin{frame}[t, fragile]{\subsecname{} -- Example 2/TBD}
\vbox to 0cm{\includegraphics[width=\linewidth,trim=0cm 0cm 0cm -2.5cm]{PRESENTATION_ExSyn/proc_01.pdf}}
\vskip-1cm
\begin{frame}[fragile]{\subsecname{} -- Example 1/3}
\begin{columns}
\column[t]{5cm}
\lstinputlisting[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=verilog]{PRESENTATION_ExSyn/proc_01.v}
\column[t]{5cm}
\lstinputlisting[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, frame=single]{PRESENTATION_ExSyn/proc_01.ys}
\end{columns}
\hfil\includegraphics[width=8cm,trim=0 0cm 0 0cm]{PRESENTATION_ExSyn/proc_01.pdf}
\end{frame}
\begin{frame}[t, fragile]{\subsecname{} -- Example 3/TBD}
\vbox to 0cm{\includegraphics[width=\linewidth,trim=0cm 0cm 0cm -1.5cm]{PRESENTATION_ExSyn/proc_02.pdf}}
\begin{frame}[t, fragile]{\subsecname{} -- Example 2/3}
\vbox to 0cm{\includegraphics[width=\linewidth,trim=0cm 0cm 0cm -2.5cm]{PRESENTATION_ExSyn/proc_02.pdf}\vss}
\vskip-1cm
\begin{columns}
\column[t]{5cm}
\lstinputlisting[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, frame=single]{PRESENTATION_ExSyn/proc_02.ys}
\column[t]{5cm}
\lstinputlisting[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=verilog]{PRESENTATION_ExSyn/proc_02.v}
\column[t]{5cm}
\lstinputlisting[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, frame=single]{PRESENTATION_ExSyn/proc_02.ys}
\end{columns}
\end{frame}
\begin{frame}[t, fragile]{\subsecname{} -- Example 3/3}
\vbox to 0cm{\includegraphics[width=\linewidth,trim=0cm 0cm 0cm -1.5cm]{PRESENTATION_ExSyn/proc_03.pdf}\vss}
\vskip-1cm
\begin{columns}
\column[t]{5cm}
\lstinputlisting[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, frame=single]{PRESENTATION_ExSyn/proc_03.ys}
\column[t]{5cm}
\lstinputlisting[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=verilog]{PRESENTATION_ExSyn/proc_03.v}
\end{columns}
\end{frame}
@ -166,6 +165,50 @@ proc; opt; memory; opt_const;; fsm;;
\end{lstlisting}
\end{frame}
\begin{frame}[t, fragile]{\subsecname{} -- Example 1/4}
\vbox to 0cm{\includegraphics[width=\linewidth,trim=0cm 0cm 0cm -0.5cm]{PRESENTATION_ExSyn/opt_01.pdf}\vss}
\vskip-1cm
\begin{columns}
\column[t]{5cm}
\lstinputlisting[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, frame=single]{PRESENTATION_ExSyn/opt_01.ys}
\column[t]{5cm}
\lstinputlisting[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=verilog]{PRESENTATION_ExSyn/opt_01.v}
\end{columns}
\end{frame}
\begin{frame}[t, fragile]{\subsecname{} -- Example 2/4}
\vbox to 0cm{\includegraphics[width=\linewidth,trim=0cm 0cm 0cm 0cm]{PRESENTATION_ExSyn/opt_02.pdf}\vss}
\vskip-1cm
\begin{columns}
\column[t]{5cm}
\lstinputlisting[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, frame=single]{PRESENTATION_ExSyn/opt_02.ys}
\column[t]{5cm}
\lstinputlisting[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=verilog]{PRESENTATION_ExSyn/opt_02.v}
\end{columns}
\end{frame}
\begin{frame}[t, fragile]{\subsecname{} -- Example 3/4}
\vbox to 0cm{\includegraphics[width=\linewidth,trim=0cm 0cm 0cm -2cm]{PRESENTATION_ExSyn/opt_03.pdf}\vss}
\vskip-1cm
\begin{columns}
\column[t]{5cm}
\lstinputlisting[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, frame=single]{PRESENTATION_ExSyn/opt_03.ys}
\column[t]{5cm}
\lstinputlisting[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=verilog]{PRESENTATION_ExSyn/opt_03.v}
\end{columns}
\end{frame}
\begin{frame}[t, fragile]{\subsecname{} -- Example 4/4}
\vbox to 0cm{\hskip6cm\includegraphics[width=6cm,trim=0cm 0cm 0cm -3cm]{PRESENTATION_ExSyn/opt_04.pdf}\vss}
\vskip-1cm
\begin{columns}
\column[t]{5cm}
\lstinputlisting[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=verilog]{PRESENTATION_ExSyn/opt_04.v}
\column[t]{5cm}
\lstinputlisting[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, frame=single]{PRESENTATION_ExSyn/opt_04.ys}
\end{columns}
\end{frame}
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
\subsection{When to use ``opt'' or ``clean''}
@ -222,7 +265,28 @@ For example:
\begin{lstlisting}[xleftmargin=0.5cm, basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont]
memory -nomap; techmap -map my_memory_map.v; memory_map
\end{lstlisting}
\end{frame}
\begin{frame}[t, fragile]{\subsecname{} -- Example 1/TBD}
\vbox to 0cm{\includegraphics[width=\linewidth,trim=0cm 0cm 0cm -10cm]{PRESENTATION_ExSyn/memory_01.pdf}\vss}
\vskip-1cm
\begin{columns}
\column[t]{5cm}
\lstinputlisting[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, frame=single]{PRESENTATION_ExSyn/memory_01.ys}
\column[t]{5cm}
\lstinputlisting[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=verilog]{PRESENTATION_ExSyn/memory_01.v}
\end{columns}
\end{frame}
\begin{frame}[t, fragile]{\subsecname{} -- Example 2/TBD}
\vbox to 0cm{\hfill\includegraphics[width=7.5cm,trim=0cm 0cm 0cm -6cm]{PRESENTATION_ExSyn/memory_02.pdf}\vss}
\vskip-1cm
\begin{columns}
\column[t]{5cm}
\lstinputlisting[basicstyle=\ttfamily\fontsize{6pt}{8pt}\selectfont, language=verilog]{PRESENTATION_ExSyn/memory_02.v}
\column[t]{5cm}
\lstinputlisting[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, frame=single]{PRESENTATION_ExSyn/memory_02.ys}
\end{columns}
\end{frame}
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%

20
manual/PRESENTATION_ExSyn/Makefile
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@ -1,12 +1,18 @@
all: proc_00.pdf proc_01.pdf proc_02.pdf
TARGETS += proc_01 proc_02 proc_03
TARGETS += opt_01 opt_02 opt_03 opt_04
TARGETS += memory_01 memory_02
proc_00.pdf: proc_00.v proc_00.ys
../../yosys -p 'script proc_00.ys; show -notitle -prefix proc_00 -format pdf'
all: $(addsuffix .pdf,$(TARGETS))
proc_01.pdf: proc_01.v proc_01.ys
../../yosys -p 'script proc_01.ys; show -notitle -prefix proc_01 -format pdf'
define make_pdf_template
$(1).pdf: $(1).v $(1).ys
../../yosys -p 'script $(1).ys; show -notitle -prefix $(1) -format pdf'
endef
proc_02.pdf: proc_02.v proc_02.ys
../../yosys -p 'script proc_02.ys; show -notitle -prefix proc_02 -format pdf'
$(foreach trg,$(TARGETS),$(eval $(call make_pdf_template,$(trg))))
clean:
rm -f $(addsuffix .pdf,$(TARGETS))
rm -f $(addsuffix .dot,$(TARGETS))

9
manual/PRESENTATION_ExSyn/memory_01.v Normal file
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@ -0,0 +1,9 @@
module test(input CLK, ADDR,
input [7:0] DIN,
output reg [7:0] DOUT);
reg [7:0] mem [0:1];
always @(posedge CLK) begin
mem[ADDR] <= DIN;
DOUT <= mem[ADDR];
end
endmodule

3
manual/PRESENTATION_ExSyn/memory_01.ys Normal file
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@ -0,0 +1,3 @@
read_verilog memory_01.v
hierarchy -check -top test
proc;; memory; opt

27
manual/PRESENTATION_ExSyn/memory_02.v Normal file
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@ -0,0 +1,27 @@
module test(
input WR1_CLK, WR2_CLK,
input WR1_WEN, WR2_WEN,
input [7:0] WR1_ADDR, WR2_ADDR,
input [7:0] WR1_DATA, WR2_DATA,
input RD1_CLK, RD2_CLK,
input [7:0] RD1_ADDR, RD2_ADDR,
output reg [7:0] RD1_DATA, RD2_DATA
);
reg [7:0] memory [0:255];
always @(posedge WR1_CLK)
if (WR1_WEN)
memory[WR1_ADDR] <= WR1_DATA;
always @(posedge WR2_CLK)
if (WR2_WEN)
memory[WR2_ADDR] <= WR2_DATA;
always @(posedge RD1_CLK)
RD1_DATA <= memory[RD1_ADDR];
always @(posedge RD2_CLK)
RD2_DATA <= memory[RD2_ADDR];
endmodule

4
manual/PRESENTATION_ExSyn/memory_02.ys Normal file
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@ -0,0 +1,4 @@
read_verilog memory_02.v
hierarchy -check -top test
proc;; memory -nomap
opt -mux_undef -mux_bool

3
manual/PRESENTATION_ExSyn/opt_01.v Normal file
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@ -0,0 +1,3 @@
module test(input A, B, output Y);
assign Y = A ? A ? B : 1'b1 : B;
endmodule

3
manual/PRESENTATION_ExSyn/opt_01.ys Normal file
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@ -0,0 +1,3 @@
read_verilog opt_01.v
hierarchy -check -top test
opt

3
manual/PRESENTATION_ExSyn/opt_02.v Normal file
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@ -0,0 +1,3 @@
module test(input A, output Y, Z);
assign Y = A == A, Z = A != A;
endmodule

3
manual/PRESENTATION_ExSyn/opt_02.ys Normal file
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@ -0,0 +1,3 @@
read_verilog opt_02.v
hierarchy -check -top test
opt

4
manual/PRESENTATION_ExSyn/opt_03.v Normal file
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@ -0,0 +1,4 @@
module test(input [3:0] A, B,
output [3:0] Y, Z);
assign Y = A + B, Z = B + A;
endmodule

3
manual/PRESENTATION_ExSyn/opt_03.ys Normal file
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@ -0,0 +1,3 @@
read_verilog opt_03.v
hierarchy -check -top test
opt

19
manual/PRESENTATION_ExSyn/opt_04.v Normal file
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@ -0,0 +1,19 @@
module test(input CLK, ARST,
output [7:0] Q1, Q2, Q3);
wire NO_CLK = 0;
always @(posedge CLK, posedge ARST)
if (ARST)
Q1 <= 42;
always @(posedge NO_CLK, posedge ARST)
if (ARST)
Q2 <= 42;
else
Q2 <= 23;
always @(posedge CLK)
Q3 <= 42;
endmodule

3
manual/PRESENTATION_ExSyn/opt_04.ys Normal file
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@ -0,0 +1,3 @@
read_verilog opt_04.v
hierarchy -check -top test
proc; opt

7
manual/PRESENTATION_ExSyn/proc_00.v
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@ -1,7 +0,0 @@
module test(input D, C, R, output reg Q);
always @(posedge C, posedge R)
if (R)
Q <= 0;
else
Q <= D;
endmodule

5
manual/PRESENTATION_ExSyn/proc_01.v
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@ -1,8 +1,7 @@
module test(input D, C, R, RV,
output reg Q);
module test(input D, C, R, output reg Q);
always @(posedge C, posedge R)
if (R)
Q <= RV;
Q <= 0;
else
Q <= D;
endmodule

16
manual/PRESENTATION_ExSyn/proc_02.v
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@ -1,10 +1,8 @@
module test(input A, B, C, D, E,
output reg Y);
always @* begin
Y <= A;
if (B)
Y <= C;
if (D)
Y <= E;
end
module test(input D, C, R, RV,
output reg Q);
always @(posedge C, posedge R)
if (R)
Q <= RV;
else
Q <= D;
endmodule

10
manual/PRESENTATION_ExSyn/proc_03.v Normal file
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@ -0,0 +1,10 @@
module test(input A, B, C, D, E,
output reg Y);
always @* begin
Y <= A;
if (B)
Y <= C;
if (D)
Y <= E;
end
endmodule

2
manual/PRESENTATION_ExSyn/proc_00.ys → manual/PRESENTATION_ExSyn/proc_03.ys
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@ -1,3 +1,3 @@
read_verilog proc_00.v
read_verilog proc_03.v
hierarchy -check -top test
proc;;