diff --git a/manual/PRESENTATION_ExSyn.tex b/manual/PRESENTATION_ExSyn.tex index 66ee18046..f2594487a 100644 --- a/manual/PRESENTATION_ExSyn.tex +++ b/manual/PRESENTATION_ExSyn.tex @@ -103,36 +103,35 @@ a call to {\tt proc} is the first command in the actual synthesis procedure after design elaboration. \end{frame} -\begin{frame}[fragile]{\subsecname{} -- Example 1/TBD} -\begin{columns} -\column[t]{5cm} -\lstinputlisting[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=verilog]{PRESENTATION_ExSyn/proc_00.v} -\column[t]{5cm} -\lstinputlisting[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, frame=single]{PRESENTATION_ExSyn/proc_00.ys} -\end{columns} -% \includegraphics[width=\linewidth,trim=0 0cm 0 0cm]{PRESENTATION_ExSyn/proc_00.pdf} -\hfil\includegraphics[width=8cm,trim=0 0cm 0 0cm]{PRESENTATION_ExSyn/proc_00.pdf} -\end{frame} - -\begin{frame}[t, fragile]{\subsecname{} -- Example 2/TBD} -\vbox to 0cm{\includegraphics[width=\linewidth,trim=0cm 0cm 0cm -2.5cm]{PRESENTATION_ExSyn/proc_01.pdf}} -\vskip-1cm +\begin{frame}[fragile]{\subsecname{} -- Example 1/3} \begin{columns} \column[t]{5cm} \lstinputlisting[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=verilog]{PRESENTATION_ExSyn/proc_01.v} \column[t]{5cm} \lstinputlisting[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, frame=single]{PRESENTATION_ExSyn/proc_01.ys} \end{columns} +\hfil\includegraphics[width=8cm,trim=0 0cm 0 0cm]{PRESENTATION_ExSyn/proc_01.pdf} \end{frame} -\begin{frame}[t, fragile]{\subsecname{} -- Example 3/TBD} -\vbox to 0cm{\includegraphics[width=\linewidth,trim=0cm 0cm 0cm -1.5cm]{PRESENTATION_ExSyn/proc_02.pdf}} +\begin{frame}[t, fragile]{\subsecname{} -- Example 2/3} +\vbox to 0cm{\includegraphics[width=\linewidth,trim=0cm 0cm 0cm -2.5cm]{PRESENTATION_ExSyn/proc_02.pdf}\vss} \vskip-1cm \begin{columns} \column[t]{5cm} -\lstinputlisting[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, frame=single]{PRESENTATION_ExSyn/proc_02.ys} -\column[t]{5cm} \lstinputlisting[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=verilog]{PRESENTATION_ExSyn/proc_02.v} +\column[t]{5cm} +\lstinputlisting[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, frame=single]{PRESENTATION_ExSyn/proc_02.ys} +\end{columns} +\end{frame} + +\begin{frame}[t, fragile]{\subsecname{} -- Example 3/3} +\vbox to 0cm{\includegraphics[width=\linewidth,trim=0cm 0cm 0cm -1.5cm]{PRESENTATION_ExSyn/proc_03.pdf}\vss} +\vskip-1cm +\begin{columns} +\column[t]{5cm} +\lstinputlisting[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, frame=single]{PRESENTATION_ExSyn/proc_03.ys} +\column[t]{5cm} +\lstinputlisting[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=verilog]{PRESENTATION_ExSyn/proc_03.v} \end{columns} \end{frame} @@ -166,6 +165,50 @@ proc; opt; memory; opt_const;; fsm;; \end{lstlisting} \end{frame} +\begin{frame}[t, fragile]{\subsecname{} -- Example 1/4} +\vbox to 0cm{\includegraphics[width=\linewidth,trim=0cm 0cm 0cm -0.5cm]{PRESENTATION_ExSyn/opt_01.pdf}\vss} +\vskip-1cm +\begin{columns} +\column[t]{5cm} +\lstinputlisting[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, frame=single]{PRESENTATION_ExSyn/opt_01.ys} +\column[t]{5cm} +\lstinputlisting[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=verilog]{PRESENTATION_ExSyn/opt_01.v} +\end{columns} +\end{frame} + +\begin{frame}[t, fragile]{\subsecname{} -- Example 2/4} +\vbox to 0cm{\includegraphics[width=\linewidth,trim=0cm 0cm 0cm 0cm]{PRESENTATION_ExSyn/opt_02.pdf}\vss} +\vskip-1cm +\begin{columns} +\column[t]{5cm} +\lstinputlisting[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, frame=single]{PRESENTATION_ExSyn/opt_02.ys} +\column[t]{5cm} +\lstinputlisting[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=verilog]{PRESENTATION_ExSyn/opt_02.v} +\end{columns} +\end{frame} + +\begin{frame}[t, fragile]{\subsecname{} -- Example 3/4} +\vbox to 0cm{\includegraphics[width=\linewidth,trim=0cm 0cm 0cm -2cm]{PRESENTATION_ExSyn/opt_03.pdf}\vss} +\vskip-1cm +\begin{columns} +\column[t]{5cm} +\lstinputlisting[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, frame=single]{PRESENTATION_ExSyn/opt_03.ys} +\column[t]{5cm} +\lstinputlisting[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=verilog]{PRESENTATION_ExSyn/opt_03.v} +\end{columns} +\end{frame} + +\begin{frame}[t, fragile]{\subsecname{} -- Example 4/4} +\vbox to 0cm{\hskip6cm\includegraphics[width=6cm,trim=0cm 0cm 0cm -3cm]{PRESENTATION_ExSyn/opt_04.pdf}\vss} +\vskip-1cm +\begin{columns} +\column[t]{5cm} +\lstinputlisting[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=verilog]{PRESENTATION_ExSyn/opt_04.v} +\column[t]{5cm} +\lstinputlisting[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, frame=single]{PRESENTATION_ExSyn/opt_04.ys} +\end{columns} +\end{frame} + %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% \subsection{When to use ``opt'' or ``clean''} @@ -222,7 +265,28 @@ For example: \begin{lstlisting}[xleftmargin=0.5cm, basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont] memory -nomap; techmap -map my_memory_map.v; memory_map \end{lstlisting} +\end{frame} +\begin{frame}[t, fragile]{\subsecname{} -- Example 1/TBD} +\vbox to 0cm{\includegraphics[width=\linewidth,trim=0cm 0cm 0cm -10cm]{PRESENTATION_ExSyn/memory_01.pdf}\vss} +\vskip-1cm +\begin{columns} +\column[t]{5cm} +\lstinputlisting[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, frame=single]{PRESENTATION_ExSyn/memory_01.ys} +\column[t]{5cm} +\lstinputlisting[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=verilog]{PRESENTATION_ExSyn/memory_01.v} +\end{columns} +\end{frame} + +\begin{frame}[t, fragile]{\subsecname{} -- Example 2/TBD} +\vbox to 0cm{\hfill\includegraphics[width=7.5cm,trim=0cm 0cm 0cm -6cm]{PRESENTATION_ExSyn/memory_02.pdf}\vss} +\vskip-1cm +\begin{columns} +\column[t]{5cm} +\lstinputlisting[basicstyle=\ttfamily\fontsize{6pt}{8pt}\selectfont, language=verilog]{PRESENTATION_ExSyn/memory_02.v} +\column[t]{5cm} +\lstinputlisting[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, frame=single]{PRESENTATION_ExSyn/memory_02.ys} +\end{columns} \end{frame} %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% diff --git a/manual/PRESENTATION_ExSyn/Makefile b/manual/PRESENTATION_ExSyn/Makefile index 0450075db..7c343c4d6 100644 --- a/manual/PRESENTATION_ExSyn/Makefile +++ b/manual/PRESENTATION_ExSyn/Makefile @@ -1,12 +1,18 @@ -all: proc_00.pdf proc_01.pdf proc_02.pdf +TARGETS += proc_01 proc_02 proc_03 +TARGETS += opt_01 opt_02 opt_03 opt_04 +TARGETS += memory_01 memory_02 -proc_00.pdf: proc_00.v proc_00.ys - ../../yosys -p 'script proc_00.ys; show -notitle -prefix proc_00 -format pdf' +all: $(addsuffix .pdf,$(TARGETS)) -proc_01.pdf: proc_01.v proc_01.ys - ../../yosys -p 'script proc_01.ys; show -notitle -prefix proc_01 -format pdf' +define make_pdf_template +$(1).pdf: $(1).v $(1).ys + ../../yosys -p 'script $(1).ys; show -notitle -prefix $(1) -format pdf' +endef -proc_02.pdf: proc_02.v proc_02.ys - ../../yosys -p 'script proc_02.ys; show -notitle -prefix proc_02 -format pdf' +$(foreach trg,$(TARGETS),$(eval $(call make_pdf_template,$(trg)))) + +clean: + rm -f $(addsuffix .pdf,$(TARGETS)) + rm -f $(addsuffix .dot,$(TARGETS)) diff --git a/manual/PRESENTATION_ExSyn/memory_01.v b/manual/PRESENTATION_ExSyn/memory_01.v new file mode 100644 index 000000000..0a3f9acd7 --- /dev/null +++ b/manual/PRESENTATION_ExSyn/memory_01.v @@ -0,0 +1,9 @@ +module test(input CLK, ADDR, + input [7:0] DIN, + output reg [7:0] DOUT); + reg [7:0] mem [0:1]; + always @(posedge CLK) begin + mem[ADDR] <= DIN; + DOUT <= mem[ADDR]; + end +endmodule diff --git a/manual/PRESENTATION_ExSyn/memory_01.ys b/manual/PRESENTATION_ExSyn/memory_01.ys new file mode 100644 index 000000000..2ffd8223a --- /dev/null +++ b/manual/PRESENTATION_ExSyn/memory_01.ys @@ -0,0 +1,3 @@ +read_verilog memory_01.v +hierarchy -check -top test +proc;; memory; opt diff --git a/manual/PRESENTATION_ExSyn/memory_02.v b/manual/PRESENTATION_ExSyn/memory_02.v new file mode 100644 index 000000000..dbe86ed18 --- /dev/null +++ b/manual/PRESENTATION_ExSyn/memory_02.v @@ -0,0 +1,27 @@ +module test( + input WR1_CLK, WR2_CLK, + input WR1_WEN, WR2_WEN, + input [7:0] WR1_ADDR, WR2_ADDR, + input [7:0] WR1_DATA, WR2_DATA, + input RD1_CLK, RD2_CLK, + input [7:0] RD1_ADDR, RD2_ADDR, + output reg [7:0] RD1_DATA, RD2_DATA +); + +reg [7:0] memory [0:255]; + +always @(posedge WR1_CLK) + if (WR1_WEN) + memory[WR1_ADDR] <= WR1_DATA; + +always @(posedge WR2_CLK) + if (WR2_WEN) + memory[WR2_ADDR] <= WR2_DATA; + +always @(posedge RD1_CLK) + RD1_DATA <= memory[RD1_ADDR]; + +always @(posedge RD2_CLK) + RD2_DATA <= memory[RD2_ADDR]; + +endmodule diff --git a/manual/PRESENTATION_ExSyn/memory_02.ys b/manual/PRESENTATION_ExSyn/memory_02.ys new file mode 100644 index 000000000..9da6fda54 --- /dev/null +++ b/manual/PRESENTATION_ExSyn/memory_02.ys @@ -0,0 +1,4 @@ +read_verilog memory_02.v +hierarchy -check -top test +proc;; memory -nomap +opt -mux_undef -mux_bool diff --git a/manual/PRESENTATION_ExSyn/opt_01.v b/manual/PRESENTATION_ExSyn/opt_01.v new file mode 100644 index 000000000..5d3c1ea49 --- /dev/null +++ b/manual/PRESENTATION_ExSyn/opt_01.v @@ -0,0 +1,3 @@ +module test(input A, B, output Y); +assign Y = A ? A ? B : 1'b1 : B; +endmodule diff --git a/manual/PRESENTATION_ExSyn/opt_01.ys b/manual/PRESENTATION_ExSyn/opt_01.ys new file mode 100644 index 000000000..34ed123be --- /dev/null +++ b/manual/PRESENTATION_ExSyn/opt_01.ys @@ -0,0 +1,3 @@ +read_verilog opt_01.v +hierarchy -check -top test +opt diff --git a/manual/PRESENTATION_ExSyn/opt_02.v b/manual/PRESENTATION_ExSyn/opt_02.v new file mode 100644 index 000000000..762fc1a89 --- /dev/null +++ b/manual/PRESENTATION_ExSyn/opt_02.v @@ -0,0 +1,3 @@ +module test(input A, output Y, Z); +assign Y = A == A, Z = A != A; +endmodule diff --git a/manual/PRESENTATION_ExSyn/opt_02.ys b/manual/PRESENTATION_ExSyn/opt_02.ys new file mode 100644 index 000000000..fc92a636e --- /dev/null +++ b/manual/PRESENTATION_ExSyn/opt_02.ys @@ -0,0 +1,3 @@ +read_verilog opt_02.v +hierarchy -check -top test +opt diff --git a/manual/PRESENTATION_ExSyn/opt_03.v b/manual/PRESENTATION_ExSyn/opt_03.v new file mode 100644 index 000000000..134161bb8 --- /dev/null +++ b/manual/PRESENTATION_ExSyn/opt_03.v @@ -0,0 +1,4 @@ +module test(input [3:0] A, B, + output [3:0] Y, Z); +assign Y = A + B, Z = B + A; +endmodule diff --git a/manual/PRESENTATION_ExSyn/opt_03.ys b/manual/PRESENTATION_ExSyn/opt_03.ys new file mode 100644 index 000000000..282f06dde --- /dev/null +++ b/manual/PRESENTATION_ExSyn/opt_03.ys @@ -0,0 +1,3 @@ +read_verilog opt_03.v +hierarchy -check -top test +opt diff --git a/manual/PRESENTATION_ExSyn/opt_04.v b/manual/PRESENTATION_ExSyn/opt_04.v new file mode 100644 index 000000000..2ed447639 --- /dev/null +++ b/manual/PRESENTATION_ExSyn/opt_04.v @@ -0,0 +1,19 @@ +module test(input CLK, ARST, + output [7:0] Q1, Q2, Q3); + +wire NO_CLK = 0; + +always @(posedge CLK, posedge ARST) + if (ARST) + Q1 <= 42; + +always @(posedge NO_CLK, posedge ARST) + if (ARST) + Q2 <= 42; + else + Q2 <= 23; + +always @(posedge CLK) + Q3 <= 42; + +endmodule diff --git a/manual/PRESENTATION_ExSyn/opt_04.ys b/manual/PRESENTATION_ExSyn/opt_04.ys new file mode 100644 index 000000000..f5ddae29f --- /dev/null +++ b/manual/PRESENTATION_ExSyn/opt_04.ys @@ -0,0 +1,3 @@ +read_verilog opt_04.v +hierarchy -check -top test +proc; opt diff --git a/manual/PRESENTATION_ExSyn/proc_00.v b/manual/PRESENTATION_ExSyn/proc_00.v deleted file mode 100644 index 612863195..000000000 --- a/manual/PRESENTATION_ExSyn/proc_00.v +++ /dev/null @@ -1,7 +0,0 @@ -module test(input D, C, R, output reg Q); - always @(posedge C, posedge R) - if (R) - Q <= 0; - else - Q <= D; -endmodule diff --git a/manual/PRESENTATION_ExSyn/proc_01.v b/manual/PRESENTATION_ExSyn/proc_01.v index 8e440f6ce..612863195 100644 --- a/manual/PRESENTATION_ExSyn/proc_01.v +++ b/manual/PRESENTATION_ExSyn/proc_01.v @@ -1,8 +1,7 @@ -module test(input D, C, R, RV, - output reg Q); +module test(input D, C, R, output reg Q); always @(posedge C, posedge R) if (R) - Q <= RV; + Q <= 0; else Q <= D; endmodule diff --git a/manual/PRESENTATION_ExSyn/proc_02.v b/manual/PRESENTATION_ExSyn/proc_02.v index a89c965e4..8e440f6ce 100644 --- a/manual/PRESENTATION_ExSyn/proc_02.v +++ b/manual/PRESENTATION_ExSyn/proc_02.v @@ -1,10 +1,8 @@ -module test(input A, B, C, D, E, - output reg Y); - always @* begin - Y <= A; - if (B) - Y <= C; - if (D) - Y <= E; - end +module test(input D, C, R, RV, + output reg Q); + always @(posedge C, posedge R) + if (R) + Q <= RV; + else + Q <= D; endmodule diff --git a/manual/PRESENTATION_ExSyn/proc_03.v b/manual/PRESENTATION_ExSyn/proc_03.v new file mode 100644 index 000000000..a89c965e4 --- /dev/null +++ b/manual/PRESENTATION_ExSyn/proc_03.v @@ -0,0 +1,10 @@ +module test(input A, B, C, D, E, + output reg Y); + always @* begin + Y <= A; + if (B) + Y <= C; + if (D) + Y <= E; + end +endmodule diff --git a/manual/PRESENTATION_ExSyn/proc_00.ys b/manual/PRESENTATION_ExSyn/proc_03.ys similarity index 59% rename from manual/PRESENTATION_ExSyn/proc_00.ys rename to manual/PRESENTATION_ExSyn/proc_03.ys index 6440efd36..3e7e6ddae 100644 --- a/manual/PRESENTATION_ExSyn/proc_00.ys +++ b/manual/PRESENTATION_ExSyn/proc_03.ys @@ -1,3 +1,3 @@ -read_verilog proc_00.v +read_verilog proc_03.v hierarchy -check -top test proc;;