Added stubnets example to manual prog chapter

manual/CHAPTER_Prog.tex

@@ -11,3 +11,11 @@ with an example module.
 \section{Internal Utility Libraries}
 \section{Loadable Modules}
 
+\section{Example Module}
+
+\lstinputlisting[title=stubnets.cc,numbers=left,frame=single,language=C++]{FILES_Prog/stubnets.cc}
+
+\lstinputlisting[title=Makefile,numbers=left,frame=single,language=make]{FILES_Prog/Makefile}
+
+\lstinputlisting[title=test.v,numbers=left,frame=single,language=Verilog]{FILES_Prog/test.v}
+

manual/FILES_Prog/Makefile

@@ -1,14 +1,13 @@
-
 test: stubnets.so
-	yosys -q -l test1.log -m ./stubnets.so test.v -p "proc; stubnets"
-	yosys -q -l test2.log -m ./stubnets.so test.v -p "proc; opt; stubnets"
-	yosys -q -l test3.log -m ./stubnets.so test.v -p "proc; techmap; opt; stubnets -report_bits"
+	yosys -ql test1.log -m ./stubnets.so test.v -p "stubnets"
+	yosys -ql test2.log -m ./stubnets.so test.v -p "opt; stubnets"
+	yosys -ql test3.log -m ./stubnets.so test.v -p "techmap; opt; stubnets -report_bits"
 	tail test1.log test2.log test3.log
 
 stubnets.so: stubnets.cc
-	$(shell yosys-config --cxx --cxxflags --ldflags -o stubnets.so -shared stubnets.cc --ldlibs )
+	$(shell yosys-config --cxx --cxxflags --ldflags -o stubnets.so \
+	                           -shared stubnets.cc --ldlibs )
 
 clean:
 	rm -f test1.log test2.log test3.log
 	rm -f stubnets.so stubnets.d
-

manual/FILES_Prog/stubnets.cc

@@ -67,7 +67,8 @@ static void find_stub_nets(RTLIL::Design *design, RTLIL::Module *module, bool re
 		// for each bit (unless it is a constant):
 		// check if it is used at least two times and add to stub_bits otherwise
 		for (size_t i = 0; i < sig.chunks.size(); i++)
-			if (sig.chunks[i].wire != NULL && (bit_usage_count[sig.chunks[i]] + usage_offset) < 2)
+			if (sig.chunks[i].wire != NULL && (bit_usage_count[sig.chunks[i]] +
+					usage_offset) < 2)
 				stub_bits.insert(i);
 
 		// continue if no stub bits found