mirror of https://github.com/YosysHQ/yosys.git
Progress on AppNote 011
This commit is contained in:
Clifford Wolf
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325b764341
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cd0324decd
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@ -686,15 +686,16 @@ of the module and wants to carefully read all the debug output created by the
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commands in order to spot a problem. This kind of troubleshooting is much easier
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if the circuit under investigation is encapsulated in a separate module.
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\begin{figure}[b]
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\includegraphics[width=\linewidth,trim=0 0cm 0 0cm]{APPNOTE_011_Design_Investigation/submod_00.pdf} \\ \centerline{\tt memdemo} \vskip1em
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\includegraphics[width=\linewidth,trim=0 0cm 0 0cm]{APPNOTE_011_Design_Investigation/submod_01.pdf} \\ \centerline{\tt scramble} \vskip1em
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\includegraphics[width=\linewidth,trim=0 0cm 0 0cm]{APPNOTE_011_Design_Investigation/submod_02.pdf} \\ \centerline{\tt outstage} \vskip1em
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\includegraphics[width=\linewidth,trim=0 0cm 0 0cm]{APPNOTE_011_Design_Investigation/submod_03.pdf} \\ \centerline{\tt selstage} \vskip1em
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Fig.~\ref{submod} shows how the {\tt submod} command can be used to split the
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circuit from Fig.~\ref{memdemo_src} and \ref{memdemo_00} into its components.
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The {\tt -name} option can is used to specify the name of the new module and
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also the name of the new cell in the current module.
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\begin{figure}[t]
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\includegraphics[width=\linewidth,trim=0 1.3cm 0 0cm]{APPNOTE_011_Design_Investigation/submod_00.pdf} \\ \centerline{\tt memdemo} \vskip1em\par
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\includegraphics[width=\linewidth,trim=0 1.3cm 0 0cm]{APPNOTE_011_Design_Investigation/submod_01.pdf} \\ \centerline{\tt scramble} \vskip1em\par
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\includegraphics[width=\linewidth,trim=0 1.3cm 0 0cm]{APPNOTE_011_Design_Investigation/submod_02.pdf} \\ \centerline{\tt outstage} \vskip1em\par
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\includegraphics[width=\linewidth,trim=0 1.3cm 0 0cm]{APPNOTE_011_Design_Investigation/submod_03.pdf} \\ \centerline{\tt selstage} \vskip1em\par
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\begin{lstlisting}[basicstyle=\ttfamily\scriptsize]
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select -set outstage y %ci2:+$dff[Q,D] %ci*:-$mux[S]:-$dff
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select -set selstage y %ci2:+$dff[Q,D] %ci*:-$dff @outstage %d
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@ -707,8 +708,61 @@ submod -name selstage @selstage
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\label{submod}
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\end{figure}
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\subsection{Evaluation of combinatorial circuits}
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\FIXME{} --- submod, eval, sat
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The {\tt eval} command can be used to evaluate combinatorial circuits.
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For example (see Fig.~\ref{submod} for the circuit diagram of {\tt selstage}):
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{\scriptsize
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\begin{verbatim}
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yosys [selstage]> eval -set s2,s1 4'b1001 -set d 4'hc -show n2 -show n1
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9. Executing EVAL pass (evaluate the circuit given an input).
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Full command line: eval -set s2,s1 4'b1001 -set d 4'hc -show n2 -show n1
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Eval result: \n2 = 2'10.
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Eval result: \n1 = 2'10.
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\end{verbatim}
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\par}
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So the {\tt -set} option is used to set input values and the {\tt -show} option
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is used to specify the nets to evaluate. If no {\tt -show} option is specified,
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all selected output ports are used per default.
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If a necessary input value is not given, an error is produced. The option
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{\tt -set-undef} can be used to instead set all unspecified input nets to
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undef ({\tt x}).
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The {\tt -table} option can be used to create a truth table. For example:
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{\scriptsize
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\begin{verbatim}
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yosys [selstage]> eval -set-undef -set d[3:1] 0 -table s1,d[0]
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15. Executing EVAL pass (evaluate the circuit given an input).
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Full command line: eval -set-undef -set d[3:1] 0 -table s1,d[0]
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\s1 \d [0] | \n1 \n2
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---- ------ | ---- ----
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2'00 1'0 | 2'00 2'00
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2'00 1'1 | 2'xx 2'00
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2'01 1'0 | 2'00 2'00
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2'01 1'1 | 2'xx 2'01
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2'10 1'0 | 2'00 2'00
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2'10 1'1 | 2'xx 2'10
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2'11 1'0 | 2'00 2'00
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2'11 1'1 | 2'xx 2'11
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Assumend undef (x) value for the following singals: \s2
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\end{verbatim}
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}
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\subsection{Solving combinatorial SAT problems}
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\FIXME
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\subsection{Solving sequential SAT problems}
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\FIXME
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\section{Conclusion}
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\label{conclusion}
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@ -1,34 +1,23 @@
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#!/bin/bash
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../../yosys example.ys
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../../yosys -p 'proc; opt; show -format dot -prefix splice' splice.v
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../../yosys -p 'techmap; abc -liberty ../../techlibs/cmos/cmos_cells.lib;; show -format dot -prefix cmos_00' cmos.v
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../../yosys -p 'techmap; splitnets -ports; abc -liberty ../../techlibs/cmos/cmos_cells.lib;; show -lib ../../techlibs/cmos/cmos_cells.v -format dot -prefix cmos_01' cmos.v
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../../yosys -p 'opt; cd sumprod; select a:sumstuff; show -format dot -prefix sumprod_00' sumprod.v
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../../yosys -p 'opt; cd sumprod; select a:sumstuff %x; show -format dot -prefix sumprod_01' sumprod.v
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../../yosys -p 'opt; cd sumprod; select prod; show -format dot -prefix sumprod_02' sumprod.v
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../../yosys -p 'opt; cd sumprod; select prod %ci; show -format dot -prefix sumprod_03' sumprod.v
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../../yosys -p 'opt; cd sumprod; select prod %ci2; show -format dot -prefix sumprod_04' sumprod.v
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../../yosys -p 'opt; cd sumprod; select prod %ci3; show -format dot -prefix sumprod_05' sumprod.v
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../../yosys -p 'proc; opt; memory; opt; cd memdemo; show -format dot -prefix memdemo_00' memdemo.v
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../../yosys -p 'proc; opt; memory; opt; cd memdemo; show -format dot -prefix memdemo_01 y %ci2:+$dff[Q,D] %ci*:-$mux[S]:-$dff' memdemo.v
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../../yosys submod.ys
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sed -i '/^label=/ d;' example_*.dot splice.dot cmos_*.dot sumprod_*.dot memdemo_*.dot submod_*.dot
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dot -Tpdf -o example_00.pdf example_00.dot
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dot -Tpdf -o example_01.pdf example_01.dot
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dot -Tpdf -o example_02.pdf example_02.dot
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dot -Tpdf -o example_03.pdf example_03.dot
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dot -Tpdf -o splice.pdf splice.dot
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dot -Tpdf -o cmos_00.pdf cmos_00.dot
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dot -Tpdf -o cmos_01.pdf cmos_01.dot
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dot -Tpdf -o sumprod_00.pdf sumprod_00.dot
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dot -Tpdf -o sumprod_01.pdf sumprod_01.dot
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dot -Tpdf -o sumprod_02.pdf sumprod_02.dot
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dot -Tpdf -o sumprod_03.pdf sumprod_03.dot
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dot -Tpdf -o sumprod_04.pdf sumprod_04.dot
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dot -Tpdf -o sumprod_05.pdf sumprod_05.dot
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dot -Tpdf -o memdemo_00.pdf memdemo_00.dot
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dot -Tpdf -o memdemo_01.pdf memdemo_01.dot
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dot -Tpdf -o submod_00.pdf submod_00.dot
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dot -Tpdf -o submod_01.pdf submod_01.dot
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dot -Tpdf -o submod_02.pdf submod_02.dot
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dot -Tpdf -o submod_03.pdf submod_03.dot
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set -ex
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if true; then
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rm -f *.dot
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../../yosys example.ys
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../../yosys -p 'proc; opt; show -format dot -prefix splice' splice.v
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../../yosys -p 'techmap; abc -liberty ../../techlibs/cmos/cmos_cells.lib;; show -format dot -prefix cmos_00' cmos.v
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../../yosys -p 'techmap; splitnets -ports; abc -liberty ../../techlibs/cmos/cmos_cells.lib;; show -lib ../../techlibs/cmos/cmos_cells.v -format dot -prefix cmos_01' cmos.v
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../../yosys -p 'opt; cd sumprod; select a:sumstuff; show -format dot -prefix sumprod_00' sumprod.v
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../../yosys -p 'opt; cd sumprod; select a:sumstuff %x; show -format dot -prefix sumprod_01' sumprod.v
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../../yosys -p 'opt; cd sumprod; select prod; show -format dot -prefix sumprod_02' sumprod.v
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../../yosys -p 'opt; cd sumprod; select prod %ci; show -format dot -prefix sumprod_03' sumprod.v
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../../yosys -p 'opt; cd sumprod; select prod %ci2; show -format dot -prefix sumprod_04' sumprod.v
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../../yosys -p 'opt; cd sumprod; select prod %ci3; show -format dot -prefix sumprod_05' sumprod.v
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../../yosys -p 'proc; opt; memory; opt; cd memdemo; show -format dot -prefix memdemo_00' memdemo.v
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../../yosys -p 'proc; opt; memory; opt; cd memdemo; show -format dot -prefix memdemo_01 y %ci2:+$dff[Q,D] %ci*:-$mux[S]:-$dff' memdemo.v
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../../yosys submod.ys
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sed -i '/^label=/ d;' *.dot
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fi
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for dot_file in *.dot; do
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pdf_file=${dot_file#.dot}.pdf
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dot -Tpdf -o example_00.pdf example_00.dot
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done
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@ -4,6 +4,11 @@ set -ex
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for job in APPNOTE_010_Verilog_to_BLIF APPNOTE_011_Design_Investigation
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do
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[ -f $job.ok -a $job.ok -nt $job.tex ] && continue
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if [ -f $job/make.sh ]; then
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cd $job
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bash make.sh
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cd ..
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fi
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old_md5=$([ -f $job.aux ] && md5sum < $job.aux || true)
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while
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pdflatex -shell-escape -halt-on-error $job.tex
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