mirror of https://github.com/YosysHQ/yosys.git
Fixed manual/CHAPTER_Prog/stubnets.cc
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@ -62,7 +62,7 @@ static void find_stub_nets(RTLIL::Design *design, RTLIL::Module *module, bool re
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// for each bit (unless it is a constant):
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// check if it is used at least two times and add to stub_bits otherwise
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for (size_t i = 0; i < SIZE(sig); i++)
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for (int i = 0; i < SIZE(sig); i++)
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if (sig[i].wire != NULL && (bit_usage_count[sig[i]] + usage_offset) < 2)
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stub_bits.insert(i);
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@ -72,7 +72,7 @@ static void find_stub_nets(RTLIL::Design *design, RTLIL::Module *module, bool re
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// report stub bits and/or stub wires, don't report single bits
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// if called with report_bits set to false.
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if (int(stub_bits.size()) == sig.width) {
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if (SIZE(stub_bits) == SIZE(sig)) {
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log(" found stub wire: %s\n", RTLIL::id2cstr(wire->name));
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} else {
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if (!report_bits)
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