Clifford Wolf
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ecc30255ba
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Added proper === and !== support in constant expressions
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2013-12-27 13:50:08 +01:00 |
Clifford Wolf
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891e4b5b0d
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Keep strings as strings in const ternary and concat
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2013-12-05 13:26:17 +01:00 |
Clifford Wolf
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e935bb6eda
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Added const folding support for $signed and $unsigned
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2013-12-05 13:09:41 +01:00 |
Clifford Wolf
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5c39948ead
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Added AstNode::mkconst_str API
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2013-12-05 12:53:49 +01:00 |
Clifford Wolf
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853538d78b
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Fixed generate-for (and disabled double warning for auto-wire)
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2013-12-04 21:33:00 +01:00 |
Clifford Wolf
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3c220e0b32
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Added support for $clog2 system function
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2013-12-04 21:19:54 +01:00 |
Clifford Wolf
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4a4a3fc337
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Various improvements in support for generate statements
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2013-12-04 21:06:54 +01:00 |
Clifford Wolf
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f4b46ed31e
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Replaced signed_parameters API with CONST_FLAG_SIGNED
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2013-12-04 14:24:44 +01:00 |
Clifford Wolf
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93a70959f3
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Replaced RTLIL::Const::str with generic decoder method
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2013-12-04 14:14:05 +01:00 |
Clifford Wolf
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507c63d112
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Added support for local regs in named blocks
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2013-12-04 09:10:16 +01:00 |
Clifford Wolf
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10aa08dca1
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Fixed temp net name generation in rtlil process generator for abbreviated name matching
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2013-11-28 21:47:08 +01:00 |
Clifford Wolf
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0e52f3fa01
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Added "src" attribute to processes
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2013-11-28 17:37:50 +01:00 |
Clifford Wolf
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8dafecd34d
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Added module->avail_parameters (for advanced techmap features)
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2013-11-24 20:29:07 +01:00 |
Clifford Wolf
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7d9a90396d
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Added verilog frontend -ignore_redef option
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2013-11-24 19:57:42 +01:00 |
Clifford Wolf
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019b301541
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Early wire/reg/parameter width calculation in ast/simplify
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2013-11-24 19:40:23 +01:00 |
Clifford Wolf
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f71e27dbf1
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Remove auto_wire framework (smarter than the verilog standard)
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2013-11-24 17:29:11 +01:00 |
Clifford Wolf
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609caa23b5
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Implemented correct handling of signed module parameters
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2013-11-24 17:17:21 +01:00 |
Clifford Wolf
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295e352ba6
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Renamed "placeholder" to "blackbox"
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2013-11-22 15:01:12 +01:00 |
Clifford Wolf
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95c94a02fc
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Fixed async proc detection in mem2reg
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2013-11-21 21:26:56 +01:00 |
Clifford Wolf
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09471846c5
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Major improvements in mem2reg and added "init" sync rules
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2013-11-21 13:49:00 +01:00 |
Clifford Wolf
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65ad556f3d
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Another name resolution bugfix for generate blocks
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2013-11-20 13:57:40 +01:00 |
Clifford Wolf
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c4c299eb5a
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Do not allow memory bit select on the left side of an assignment
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2013-11-20 12:18:46 +01:00 |
Clifford Wolf
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ac2be2d892
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Fixed name resolution of local tasks and functions in generate block
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2013-11-20 11:05:58 +01:00 |
Clifford Wolf
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19dba2561e
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Implemented part/bit select on memory read
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2013-11-20 10:51:32 +01:00 |
Clifford Wolf
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4f2edcf2f9
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Fixed two bugs in mem2reg functionality in AST frontend
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2013-11-18 19:55:12 +01:00 |
Clifford Wolf
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79910a5547
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Added dumping of attributes in AST frontend
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2013-11-18 19:54:36 +01:00 |
Clifford Wolf
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2a25e3bca3
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Fixed parsing of default cases when not last case
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2013-11-18 16:10:50 +01:00 |
Clifford Wolf
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de03184150
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Fixed mem2reg for reg usage outside always block
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2013-11-18 12:35:41 +01:00 |
Clifford Wolf
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e5b974fa2a
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Cleanups and bugfixes in response to new internal cell checker
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2013-11-11 00:39:45 +01:00 |
Clifford Wolf
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378cc509cd
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Call internal checker more often
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2013-11-10 23:24:21 +01:00 |
Clifford Wolf
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259cc1391e
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More undef-propagation related fixes
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2013-11-08 11:40:36 +01:00 |
Clifford Wolf
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9f49d538e1
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Fixed handling of different signedness in power operands
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2013-11-08 11:06:11 +01:00 |
Clifford Wolf
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4abc8e695a
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Implemented const folding of ternary op with undef select
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2013-11-08 04:44:09 +01:00 |
Clifford Wolf
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fc6dc0d7b8
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Fixed handling of power operator
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2013-11-07 22:20:00 +01:00 |
Clifford Wolf
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d7cb62ac96
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Fixed more extend vs. extend_u0 issues
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2013-11-07 19:20:20 +01:00 |
Clifford Wolf
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02f4f89fdb
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Disabled const folding of ternary op when select is undef
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2013-11-07 18:18:16 +01:00 |
Clifford Wolf
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947bd9b96b
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Renamed extend_un0() to extend_u0() and use it in genrtlil
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2013-11-07 18:17:10 +01:00 |
Clifford Wolf
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ed4bcd52e5
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Fixed sign handling in constants
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2013-11-07 14:53:10 +01:00 |
Clifford Wolf
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83a8b8b5ca
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Fixed const folding in corner cases with parameters
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2013-11-07 14:08:53 +01:00 |
Clifford Wolf
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b52bf379b9
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Fixed width detection for replicate operator
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2013-11-07 12:43:04 +01:00 |
Clifford Wolf
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536621a98b
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Fixed at_zero evaluation of dynamic ranges
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2013-11-07 11:25:19 +01:00 |
Clifford Wolf
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f050c40519
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Various fixes for correct parameter support
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2013-11-07 10:02:11 +01:00 |
Clifford Wolf
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160adccca2
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Fixed the fix for propagation of width hints for $signed() and $unsigned()
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2013-11-07 03:01:28 +01:00 |
Clifford Wolf
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7fe13faefa
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Fixed propagation of width hints for $signed() and $unsigned()
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2013-11-06 22:41:21 +01:00 |
Clifford Wolf
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baeca48a24
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Additional fixes for undef propagation in concat and replicate ops
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2013-11-06 21:16:54 +01:00 |
Clifford Wolf
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6fcbc79b5c
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Improved width extension with regard to undef propagation
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2013-11-06 21:05:11 +01:00 |
Clifford Wolf
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f2786df146
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Another fix for early width and sign detection in ast simplifier
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2013-11-04 21:29:36 +01:00 |
Clifford Wolf
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d38c67f53d
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Fixed const folding of ternary operator
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2013-11-04 16:46:14 +01:00 |
Clifford Wolf
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8d226da694
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Use proper bit width ans sign extension for const folding
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2013-11-04 15:37:09 +01:00 |
Clifford Wolf
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1325514d33
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Fixes for early width and sign detection in ast simplifier
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2013-11-04 08:28:13 +01:00 |
Clifford Wolf
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472117d532
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further improved early width and sign detection in ast simplifier
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2013-11-04 06:04:42 +01:00 |
Clifford Wolf
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d2b083f5cb
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Fixed detectSignWidthWorker (ast frontend) for AST_CONCAT
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2013-11-03 18:56:45 +01:00 |
Clifford Wolf
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ada80545fa
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Behavior should be identical now to rev. 0b4a64ac6a (next: testing before constfold fixes)
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2013-11-02 21:13:01 +01:00 |
Clifford Wolf
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943329c1dc
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Various ast changes for early expression width detection (prep for constfold fixes)
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2013-11-02 13:00:17 +01:00 |
Clifford Wolf
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23cf23418c
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Fixed handling of boolean attributes (frontends)
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2013-10-24 11:20:13 +02:00 |
Johann Glaser
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6c4cbc03c2
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Added support for notif0/notif1 primitives
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2013-08-20 11:23:59 +02:00 |
Clifford Wolf
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0003743432
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Fixed width and sign detection for ** operator
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2013-08-19 20:58:01 +02:00 |
Clifford Wolf
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8656b1c08f
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Added support for bufif0/bufif1 primitives
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2013-08-19 19:50:04 +02:00 |
Clifford Wolf
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4214561890
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Improved ast dumping (ast/verilog frontend)
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2013-08-19 19:49:14 +02:00 |
Clifford Wolf
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759852914d
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Added support for "2**n" shifter encoding
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2013-08-12 14:47:50 +02:00 |
Clifford Wolf
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c8763301b4
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Added $div and $mod technology mapping
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2013-08-09 17:09:24 +02:00 |
Clifford Wolf
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0f38008ed3
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Added "design" command (-reset, -save, -load)
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2013-07-27 14:27:51 +02:00 |
Clifford Wolf
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3650fd7fbe
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More fixes in ternary op sign handling
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2013-07-12 13:13:04 +02:00 |
Clifford Wolf
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ded769c98c
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Fixed sign handling in ternary operator
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2013-07-12 01:15:37 +02:00 |
Clifford Wolf
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b380c8c790
|
Another vloghammer related bugfix
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2013-07-11 19:24:59 +02:00 |
Clifford Wolf
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ed62fcdbe2
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Fixed sign propagation in bit-wise operators
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2013-07-09 23:53:55 +02:00 |
Clifford Wolf
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5dab327b30
|
More fixes in ast expression sign/width handling
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2013-07-09 23:41:43 +02:00 |
Clifford Wolf
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00a6c1d9a5
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Major redesign of expr width/sign detecion (verilog/ast frontend)
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2013-07-09 14:31:57 +02:00 |
Clifford Wolf
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e8da3ea7b6
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Fixed another bug found using vloghammer
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2013-07-07 16:49:30 +02:00 |
Clifford Wolf
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eff68560a2
|
Fixed AST_CONSTANT node generation
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2013-07-07 15:40:26 +02:00 |
Clifford Wolf
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56432a920f
|
Added defparam support to Verilog/AST frontend
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2013-07-04 14:12:33 +02:00 |
Clifford Wolf
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0c6ffc4c65
|
More fixes for bugs found using xsthammer
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2013-06-13 11:18:45 +02:00 |
Clifford Wolf
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a5c30183b5
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Sign-extension related fixes in SatGen and AST frontend
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2013-06-10 17:10:06 +02:00 |
Clifford Wolf
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59dd02baa2
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Fixes and improvements in AST const folding
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2013-06-10 13:56:03 +02:00 |
Clifford Wolf
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db98a18edb
|
Enabled AST/Verilog front-end optimizations per default
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2013-06-10 13:19:04 +02:00 |
Clifford Wolf
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ed0e2f7a6f
|
Added log_assert() api
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2013-05-24 14:38:36 +02:00 |
Clifford Wolf
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c5ee2b306a
|
Merge branch 'bugfix'
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2013-05-16 16:44:45 +02:00 |
Clifford Wolf
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6cc8e848b6
|
Fixed synthesis of functions in latched blocks
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2013-05-16 16:44:06 +02:00 |
Clifford Wolf
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8f2d90de4f
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Fixed handling of positional module parameters
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2013-04-26 14:40:25 +02:00 |
Clifford Wolf
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453a29c9f6
|
Only use sha1 checksums for names of parametric modules when the verbose form is to long
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2013-04-26 13:13:58 +02:00 |
Clifford Wolf
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e0c408cb4a
|
Fixed a bug in AST frontend for cases with non-blocking assigned variables as case values
|
2013-04-13 21:19:10 +02:00 |
Clifford Wolf
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f1a2fd966f
|
Now only use value from "initial" when no matching "always" block is found
|
2013-03-31 11:51:12 +02:00 |
Clifford Wolf
|
161565be10
|
Added AST_INITIAL (before verilog "initial" was mapped to AST_ALWAYS)
|
2013-03-31 11:19:11 +02:00 |
Clifford Wolf
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7bfc7b61a8
|
Implemented proper handling of stub placeholder modules
|
2013-03-28 09:20:10 +01:00 |
Clifford Wolf
|
7a99349de4
|
Improvements and bugfixes for generate blocks with local signals
|
2013-03-26 11:31:34 +01:00 |
Clifford Wolf
|
6a382f2aba
|
Fixed handling of unconditional generate blocks
|
2013-03-26 09:44:54 +01:00 |
Clifford Wolf
|
227520f94d
|
Added nosync attribute and some async reset related fixes
|
2013-03-25 17:13:14 +01:00 |
Clifford Wolf
|
df9753d398
|
Added mem2reg option to verilog frontend
|
2013-03-24 11:13:32 +01:00 |
Clifford Wolf
|
3a5244e913
|
Another fix in mem2reg ast simplify logic
|
2013-03-24 10:42:08 +01:00 |
Clifford Wolf
|
bb3357c027
|
Improved mem2reg handling in ast simplifier
|
2013-03-24 09:27:01 +01:00 |
Clifford Wolf
|
e45d1c8865
|
Tiny fixes to verilog parser
|
2013-03-23 18:54:31 +01:00 |
Clifford Wolf
|
a321a5c412
|
Moved stand-alone libs to libs/ directory and added libs/subcircuit
|
2013-02-27 09:32:19 +01:00 |
Clifford Wolf
|
4f0c2862a0
|
Added support for verilog genblock[index].member syntax
|
2013-02-26 13:18:22 +01:00 |
Clifford Wolf
|
7764d0ba1d
|
initial import
|
2013-01-05 11:13:26 +01:00 |