riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity
1,396 Commits 85 Branches 48 Tags 64 MiB
Commit Graph

102 Commits

Author SHA1 Message Date
Clifford Wolf 03c96f9ce7 Added "techmap -map %{design-name}" 2014-07-29 16:35:13 +02:00
Clifford Wolf 397b00252d Added $shift and $shiftx cell types (needed for correct part select behavior) 2014-07-29 16:35:13 +02:00
Clifford Wolf 3c45277ee0 Added wire->upto flag for signals such as "wire [0:7] x;" 2014-07-28 12:12:13 +02:00
Clifford Wolf 7bd2d1064f Using log_assert() instead of assert() 2014-07-28 11:27:48 +02:00
Clifford Wolf d86a25f145 Added std::initializer_list<> constructor to SigSpec 2014-07-28 10:52:58 +02:00
Clifford Wolf f99495a895 Added cover() to all SigSpec constructors 2014-07-28 10:52:30 +02:00
Clifford Wolf c4bdba78cb Added proper Design->addModule interface 2014-07-27 21:12:09 +02:00
Clifford Wolf 4be645860b Added RTLIL::SigSpec::remove_const() handling of packed SigSpecs 2014-07-27 14:47:48 +02:00
Clifford Wolf 675cb93da9 Added RTLIL::Module::wire(id) and cell(id) lookup functions 2014-07-27 11:18:31 +02:00
Clifford Wolf 10e5791c5e Refactoring: Renamed RTLIL::Design::modules to modules_ 2014-07-27 11:18:30 +02:00
Clifford Wolf 1c8fdaeef8 Added RTLIL::ObjIterator and RTLIL::ObjRange 2014-07-27 11:18:30 +02:00
Clifford Wolf 4c4b602156 Refactoring: Renamed RTLIL::Module::cells to cells_ 2014-07-27 01:51:45 +02:00
Clifford Wolf f9946232ad Refactoring: Renamed RTLIL::Module::wires to wires_ 2014-07-27 01:49:51 +02:00
Clifford Wolf d68c993ed2 Changed more code to the new RTLIL::Wire constructors 2014-07-26 21:30:38 +02:00
Clifford Wolf 946ddff9ce Changed a lot of code to the new RTLIL::Wire constructors 2014-07-26 20:12:50 +02:00
Clifford Wolf 97a59851a6 Added RTLIL::Cell::has(portname) 2014-07-26 16:11:28 +02:00
Clifford Wolf f8fdc47d33 Manual fixes for new cell connections API 2014-07-26 15:58:23 +02:00
Clifford Wolf b7dda72302 Changed users of cell->connections_ to the new API (sed command) 
git grep -l 'connections_' | xargs sed -i -r -e '
	s/(->|\.)connections_\["([^"]*)"\] = (.*);/\1set("\2", \3);/g;
	s/(->|\.)connections_\["([^"]*)"\]/\1get("\2")/g;
	s/(->|\.)connections_.at\("([^"]*)"\)/\1get("\2")/g;
	s/(->|\.)connections_.push_back/\1connect/g;
	s/(->|\.)connections_/\1connections()/g;'
 2014-07-26 15:58:23 +02:00
Clifford Wolf cd6574ecf6 Added some missing "const" in rtlil.h 2014-07-26 15:58:22 +02:00
Clifford Wolf 7ac9dc7f6e Added RTLIL::Module::connections() 2014-07-26 15:58:21 +02:00
Clifford Wolf b03aec6e32 Added RTLIL::Module::connect(const RTLIL::SigSig&) 2014-07-26 14:31:47 +02:00
Clifford Wolf 3719281ed4 Automatically pack SigSpec on copy/assign 2014-07-26 13:59:30 +02:00
Clifford Wolf e75e495c2b Added new RTLIL::Cell port access methods 2014-07-26 12:22:58 +02:00
Clifford Wolf cc4f10883b Renamed RTLIL::{Module,Cell}::connections to connections_ 2014-07-26 11:58:03 +02:00
Clifford Wolf 4755e14e7b Added copy-constructor-like module->addCell(name, other) method 2014-07-26 00:38:44 +02:00
Clifford Wolf 2bec47a404 Use only module->addCell() and module->remove() to create and delete cells 2014-07-25 17:56:19 +02:00
Clifford Wolf c762050e7f Added RTLIL::SigSpec is_chunk()/as_chunk() API 2014-07-25 14:23:10 +02:00
Clifford Wolf 7f1789ad1b Fixed typo in cover id 2014-07-25 03:41:53 +02:00
Clifford Wolf 6aa792c864 Replaced more old SigChunk programming patterns 2014-07-24 23:10:58 +02:00
Clifford Wolf e589289df7 Some improvements in SigSpec packing/unpacking and checking 2014-07-24 15:05:41 +02:00
Clifford Wolf 22ede43b3f Small changes regarding cover() and check() in SigSpec 2014-07-24 04:46:36 +02:00
Clifford Wolf 798f713629 Added support for YOSYS_COVER_FILE env variable 2014-07-24 04:16:32 +02:00
Clifford Wolf 1b0d5fc22d Added cover() calls to RTLIL::SigSpec methods 2014-07-24 03:50:28 +02:00
Clifford Wolf 82fa356037 Added hashing to RTLIL::SigSpec relational and equal operators 2014-07-23 23:58:03 +02:00
Clifford Wolf f368d792fb Disabled RTLIL::SigSpec::check() in release builds 2014-07-23 21:42:44 +02:00
Clifford Wolf 95ac484548 Fixed release build 2014-07-23 21:38:18 +02:00
Clifford Wolf 2a41afb7b2 Added RTLIL::SigSpec::repeat() 2014-07-23 21:34:14 +02:00
Clifford Wolf c094c53de8 Removed RTLIL::SigSpec::optimize() 2014-07-23 20:32:28 +02:00
Clifford Wolf 8fd8e4a468 Turned RTLIL::SigSpec::optimize() to a no-op: a packed SigSpec is now always optimized 2014-07-23 20:11:55 +02:00
Clifford Wolf a62c21c9c6 Removed RTLIL::SigSpec::expand() method 2014-07-23 19:34:51 +02:00
Clifford Wolf 85db102e13 Replaced RTLIL::SigSpec::operator!=() with inline version 2014-07-23 15:35:09 +02:00
Clifford Wolf ec923652e2 Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 3/3 2014-07-23 09:52:55 +02:00
Clifford Wolf a8d3a68971 Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 2/3 2014-07-23 09:49:43 +02:00
Clifford Wolf 260c19ec5a Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 1/3 2014-07-23 09:34:47 +02:00
Clifford Wolf c61467a32c Some cleanups in RTLIL::SigChunk::SigChunk(const RTLIL::Const&) 2014-07-23 08:59:54 +02:00
Clifford Wolf 115dd959d9 SigSpec refactoring: More cleanups of old SigSpec use pattern 2014-07-22 23:50:21 +02:00
Clifford Wolf fd4cbe6275 SigSpec refactoring: rewrote some RTLIL::SigSpec methods to use unpacked form 2014-07-22 22:26:30 +02:00
Clifford Wolf a97be0828a Removed RTLIL::SigChunk::compare() 2014-07-22 21:40:52 +02:00
Clifford Wolf 08e1e25169 SigSpec refactoring: added RTLIL::SigSpec::bits() and pack/unpack api 2014-07-22 21:33:52 +02:00
Clifford Wolf 28b3fd05fa SigSpec refactoring: change RTLIL::SigSpec::chunks() to be read-only, created interim RTLIL::SigSpec::chunks_rw() 2014-07-22 20:58:44 +02:00