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1429 Commits

Author SHA1 Message Date
whitequark deff6a9546
Merge pull request #2501 from zachjs/genrtlil-tern-sign 
genrtlil: fix mux2rtlil generated wire signedness
 2020-12-23 23:15:56 +00:00
whitequark 8ef6b77dc3
Merge pull request #2476 from zachjs/const-arg-width 
Fix constants bound to single bit arguments (fixes #2383)
 2020-12-23 23:15:30 +00:00
Zachary Snow 999eec5617 genrtlil: fix mux2rtlil generated wire signedness 2020-12-22 17:49:16 -07:00
Zachary Snow 8206546c45 Fix constants bound to single bit arguments (fixes #2383) 2020-12-22 17:01:03 -07:00
whitequark 3e67ab1ebb
Merge pull request #2479 from zachjs/const-arg-hint 
Allow constant function calls in constant function arguments
 2020-12-22 01:31:25 +00:00
Zachary Snow 0d8e5d965f Sign extend port connections where necessary 
- Signed cell outputs are sign extended when bound to larger wires
- Signed connections are sign extended when bound to larger cell inputs
- Sign extension is performed in hierarchy and flatten phases
- genrtlil indirects signed constants through signed wires
- Other phases producing RTLIL may need to be updated to preserve
  signedness information
- Resolves #1418
- Resolves #2265
 2020-12-18 20:33:14 -07:00
Zachary Snow 186d6df4c3 Allow constant function calls in constant function arguments 2020-12-07 13:53:27 -07:00
Claire Xen cf67e6a397
Merge pull request #2133 from dh73/nodev_head 
Adding latch tests for shift&mask AST dynamic part-select enhancements
 2020-11-25 09:44:23 +01:00
David Shah 9f241c9a42 nexus: DSP inference support 
Signed-off-by: David Shah <dave@ds0.me>
 2020-11-20 08:45:55 +00:00
dalance 84ecb321b4 Fix begin/end in generate 2020-11-11 12:03:37 +09:00
Xiretza 86e0440da9
Update nexus arch tests to new harness 2020-10-29 14:42:07 +01:00
Marcelina Kościelnicka d3b6b7fe98 xilinx: Fix attributes_test.ys 
This test pretty much passes by accident — the `prep` command runs
memory_collect without memory_dff first, which prevents merging read
register into the memory, and thus blocks block RAM inference for a
reason completely unrelated to the attribute.

The attribute setting didn't actually work because it was set on the
containing module instead of the actual memory.
 2020-10-24 23:52:37 +02:00
Marcelina Kościelnicka eb76d35e80 memory_dff: Fix needlessly duplicating enable bits. 
When the register being merged into the EN signal happens to be a $sdff,
the current code creates a new $mux for every bit, even if they happen
to be identical (as is usually the case), preventing proper grouping
further down the flow.  Fix this by adding a simple cache.

Fixes #2409.
 2020-10-22 13:03:42 +02:00
Miodrag Milanović ac0bd2ffc4
Merge pull request #2397 from daveshah1/nexus 
synth_nexus: Initial implementation
 2020-10-19 11:20:56 +02:00
David Shah 4d584d9319 synth_nexus: Initial implementation 
Signed-off-by: David Shah <dave@ds0.me>
 2020-10-15 08:52:15 +01:00
Marcelina Kościelnicka 7670a89e1f opt_clean: Better memory handling. 
Previously, `$memwr` and `$meminit` cells were always preserved (along
with the memory itself).  With this change, they are instead part of the
main cell mark-and-sweep pass: a memory (and its `$meminit` and `$memwr`
cells) is only preserved iff any associated `$memrd` cell needs to be
preserved.
 2020-10-08 18:05:51 +02:00
clairexen 7e2fc2eaeb
Merge pull request #2378 from udif/pr_dollar_high_low 
Added $high(), $low(), $left(), $right()
 2020-10-01 18:17:36 +02:00
clairexen 2412e75495
Merge pull request #2380 from Xiretza/parallel-tests 
Clean up and parallelize testsuite
 2020-10-01 18:12:31 +02:00
David Shah c4bfbecca6 Update .gitignore 
Signed-off-by: David Shah <dave@ds0.me>
 2020-10-01 15:53:14 +01:00
N. Engelhardt dc4a617694 add tests 2020-09-28 18:16:08 +02:00
Xiretza bed14241ef
tests: add gitignores for auto-generated makefiles 2020-09-26 16:28:24 +02:00
Eddie Hung de79978372
xilinx: do not make DSP48E1 a whitebox for ABC9 by default (#2325) 
* xilinx: eliminate SCCs from DSP48E1 model

* xilinx: add SCC test for DSP48E1

* Update techlibs/xilinx/cells_sim.v

* xilinx: Gate DSP48E1 being a whitebox behind ALLOW_WHITEBOX_DSP48E1

Have a test that checks it works through ABC9 when enabled
 2020-09-23 09:15:24 -07:00
N. Engelhardt 370243426e switch argument order to work with macOS getopt 2020-09-23 12:48:26 +02:00
Xiretza e38b830cbb
tests/simple: remove "nullglob" shopt 2020-09-21 15:07:02 +02:00
Xiretza 01260344d3
tests: Parallelize 2020-09-21 15:07:02 +02:00
Xiretza acd47bbd52
tests: Centralize test collection and Makefile generation 2020-09-21 15:07:02 +02:00
clairexen f176bd7778
Merge pull request #2329 from antmicro/arrays-fix-multirange-size 
Rewrite multirange arrays sizes [n] as [n-1:0]
 2020-09-17 18:27:05 +02:00
clairexen 9e937961dc
Merge pull request #2330 from antmicro/arrays-fix-multirange-access 
Fix unsupported subarray access detection
 2020-09-17 18:21:53 +02:00
Udi Finkelstein 7ed0e23e19 We can now handle array slices (e.g. $size(x[1]) etc. ) 2020-09-17 00:55:17 +03:00
Udi Finkelstein b548722bee Added $high(), $low(), $left(), $right() 2020-09-15 20:49:52 +03:00
Miodrag Milanović da3002e580
Merge pull request #2369 from Xiretza/gitignores 
Add missing gitignores for test artifacts
 2020-09-10 13:37:49 +02:00
clairexen a10893072b
Merge pull request #2352 from zachjs/const-func-localparam 
Allow localparams in constant functions
 2020-09-01 17:31:48 +02:00
clairexen 3e1840d036
Merge pull request #2353 from zachjs/top-scope 
Module name scope support
 2020-09-01 17:30:09 +02:00
clairexen 452442ac2f
Merge pull request #2365 from zachjs/const-arg-loop-split-type 
Fix constant args used with function ports split across declarations
 2020-09-01 17:28:35 +02:00
Xiretza 6224fd9055
Add missing gitignores for test artifacts 2020-08-31 19:43:51 +02:00
Zachary Snow ecc5c23b4d Fix constant args used with function ports split across declarations 2020-08-29 13:31:02 -04:00
whitequark 2d10d59d93
Merge pull request #2356 from whitequark/flatten-techmap-no-tpl_driven-sigmap 
flatten, techmap: don't canonicalize tpl driven bits via sigmap
 2020-08-27 11:28:31 +00:00
Dan Ravensloft 1a07b330f8 intel_alm: Add multiply signedness to cells 
Quartus assumes unsigned multiplication by default, breaking signed
multiplies, so add an input signedness parameter to the MISTRAL_MUL*
cells to propagate to Quartus' <family>_mac cells.
 2020-08-26 22:50:16 +02:00
whitequark 9f0892159e flatten, techmap: don't canonicalize tpl driven bits via sigmap. 
For connection `assign a = b;`, `sigmap(a)` returns `b`. This is
exactly the opposite of the desired canonicalization for driven bits.
Consider the following code:

    module foo(inout a, b);
      assign a = b;
    endmodule
    module bar(output c);
      foo f(c, 1'b0);
    endmodule

Before this commit, the inout ports would be swapped after flattening
(and cause a crash while attempting to drive a constant value).

This issue was introduced in 9f772eb9.

Fixes #2183.
 2020-08-26 16:29:42 +00:00
Zachary Snow 6127f22788 Module name scope support 2020-08-20 20:15:08 -04:00
Zachary Snow 74abc3bbfd Allow localparams in constant functions 2020-08-20 20:10:24 -04:00
clairexen d9dd8bc748
Merge pull request #2347 from YosysHQ/mwk/techmap-shift-fixes 
techmap/shift_shiftx: Remove the "shiftx2mux" special path.
 2020-08-20 16:25:56 +02:00
clairexen a96df40814
Merge pull request #2344 from YosysHQ/mwk/opt_share-fixes 
opt_share: Refactor, fix some bugs.
 2020-08-20 16:24:53 +02:00
clairexen 799076af24
Merge pull request #2333 from YosysHQ/mwk/peepopt-shiftmul-signed 
peeopt.shiftmul: Add a signedness check.
 2020-08-20 16:23:07 +02:00
clairexen 6a68b8ed54
Merge pull request #2328 from YosysHQ/mwk/opt_dff-cleanup 
Remove passes redundant with opt_dff
 2020-08-20 16:21:58 +02:00
clairexen faf8e19511
Merge pull request #2327 from YosysHQ/mwk/techmap-constmap-fix 
techmap.CONSTMAP: Handle outputs before inputs.
 2020-08-20 16:21:09 +02:00
clairexen 16bb3fc8bb
Merge pull request #2326 from YosysHQ/mwk/peeopt-muldiv-sign 
peepopt.muldiv: Add a signedness check.
 2020-08-20 16:19:37 +02:00
Marcelina Kościelnicka 50d532f01c techmap/shift_shiftx: Remove the "shiftx2mux" special path. 
Our techmap rules for $shift and $shiftx cells contained a special path
that aimed to decompose the shift LSB-first instead of MSB-first in
select cases that come up in pmux lowering.  This path was needlessly
overcomplicated and contained bugs.

Instead of doing that, just switch over the main path to iterate
LSB-first (except for the specially-handled MSB for signed shifts
and overflow handling).  This also makes the code consistent with
shl/shr/sshl/sshr cells, which are already decomposed LSB-first.

Fixes #2346.
 2020-08-20 12:44:09 +02:00
clairexen 87b9ee330d
Merge pull request #2122 from PeterCrozier/struct_array2 
Support 2D bit arrays in structures. Optimise array indexing.
 2020-08-19 17:58:37 +02:00
N. Engelhardt 850f66cfdd include both power-of-two and non-power-of-two testcases 2020-08-18 18:54:22 +02:00
clairexen 22765ef0a5
Merge pull request #2339 from zachjs/display-format-0s 
Allow %0s $display format specifier
 2020-08-18 17:39:01 +02:00
clairexen 4aa0dc4dc7
Merge pull request #2338 from zachjs/const-branch-finish 
Propagate const_fold through generate blocks and branches
 2020-08-18 17:38:07 +02:00
clairexen a9681f4e06
Merge pull request #2317 from zachjs/expand-genblock 
Fix generate scoping issues
 2020-08-18 17:37:11 +02:00
Claire Wolf 7f767bf2b7 Merge branch 'const-func-block-var' of https://github.com/zachjs/yosys into zachjs-const-func-block-var 
Signed-off-by: Claire Wolf <claire@symbioticeda.com>
 2020-08-18 17:29:49 +02:00
clairexen 5ee9349647
Merge pull request #2281 from zachjs/const-real 
Allow reals as constant function parameters
 2020-08-18 17:22:20 +02:00
Marcelina Kościelnicka 2b777bbda8 opt_share: Refactor, fix some bugs. 
Fixes #2334.
Fixes #2335.
Fixes #2336.
 2020-08-17 17:26:36 +02:00
Zachary Snow 2ee0b8ebea Propagate const_fold through generate blocks and branches 2020-08-09 17:21:08 -04:00
Zachary Snow 96ec9acf84 Allow %0s $display format specifier 2020-08-09 17:19:49 -04:00
Marcelina Kościelnicka 5693386a4e Remove now-redundant dff2dffs pass. 2020-08-07 13:21:34 +02:00
Marcelina Kościelnicka a0e99a9f3f peepopt: Remove now-redundant dffmux pattern. 2020-08-07 13:21:34 +02:00
Marcelina Kościelnicka 9a4f420b4b Replace opt_rmdff with opt_dff. 2020-08-07 13:21:03 +02:00
Marcelina Kościelnicka c1ed1c28be peeopt.shiftmul: Add a signedness check. 
Fixes #2332.
 2020-08-05 21:01:20 +02:00
Marcelina Kościelnicka b4a4cb081d techmap.CONSTMAP: Handle outputs before inputs. 
Fixes #2321.
 2020-08-05 12:28:18 +02:00
Marcelina Kościelnicka e89cc9c02f peepopt.muldiv: Add a signedness check. 
Fixes #2318.
 2020-08-04 16:30:24 +02:00
Lukasz Dalek daee2d967f Add test for subarray access on multidimensional arrays 
Signed-off-by: Lukasz Dalek <ldalek@antmicro.com>
 2020-08-03 17:07:33 +02:00
Lukasz Dalek 6e78f3a197 Test multirange (unpacked) arrays size 
Signed-off-by: Lukasz Dalek <ldalek@antmicro.com>
 2020-08-03 15:34:55 +02:00
Zachary Snow c3e95eb1ab Fix generate scoping issues 
- expand_genblock defers prefixing of items within named sub-blocks
- Allow partially-qualified references to local scopes
- Handle shadowing within generate blocks
- Resolve generate scope references within tasks and functions
- Apply generate scoping to genvars
- Resolves #2214, resolves #1456
 2020-07-31 20:32:47 -06:00
Marcelina Kościelnicka 18ad56ef41 Add dffunmap pass. 
To be used with backends that cannot deal with fancy FF types (like blif
or smt).
 2020-07-31 00:59:51 +02:00
Marcelina Kościelnicka 6cd135a5eb opt_expr: Remove -clkinv option, make it the default. 
Adds -noclkinv option just in case the old behavior was actually useful
to someone.
 2020-07-31 00:08:15 +02:00
Marcelina Kościelnicka cf60699884 synth_ice40: Use opt_dff. 
The main part is converting ice40_dsp to recognize the new FF types
created in opt_dff instead of trying to recognize the mux patterns on
its own.

The fsm call has been moved upwards because the passes cannot deal with
$dffe/$sdff*, and other optimizations don't help it much anyway.
 2020-07-30 22:26:20 +02:00
Marcelina Kościelnicka 8501342fc5 synth_xilinx: Use opt_dff. 
The main part is converting xilinx_dsp to recognize the new FF types
created in opt_dff instead of trying to recognize the patterns on its
own.

The fsm call has been moved upwards because the passes cannot deal with
$dffe/$sdff*, and other optimizations don't help it much anyway.
 2020-07-30 22:26:09 +02:00
Marcelina Kościelnicka af6623ebb8 Add opt_dff pass. 2020-07-30 18:27:04 +02:00
Marcelina Kościelnicka dc18bf1969 opt_expr: Fix handling of $_XNOR_ cells with A = B. 
Fixes #2311.
 2020-07-29 12:41:43 +02:00
clairexen 66afed6f55
Merge pull request #2306 from YosysHQ/mwk/equiv_induct-undef 
equiv_induct: Fix up assumption for $equiv cells in -undef mode.
 2020-07-28 12:56:22 +02:00
Marcelina Kościelnicka a1a0abf52a equiv_induct: Fix up assumption for $equiv cells in -undef mode. 
Before this fix, equiv_induct only assumed that one of the following is
true:

- defined value of A is equal to defined value of B
- A is undefined

This lets through valuations where A is defined, B is undefined, and
the defined (meaningless) value of B happens to match the defined value
of A.  Instead, tighten this up to OR of the following:

- defined value of A is equal to defined value of B, and B is not
  undefined
- A is undefined
 2020-07-27 18:36:13 +02:00
Dan Ravensloft a2fb84fd0c intel_alm: direct M10K instantiation 
This reverts commit a3a90f6377.
 2020-07-27 15:39:06 +02:00
Dan Ravensloft 62311b7ec0 intel_alm: increase abc9 -W 2020-07-26 23:56:54 +02:00
clairexen 9bcde4d82b
Merge pull request #2299 from zachjs/arg-loop 
Avoid generating wires for function args which are constant
 2020-07-26 21:34:55 +02:00
Zachary Snow f69daf4830 Allow blocks with declarations within constant functions 2020-07-25 10:16:12 -06:00
Zachary Snow 59c4ad8ed3 Avoid generating wires for function args which are constant 2020-07-24 21:18:24 -06:00
Marcelina Kościelnicka 1c8483b7dd zinit: Refactor to use FfInitVals. 2020-07-24 11:22:31 +02:00
Marcelina Kościelnicka abe4e9e607 clk2fflogic: Support all FF types. 2020-07-24 03:19:48 +02:00
Marcelina Kościelnicka 0c6d0d4b5d satgen: Add support for dffe, sdff, sdffe, sdffce cells. 2020-07-24 03:19:21 +02:00
clairexen c0ad522cf6
Merge pull request #2285 from YosysHQ/mwk/techmap-cellname 
techmap: Add _TECHMAP_CELLNAME_ special parameter.
 2020-07-23 18:39:42 +02:00
Dan Ravensloft 4d9d90079c intel_alm: add additional ABC9 timings 2020-07-23 11:57:07 +01:00
Marcelina Kościelnicka dc07ae9677 techmap: Add _TECHMAP_CELLNAME_ special parameter. 
This parameter will resolve to the name of the cell being mapped.  The
first user of this parameter will be synth_intel_alm's Quartus output,
which requires a unique (and preferably descriptive) name passed as
a cell parameter for the memory cells.
 2020-07-21 15:00:54 +02:00
Zachary Snow f285f7b769 Allow reals as constant function parameters 2020-07-19 20:27:09 -06:00
Miodrag Milanović 910f421324
Merge pull request #2238 from YosysHQ/mwk/dfflegalize-anlogic 
anlogic: Use dfflegalize.
 2020-07-16 18:07:58 +02:00
clairexen 021ce8e596
Merge pull request #2257 from antmicro/fix-conflicts 
Restore #2203 and #2244 and fix parser conflicts
 2020-07-15 11:49:09 +02:00
Marcelina Kościelnicka 3050454d6e anlogic: Use dfflegalize. 2020-07-14 05:02:50 +02:00
Lofty a3a90f6377 Revert "intel_alm: direct M10K instantiation" 
This reverts commit 09ecb9b2cf.
 2020-07-13 18:05:38 +02:00
Marcelina Kościelnicka 347dd01c2f xilinx: Fix srl regression. 
Of standard yosys cells, xilinx_srl only works on $_DFF_?_ and
$_DFFE_?P_, which get upgraded to $_SDFFE_?P?P_ by dfflegalize at the
point where xilinx_srl is called for non-abc9.  Fix this by running
ff_map.v first, resulting in FDRE cells, which are handled correctly.
 2020-07-12 23:41:27 +02:00
Kamil Rakoczy de649b9194 Revert "Revert PRs #2203 and #2244." 
This reverts commit 9c120b89ac.
 2020-07-10 09:59:48 +02:00
whitequark 9c120b89ac Revert PRs #2203 and #2244. 
This reverts commit 7e83a51fc9.
This reverts commit b422f2e4d0.
This reverts commit 7cb56f34b0.
This reverts commit 6f9be939bd.
This reverts commit 76a34dc5f3.
 2020-07-09 19:36:32 +00:00
Marcelina Kościelnicka 7ed9d18907 dfflibmap: Refactor to use dfflegalize internally. 2020-07-09 18:51:03 +02:00
Marcelina Kościelnicka 32d2cc8c28 clkbufmap: improve input pad handling. 
- allow inserting only the input pad cell
- do not insert the usual buffer if the input pad already acts as a
  buffer
 2020-07-09 18:48:01 +02:00
clairexen 802671b22e
Merge pull request #2244 from antmicro/logic 
Add logic type support to parameters
 2020-07-09 18:39:30 +02:00
Marcelina Kościelnicka 03e28f7ab4 clk2fflogic: Consistently treat async control signals as negative hold. 
This fixes some dfflegalize equivalence checks, and breaks others — and
I strongly suspect the others are due to bad support for multiple
async inputs in `proc` (in particular, lack of proper support for
dlatchsr and sketchy circuits on dffsr control inputs).
 2020-07-09 18:12:47 +02:00
Marcelina Kościelnicka e9c2c1b717 dfflegalize: Add special support for const-D latches. 
Those can be created by `opt_dff` when optimizing `$adff` with const
clock, or with D == Q.  Make dfflegalize do the opposite transform
when such dlatches would be otherwise unimplementable.
 2020-07-09 18:11:32 +02:00
Marcelina Kościelnicka c73ebeb90e gowin: Use dfflegalize. 2020-07-06 12:27:46 +02:00
Kamil Rakoczy b422f2e4d0 Add logic param and integer bad syntax tests 
Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
 2020-07-06 09:18:48 +02:00
Dan Ravensloft 09ecb9b2cf intel_alm: direct M10K instantiation 2020-07-05 23:28:59 +02:00
Dan Ravensloft 7f45cab27a synth_gowin: ABC9 support 
This adds ABC9 support for synth_gowin; drastically improving
synthesis quality.
 2020-07-05 22:07:17 +02:00
Dan Ravensloft 0d4c2f0a65 intel_alm: add Cyclone 10 GX tests 2020-07-05 21:36:38 +02:00
Marcelina Kościelnicka 7afcb72c98 opt_expr: Fix crash on $mul optimization with more zeros removed than Y has. 
Fixes #2221.
 2020-07-05 06:31:58 +02:00
Dan Ravensloft b004f09018 intel_alm: DSP inference 2020-07-05 05:39:20 +02:00
Marcelina Kościelnicka 3ca2de0f77 synth_intel_alm: Use dfflegalize. 2020-07-04 22:56:16 +02:00
Dan Ravensloft c6765443fd Improve MISTRAL_FF specify rules 
Co-authored-by: Eddie Hung <eddie@fpgeh.com>
 2020-07-04 19:45:10 +02:00
Eddie Hung 52fbaeca07 tests: update fsm.ys resource count 
Suspect it is to do with map/set ordering in techmap; should
be fixed by #1862?
 2020-07-04 19:45:10 +02:00
clairexen 5428666151
Merge pull request #2186 from YosysHQ/mwk/dfflegalize 
Add dfflegalize pass.
 2020-07-02 17:46:11 +02:00
clairexen 7450ee7f8a
Merge pull request #2203 from antmicro/fix-grammar 
Signed and macro grammar update
 2020-07-01 16:41:32 +02:00
clairexen 8ce4f8790e
Merge pull request #2179 from splhack/static-cast 
Support SystemVerilog Static Cast
 2020-07-01 16:40:20 +02:00
Marcelina Kościelnicka 6b42819a37 dfflegalize: Add tests. 2020-07-01 01:57:15 +02:00
Zachary Snow 27cec16cda Allow constant function calls in for loops and generate if and case 2020-06-29 16:06:17 -06:00
Kamil Rakoczy 76a34dc5f3 Add signed/unsigned tests 
Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
 2020-06-26 15:38:20 +02:00
Kamil Rakoczy 39c39848a2 Add sub-assign and and-assign tests 
Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
 2020-06-25 14:32:05 +02:00
Kamil Rakoczy 470df03f3d Move combined assign tests to single file 
Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
 2020-06-25 14:19:16 +02:00
Kamil Rakoczy f6d06c9f7b Add xor-assignment test 
Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
 2020-06-24 14:46:21 +02:00
Kamil Rakoczy a5ca4eeefb Add or-assignment and plus-assignment tests 
Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
 2020-06-24 11:56:26 +02:00
Marcelina Kościelnicka 88e7f90663 Update dff2dffe, dff2dffs, zinit to new FF types. 2020-06-23 18:24:53 +02:00
Kazuki Sakamoto 6bf75be73b static cast: add tests 2020-06-19 17:40:38 -07:00
whitequark 7191dd16f9 Use C++11 final/override keywords. 2020-06-18 23:34:52 +00:00
Dan Ravensloft 8b4eb78849 intel_alm: fix DFFE matching 2020-06-11 19:55:51 +02:00
diego d68a8f9e2b Removing trailing whitespace 2020-06-10 10:35:40 -05:00
Claire Wolf b3b515087d Fix tests/opt/opt_rmdff 
This only passed before because "prep" was also running opt_rmdff

Signed-off-by: Claire Wolf <claire@symbioticeda.com>
 2020-06-09 22:48:26 +02:00
diego 3c2a1171ff Adding latch tests for shift&mask AST dynamic part-select enhancements 2020-06-09 15:17:01 -05:00
Peter Crozier 01ec681373 Support 2D bit arrays in structures. Optimise array indexing. 2020-06-08 20:34:52 +01:00
Peter Crozier 76c499db71 Support packed arrays in struct/union. 2020-06-07 18:33:11 +01:00
Claire Wolf 7112f187cd Add missing .gitignore file 
Signed-off-by: Claire Wolf <claire@symbioticeda.com>
 2020-06-04 22:25:47 +02:00
clairexen 352731df4e
Merge pull request #2041 from PeterCrozier/struct 
Implementation of  SV structs.
 2020-06-04 18:26:07 +02:00
Eddie Hung 69850204c4
Merge pull request #2077 from YosysHQ/eddie/abc9_dff_improve 
abc9: -dff improvements
 2020-06-04 08:15:25 -07:00
Eddie Hung 45cd323055
Merge pull request #2082 from YosysHQ/eddie/abc9_scc_fixes 
abc9: fixes around handling combinatorial loops
 2020-06-03 17:35:46 -07:00
Peter Crozier 0d3f7ea011
Merge branch 'master' into struct 2020-06-03 17:19:28 +01:00
Eddie Hung 8a11019d38 tests: tidy up testcase 2020-06-03 08:41:55 -07:00
Eddie Hung 46ed0db2ec
Merge pull request #2080 from YosysHQ/eddie/fix_test_warnings 
tests: reduce test warnings
 2020-06-03 08:37:07 -07:00
Miodrag Milanovic 0a88f002e5 allow range for mux test 2020-06-01 13:48:19 +02:00
Eddie Hung ea4374a223 abc9_ops: update messaging (credit to @Xiretza for spotting) 2020-05-30 08:57:48 -07:00
Eddie Hung d3b53bc495 abc9_ops: -reintegrate use SigMap to remove (* init *) from $_DFF_[NP]_ 2020-05-29 17:17:40 -07:00
clairexen 0a14e1e837
Merge pull request #2029 from whitequark/fix-simplify-memory-sv_logic 
ast/simplify: don't bitblast async ROMs declared as `logic`
 2020-05-29 16:52:11 +02:00
Xiretza 6a2bac21d3
Expand tests/simple/constmuldivmod.v 2020-05-28 22:59:04 +02:00
whitequark abac0ab28e
Merge pull request #2091 from boqwxp/printattrs 
Add `printattrs` command to print attributes of currently selected objects.
 2020-05-28 10:25:34 +00:00
Alberto Gonzalez 6228b10c9f
printattrs: Add test. 2020-05-27 08:00:00 +00:00
Eddie Hung 1dce798dc5 tests: add ecp5 latch testcase with -abc9 2020-05-25 16:39:16 -07:00
Eddie Hung a7f2ef6d34
Merge pull request #2078 from YosysHQ/eddie/xilinx_sim_tidy 
xilinx: tidy up cells_sim.v a little
 2020-05-25 14:21:10 -07:00
Eddie Hung 08221edbc1 tests: xilinx macc test to have initval, shorten BMC depth for runtime 2020-05-25 10:09:05 -07:00
Eddie Hung 60aa804915 tests: fix some test warnings 2020-05-25 10:07:58 -07:00
Eddie Hung 9c6d216a06 tests: add test for abc9 -dff removing a redundant flop entirely 2020-05-25 08:43:33 -07:00
Eddie Hung 8dd93e389e tests: add testcase for abc9 -dff preserving flop names 2020-05-25 08:43:33 -07:00
Eddie Hung 95dcd7e785 test: add attribute-before-stmt test from @nakengelhardt 2020-05-25 07:36:53 -07:00
Eddie Hung 1c117ac023 verilog: do not warn for attributes on null statements 2020-05-25 07:36:53 -07:00