manarabdelaty
92f1ab7ace
[DATA] Update chip_io_alt.gds to match the mag view
2021-12-09 22:15:05 +02:00
manarabdelaty
2aa61e7bff
[DATA] Update gpio_control_block gds to match the mag view
...
- now has the substrate cut layer for isolating the two ground domains and passes LVS on the gds
2021-12-08 15:14:04 +02:00
manarabdelaty
db8cc0580b
[DATA] Update GDS views for the chip_io/chip_io_alt/mgmt_protect_hv/mgmt_protect to match the mag view
2021-12-07 14:28:29 +02:00
manarabdelaty
bd88221d17
[DATA] Update caravel_clocking
2021-12-07 13:36:56 +02:00
manarabdelaty
966b1f22bb
[DATA] Update digital_pll
2021-12-07 13:19:02 +02:00
manarabdelaty
aa766f9144
[DATA] Update caravel_clocking module
2021-12-05 19:44:28 +02:00
manarabdelaty
ef1019b62a
[DATA] Update caravel_clocking
2021-12-02 22:50:20 +02:00
manarabdelaty
85ad4b0e0f
Merge branch 'main' of https://github.com/efabless/caravel_openframe into main
2021-12-02 21:20:59 +02:00
manarabdelaty
0067bd5b7c
[DATA] Update caravel_clocking/digital_pll/housekeeping
2021-12-02 21:09:43 +02:00
jeffdi
5896df50a8
add files for seal ring
2021-12-01 22:35:39 -08:00
Jeff DiCorpo
de041996a6
Merge branch 'main' of https://github.com/efabless/caravel_openframe into main
2021-12-01 17:27:24 -08:00
Jeff DiCorpo
a2d5967b67
updating caravel.gds to final with mgmt core wrapper
2021-12-01 17:15:02 -08:00
jeffdi
0a09f3b5ac
added missing scripts
2021-12-01 11:03:45 -08:00
manarabdelaty
c4efcec989
[DATA] Update housekeeping views
2021-11-30 13:00:33 +02:00
manarabdelaty
8b1c5df909
[DATA] Update caravel_clocking module (timing clean)
2021-11-25 15:23:01 +02:00
manarabdelaty
05278ec738
[DATA] Update HK views (timing clean)
2021-11-25 12:54:22 +02:00
manarabdelaty
83e150bf25
[DATA] Add spare_logic_block
2021-11-24 20:36:23 +02:00
manarabdelaty
aeffe4756a
[DATA] Add caravan layout
2021-11-22 23:10:25 +02:00
manarabdelaty
38f64d08a3
[DATA] Add user_analog_project_wrapper and chip_io_alt gds/lef views
2021-11-22 23:08:25 +02:00
manarabdelaty
1c18c1dae9
[DATA] Update caravel
2021-11-20 17:28:59 +02:00
manarabdelaty
331fdee2bb
[DATA] Update HK module (li1 routing: 249um)
2021-11-20 15:13:16 +02:00
manarabdelaty
5cd3843f00
[DATA] Update gpio_control_block (li1 used 2um)
2021-11-20 14:43:20 +02:00
manarabdelaty
37fb2d6766
[DATA] update caravel_clocking module (removed long li1 routes, in total it used 8um from li1)
2021-11-20 13:07:23 +02:00
manarabdelaty
ededa9ed35
[DATA] Update caravel layout with the latest views for the mgmt_protect and mgmt_core
2021-11-19 16:51:28 +02:00
manarabdelaty
866755f228
[DATA] Update mgmt_protect mag/gds to remove the shorted power nets
2021-11-19 15:50:36 +02:00
manarabdelaty
bf6ad67934
[DATA] Update gpio_control_block pin order to fix shorts at the top level
2021-11-19 13:13:24 +02:00
manarabdelaty
581a22de6a
[DATA] Update mgmt_protect (removed all li1 routing )
2021-11-19 13:11:18 +02:00
manarabdelaty
2574eada93
[DATA] Add initial caravel layout
2021-11-19 01:37:10 +02:00
manarabdelaty
61bf3c651e
[DATA] Update mgmt_protect pin placement
2021-11-19 01:33:11 +02:00
manarabdelaty
53b3a9013e
[DATA] Update HK pin placement
2021-11-19 01:30:14 +02:00
manarabdelaty
37a07e291b
[DATA] Update digital_pll pin placement to have it align with the HK
2021-11-19 01:28:40 +02:00
manarabdelaty
1f55f46596
[DATA] Add chip_io views with the fixed clamped3 pad
2021-11-17 16:42:36 +02:00
manarabdelaty
1b300d7b59
[DATA] Add digital user project wrapper
2021-11-17 13:13:11 +02:00
manarabdelaty
098b4befb2
Add gds view for chip_io
2021-11-15 23:02:01 +02:00
manarabdelaty
46540437af
[DATA] Add gds/lef/maglef/gl views for the user_id_programming block
2021-11-15 18:17:32 +02:00
manarabdelaty
10cf11fbf5
Add gds/lef views for simple_por
2021-11-15 18:08:22 +02:00
manarabdelaty
6203460f57
[DATA] Add views for xres_buf
2021-11-15 18:07:02 +02:00
manarabdelaty
72b2c724c9
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 15:50:43 +02:00
manarabdelaty
56f672bbd8
[DATA] Add HK views
2021-11-15 13:23:54 +02:00
manarabdelaty
89bb33fbc0
Merge branch 'main' of https://github.com/efabless/caravel_openframe into main
2021-11-08 13:35:16 +02:00
manarabdelaty
bee7b4ed78
Add initial config for the digital_pll
2021-11-08 13:34:59 +02:00
Tim Edwards
f53590d4b5
Split the layout of the GPIO defaults block into three versions, for the
...
three parameterized values used in the RTL verilog. Modified the
"user_defines.v" file to create verilog definitions that match the C-style
definitions from "defs.h", for convenience/simplicity.
2021-11-06 13:28:26 -04:00
Tim Edwards
33140b67a5
Edited the gpio_defaults_block layout like the user_id_programming
...
cell to have landing sites for vias on both the HI and LO pins of
each conb_1 cell, in preparation for via programming.
2021-11-06 12:59:49 -04:00
manarabdelaty
59076d499a
Update gpio_defaults_block to align the pins with the gpio_control_block
2021-11-05 23:27:32 +02:00
manarabdelaty
49c506f052
Update gpio_control_block after constrainting the clock period to be half the mgmt_core frequency
2021-11-05 18:36:43 +02:00
manarabdelaty
e68664101c
Update gpio_control_block
2021-11-05 16:54:55 +02:00
manarabdelaty
53b09f43d1
Add gpio_defaults_block views
2021-11-05 12:33:36 +02:00
manarabdelaty
78ce7265c1
Update gpio_control block
2021-11-04 17:58:58 +02:00
manarabdelaty
cb9990f97e
harden gpio_control_block
2021-11-04 16:19:12 +02:00
Tim Edwards
a67cbcb01c
Added back a couple more files related to the user ID programming block.
2021-10-26 10:40:55 -04:00