Commit Graph

154 Commits

Author SHA1 Message Date
R. Timothy Edwards d9260dc533
Fixes to caravan for LVS and ERC (#330)
* Corrected missing part of porb_h route in the caravan chip_io_alt
layout.  Correcting the indexing of the "mprj_io_one" connections
to "mgmt_io_oeb" on the left-hand side of caravan, as they were
connecting back to the right side and making a mess of wiring,
instead of being wired locally directly to the nearest I/O.

* Apply automatic changes to Manifest and README.rst

* Corrected the unconnected mgmt_io_in inputs to housekeeping on
the caravan chip (which correspond to the GPIOs that do not exist
in caravan) by connecting them to the "zero" outputs of the
closest GPIO control blocks.

* Apply automatic changes to Manifest and README.rst

Co-authored-by: RTimothyEdwards <RTimothyEdwards@users.noreply.github.com>
2022-10-21 14:28:53 -07:00
R. Timothy Edwards 5029d71df6
Syntax changes that are non-functional from a synthesis perspective. (#324)
* Syntax changes that are non-functional from a synthesis perspective.
There are a few errors that are caught by commercial tools and halt
synthesis, which are handled more gracefully by the open source
tool flow.  In housekeeping.v:  Some wires declared after they are
used.  In housekeeping_spi.v:  A non-blocking "=" assignment used
where a blocking "<-" assignment was intended.

* Apply automatic changes to Manifest and README.rst

Co-authored-by: RTimothyEdwards <RTimothyEdwards@users.noreply.github.com>
2022-10-21 10:10:20 -07:00
M0stafaRady 096f5035f5
cocotb - updates related to enable simulating caraval using iverilog (#320)
* cocotb - updates related to enable simulating caraval using iverilog

* Apply automatic changes to Manifest and README.rst

Co-authored-by: M0stafaRady <M0stafaRady@users.noreply.github.com>
2022-10-21 07:43:34 -07:00
Jeff DiCorpo 4192c34f4b
Caravan redesign (#321)
* Fixed caravan top level power routing and updated views for mag, gds and lef

* caravan(rtl): updates

~ typos fix
- remove unused pin in chip_io_alt
+ add caravan_power_routing verilog

* Apply automatic changes to Manifest and README.rst

* ~ update caravan openlane configs to add extra cell references
~ correct placment and cell names of some macro in caravan interactive script

* reharden: caravan

+ add non functional blocks
+ add an initial iteration of caravan

* Apply automatic changes to Manifest and README.rst

* Revert "Fixed caravan top level power routing and updated views for mag, gds and lef"

This reverts commit 70628f748a.

* fixed caravan top level power routing

* reharden: caravan

based on new power routing
~ guard rtl chip_io power pins in the power macro guard

* Apply automatic changes to Manifest and README.rst

* fixed caravan top level power routing

* rehadren: caravan

+ add caravan signal routing to openlane run
~ change rtl to guard power and analog against routing by
openlane by ifndef TOP_ROUTING
~ add pr bounadry for caravan signal routing to fix origin issues

* Apply automatic changes to Manifest and README.rst

* fix power connection in buffering block and regenerate gl

* Apply automatic changes to Manifest and README.rst

* updated views for caravan

* Added extract unique to lvs-gds-cell target. (#313)

* This fixes errors in the top level RTL of caravan that failed to
hook up the buffers through the SoC correctly.

* Apply automatic changes to Manifest and README.rst

* reharden: caravan

~ rtl updated

* fixed caravan mag top level

* updated views for caravan + signoff

* fixed top level cell name

* fix syntax error related to signal initialization place in caravan (#319)

* fix syntax error related to signal initialization place in caravan- fixed in caravel in another commit

* Apply automatic changes to Manifest and README.rst

Co-authored-by: M0stafaRady <M0stafaRady@users.noreply.github.com>

* Apply automatic changes to Manifest and README.rst

Co-authored-by: Marwan Abbas <marwaneltoukhy@aucegypt.edu>
Co-authored-by: kareem <kareem.farid@efabless.com>
Co-authored-by: kareefardi <kareefardi@users.noreply.github.com>
Co-authored-by: Mitch Bailey <d-m-bailey@users.noreply.github.com>
Co-authored-by: Tim Edwards <tim@opencircuitdesign.com>
Co-authored-by: RTimothyEdwards <RTimothyEdwards@users.noreply.github.com>
Co-authored-by: Marwan Abbas <67271180+marwaneltoukhy@users.noreply.github.com>
Co-authored-by: M0stafaRady <107422726+M0stafaRady@users.noreply.github.com>
Co-authored-by: M0stafaRady <M0stafaRady@users.noreply.github.com>
Co-authored-by: jeffdi <jeffdi@users.noreply.github.com>
2022-10-21 07:37:41 -07:00
M0stafaRady 98d089ed08 Move decleration of some signal in caravel.v to fix error in iverilog 2022-10-20 06:26:55 -07:00
Mohamed Shalan 3fbc52ecbf
Merge pull request #276 from efabless/caravel_redesign-digital_pll-fanout
reharden!: digital_pll
2022-10-17 20:50:01 +02:00
mo-hosni 2d147966b9 Update housekeeping views and openlane configuration 2022-10-17 11:37:24 -07:00
kareem e5d9788a43 reharden!: digital_pll
~ enable synth buffering to fix fanout
~ add *buf_1* to no synth list
~ add attribute (* keep *) to the oscillator as dont
touch for yosys

!need to verify that the oscillator remains untouched
2022-10-17 10:56:01 -07:00
Passant 9c3fea9a4d update caravel top-level rtl to not buffer `porb_h` through the `mgmt_core_wrapper` 2022-10-17 10:46:31 -07:00
kareem a8794dff4b reharden: caravel
~ reharden with updated pdn
~ add stubs for non functional blocks
2022-10-17 03:59:28 -07:00
marwaneltoukhy 2d28c973ee added views for caravel with power routing 2022-10-16 19:08:56 -07:00
marwaneltoukhy 7ec1eeb010 Merge branch 'caravel_redesign' into caravel_redesign-top-level 2022-10-16 18:39:39 -07:00
Tim Edwards 69d353f65c Corrected the verilog and the layout for the caravan version of the
signal buffering (verilog was missing one of the buffers, and the
layout had some of the labels at the top accidentally erased).
2022-10-16 21:06:27 -04:00
Marwan Abbas 37d2a9d463 connected rest of buffers to power 2022-10-17 01:15:46 +02:00
kareem 2409207178 reharden: caravel
~ add non functional blocks - like caravel_motto
2022-10-16 15:44:27 -07:00
Tim Edwards c5e7c67d60 Once again. . . Rewrote the RTL verilog so that only signals
being buffered pass through the buffer macros.  Removed the
straight-through signals from the layout, and renumbered the
vectors in the buffer cells, which no longer match the numbering
at the top level (unfortunately).
2022-10-16 12:49:44 -04:00
kareem 5d5d019ea1 Revert "add buff_flash_clkrst"
This reverts commit 2675487322.
2022-10-15 08:47:02 -07:00
mo-hosni 2675487322 add buff_flash_clkrst 2022-10-15 06:38:42 -07:00
Marwan Abbas 696eddcc7b
Merge branch 'caravel_redesign' into buff_power_connection 2022-10-15 13:34:21 +02:00
Marwan Abbas 40c7776b57 added power connection to buffer rtl 2022-10-15 12:56:40 +02:00
Marwan Abbas d025944505
Merge branch 'caravel_redesign' into buff_power_connection 2022-10-15 11:48:51 +02:00
Marwan Abbas 6c19140590 added power connection to buffer top level rtl 2022-10-15 11:27:30 +02:00
passant5 8c0e4f7403
Merge branch 'caravel_redesign' into add_top_level_buffers 2022-10-15 00:28:14 +02:00
Passant 653e7fa561 update top-level rtl to resolve conflict with adding top level buffers between housekeeping and `gpio_control_block` https://github.com/efabless/caravel/pull/213 2022-10-14 15:02:16 -07:00
Passant f499b8b75f update top-level rtl with 7 pass through signals to be buffered inside the SoC 2022-10-14 13:11:42 -07:00
Tim Edwards ac209d2397 Corrected a bunch of typos (different signal names used in the
same file), errors (buffer output pin name, power supplies not
passed at the top level).  Corrected a major error that prevented
the use of the buffers in simulation, so this was not previously
verified by simulation.  The buffering has now been properly
verified.
2022-10-14 10:51:29 -04:00
Marwan Abbas b8651328f9
Merge branch 'caravel_redesign' into cocotb 2022-10-13 21:14:42 +02:00
Passant c3a2c8650e update caravel top-level rtl to add `buff_flash_clkrst` module 2022-10-13 12:11:22 -07:00
Marwan Abbas f7299933ee
Merge pull request #217 from mo-hosni/buff_flash_clkrst
Buff flash clkrst
2022-10-13 20:53:18 +02:00
kareem d5379ab6f9 fix power pins assignment of clockp buffers again 2022-10-13 11:02:35 -07:00
kareem fdf1f11ece fix power pins assignment of clockp buffers 2022-10-13 11:00:04 -07:00
mo-hosni 889aa7e308 add buff_flash_clkrst 2022-10-13 10:35:51 -07:00
Tim Edwards f7ec0cd012 Added buffers to the top level, inside a macro called
gpio_signal_buffering (gpio_signal_buffering_alt in caravan).
Note that this macro requires manual placement and routing, like
the padframe, and the top level will need to route around its own
internal routes.
2022-10-13 13:29:27 -04:00
kareem 59743f4832 change buf16 to clkbuf16 and reimplement 2022-10-13 06:54:55 -07:00
kareem bb2d983e03 + add a size 16 buf for clockp signal in digital_pll 2022-10-13 05:57:09 -07:00
M0stafaRady 327900b526 fix bug of wrapper ack 2022-10-11 06:02:44 -07:00
M0stafaRady 150d83fe48 Merge branch 'caravel_redesign' into cocotb 2022-10-11 03:56:05 -07:00
Mohamed Shalan 11530f691e
Merge pull request #165 from efabless/misc-rtl-changes
some rtl changes
2022-10-11 10:48:18 +02:00
Mohamed Shalan fe3d2b927f
Merge pull request #139 from efabless/cocotb
new environment for simulation automation with cocotb and vcs
2022-10-11 10:41:22 +02:00
Mohamed Shalan 344f806980
Merge pull request #166 from efabless/gpio_control_block-sparecell
gpio_control_block sparecell
2022-10-11 10:39:50 +02:00
Mohamed Shalan db9362d858
Merge branch 'caravel_redesign' into misc-rtl-changes 2022-10-11 10:39:32 +02:00
M0stafaRady 7fe790649d Add gpio_all_bidir_user test 2022-10-10 15:59:20 -07:00
M0stafaRady 01a9fd928f
Fix typo at mprj_io (#168)
* Fix typo at mprj_io

* Apply automatic changes to Manifest and README.rst

Co-authored-by: M0stafaRady <M0stafaRady@users.noreply.github.com>
2022-10-10 12:11:05 -07:00
kareem 3a81dde555 add sky130_fd_sc_hd__macro_sparecell inside gpio_control_block rtl 2022-10-10 05:24:25 -07:00
kareem 71e309a923 some rtl changes
- remove unused port in chip_io
- move the rest of chip_io power ports to the USE_POWER_PINS guard
- add caravel_power_routing cell guarded by TOP_ROUTING ifdef
2022-10-10 05:13:48 -07:00
M0stafaRady 0f0a495906 merge with caravel_redesign 2022-10-10 05:04:44 -07:00
kareem 285ef6b642 reharden!: caravel
~ update the following views:
def
mag
verilog
spef(all corners)
+ add the ability to override the interactive script filename
+ add the ability to run openlane regression using regression.config
file
~ change GRT ADJUSTMENT values
~ change pointers to some files for workarounds

!important the interactive script still needs updates
!important this was done using old openlane v0.22 and its matching
pdk
!important known workarounds:
- a custom techlef is used where large metal spacing rules are the
only ones present to avoid violations by the router
- some odd behaviour happening when a macro has a lef view
with a non zero origin. so the power routing cell is (temporarily)
modified to have a zero origin and its placement has been shifted
which doesn't match the power routing mag.
- the old openlane doesn't generate multi spef corners. they
are generated using timing-scripts repo
2022-10-10 04:51:05 -07:00
M0stafaRady 00364eb092 Add gpio_all_o_user test 2022-10-09 07:53:25 -07:00
Tim Edwards d1a3922dbb Initial commit for rework of chip_io and chip_io_alt layouts;
includes RTL change inside the padframe definition to remove one
previously unnoticed hard-wired connection between VDDIO and a
3.3V domain digital input pin.
2022-10-08 12:05:10 -04:00
M0stafaRady e94a8e0477 add test la test 2022-10-08 06:25:26 -07:00