tangxifan
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e78b234e00
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[Testbench] Bug fix for wrapper testbench include netlist
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2020-12-14 13:30:01 -07:00 |
tangxifan
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68c1e17a96
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[Testbench] Add more testbenches for CHD post-pnr verification
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2020-12-14 13:26:04 -07:00 |
tangxifan
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7c0dc4c871
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[Testbench] Restore post-Pnr testbenches for CHD version
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2020-12-14 13:17:37 -07:00 |
tangxifan
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62924d5464
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[Git] Bug fix in lfs file tracking
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2020-12-14 13:11:20 -07:00 |
Ganesh Gore
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3c174619b0
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[Action] Updated action script for local run
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2020-12-14 12:08:16 -07:00 |
tangxifan
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230b945e2d
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Merge pull request #68 from lnis-uofu/xt_dev
Update sphinx bibtex version requirement to avoid icompatible versions
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2020-12-14 11:26:13 -07:00 |
tangxifan
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d6dc543870
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Merge pull request #67 from lnis-uofu/ganesh_dev
Updated CHD design with mux_primitive fix
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2020-12-14 11:10:04 -07:00 |
tangxifan
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61ab543e2a
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[Doc] Update sphinx bibtex version requirement to avoid imcompatible versions
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2020-12-14 10:57:59 -07:00 |
Ganesh Gore
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13fc082cb3
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[SOFA_HD] Updated verification script
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2020-12-14 01:16:30 -07:00 |
Ganesh Gore
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5c12369380
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[SOFA_HD] Updated netlist + Caravel precheck passed
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2020-12-14 01:16:00 -07:00 |
Ganesh Gore
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967905e046
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[SOFA_HD] Updated netlist and task
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2020-12-14 01:14:14 -07:00 |
Ganesh Gore
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fa87753d62
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[Cleanup] Renamed projects to SOFA-HD and QLSOFA-HD
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2020-12-14 00:45:11 -07:00 |
Ganesh Gore
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9f9897c5e2
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[SOFA-CHD] Updated design with mux-primitive bug fixed - Calibre DRC pending
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2020-12-14 00:34:42 -07:00 |
Ganesh Gore
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0672f01e3a
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[Cleanup] Removed unused SDCs
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2020-12-14 00:31:03 -07:00 |
tangxifan
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8def618a52
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Merge pull request #66 from lnis-uofu/xt_dev
FPGA I/O cell Update
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2020-12-11 18:08:18 -07:00 |
tangxifan
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b38a948a56
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[Doc] Add testing waveform example to documentation
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2020-12-11 17:24:28 -07:00 |
tangxifan
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63bc60ccdd
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[Git] Relax the LFS application to get rid of small files
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2020-12-11 16:25:23 -07:00 |
tangxifan
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1e490c1714
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[HDL] Add digital I/O self testing testbench
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2020-12-11 16:11:12 -07:00 |
tangxifan
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52d98eb7ca
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[HDL] Revert I/O cell back to the current design in GDS
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2020-12-11 11:26:46 -07:00 |
tangxifan
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88f522026a
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[Doc] Update I/O schematic to be consistent with HDL netlist
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2020-12-11 11:25:28 -07:00 |
tangxifan
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9dc1b6efa7
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[Doc] Fine tune documentation on I/O design
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2020-12-11 11:25:07 -07:00 |
tangxifan
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c1cdca61b5
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[HDL] Critical Patch on the digital I/O cell which now outputs 'Z' when input mode is selected
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2020-12-11 10:59:28 -07:00 |
tangxifan
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00b1740b44
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Merge pull request #65 from lnis-uofu/xt_dev
Bug fix in the custom cell code generator
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2020-12-11 10:12:53 -07:00 |
tangxifan
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9c80a1b1a7
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[HDL] Bug fix in the custom cell code generator
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2020-12-10 15:45:20 -07:00 |
tangxifan
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3ccb0e2931
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Merge pull request #64 from lnis-uofu/xt_dev
Release of Testbenches for SOFA CHD version and Documentation Update
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2020-12-09 20:55:06 -07:00 |
tangxifan
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b1a606443f
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[Doc] Add motiviation figure and reworked introduction part
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2020-12-09 20:12:09 -07:00 |
tangxifan
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abd51929f9
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[Doc] Add MUX design information to documentation
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2020-12-09 17:51:15 -07:00 |
tangxifan
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9f82ac7636
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[Doc] Add SOFA CHD to documentation. Clean up redundant document between HD FPGA IPs
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2020-12-09 16:18:04 -07:00 |
tangxifan
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d9e965cf3b
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[Testbench] Add post-PnR testbenches for SOFA-CHD
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2020-12-09 14:55:27 -07:00 |
tangxifan
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5a567644db
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Merge pull request #63 from lnis-uofu/xt_dev
Fine-tune architecture file to be consistent in port naming of SOFA CHD
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2020-12-09 14:05:20 -07:00 |
tangxifan
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e7fd8e7d92
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[Arch] Fine-tune architecture file to be consistent in port naming as post-PnR netlist
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2020-12-09 12:12:40 -07:00 |
tangxifan
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73622b1df5
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[TESTBENCH] Add more cells that are used by post-PNR CHD FPGA
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2020-12-09 12:12:14 -07:00 |
tangxifan
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0c761ebc05
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Merge pull request #61 from lnis-uofu/ganesh_dev
SOFA CHD Post-PnR Netlist
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2020-12-09 10:41:29 -07:00 |
tangxifan
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0180a5146f
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Merge pull request #62 from lnis-uofu/xt_dev
Bug fix on the CI dependency for OpenFPGA-run in Github Actions
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2020-12-09 09:53:45 -07:00 |
Ganesh Gore
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d9b945ab6f
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[Actions] Temporarily disable deployment
+ Magic DRC check fails on CI machine
+ Not enough RAM
+ Will perform test locally and upload
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2020-12-09 01:04:26 -07:00 |
Ganesh Gore
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77bb6d4eae
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[SOFA_CHD] Added Verification results
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2020-12-09 00:55:27 -07:00 |
Ganesh Gore
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45ff6d2dfe
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[SOFA_CHD] Added post-pnr netlist, Verified CCFF/SCFF
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2020-12-09 00:54:03 -07:00 |
Ganesh Gore
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1a2e6de718
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[SOFA_CHD] Removed large testbench file
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2020-12-09 00:51:30 -07:00 |
Ganesh Gore
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9284bbf8fa
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[SOFA_CHD] Added OpenFPGA taks and verilog netlist
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2020-12-09 00:49:00 -07:00 |
Ganesh Gore
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def270a94b
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[Actions] Launched checker in correct directory
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2020-12-08 21:50:18 -07:00 |
tangxifan
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3c9017b2f8
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[CI] Bug fix
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2020-12-08 16:41:22 -07:00 |
tangxifan
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80937ca769
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[CI] Update dependency to sync with OpenFPGA
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2020-12-08 16:36:02 -07:00 |
tangxifan
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ed92cba451
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[HDL] Add netlist for simulation with Caravel + FPGA
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2020-12-08 15:35:38 -07:00 |
Ganesh Gore
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3ecd96596f
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[Actions] Merged Caravel with Klayout
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2020-12-08 13:33:17 -07:00 |
Laboratory for Nano Integrated Systems (LNIS)
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06ea86c0b0
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Merge pull request #60 from lnis-uofu/xt_dev
Scripts to Automate the Synthesis for the decoders in FPGAs with custom cells
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2020-12-08 13:30:40 -07:00 |
Ganesh Gore
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2f2b301395
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[Action] Updated repo destination
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2020-12-08 11:31:04 -07:00 |
Ganesh Gore
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9efe8a7935
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[Actions] Added correct repository
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2020-12-08 10:24:54 -07:00 |
tangxifan
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3cc54ccb59
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[MSIM] Bug fix
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2020-12-08 10:15:39 -07:00 |
tangxifan
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4247819ccb
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Merge branch 'xt_dev' of https://github.com/LNIS-Projects/skywater-openfpga into xt_dev
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2020-12-08 10:13:33 -07:00 |
tangxifan
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55ff90905f
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[DC] Add scripts to automate the synthesis for local encoders
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2020-12-08 10:12:57 -07:00 |