Default Branch

abea1a8aa0 · Changed fpga_top to fpga_core · Updated 2023-03-17 11:23:05 -05:00

Branches

cd4e58f9ff · pdsemi progress · Updated 2021-08-26 10:08:26 -05:00

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fd56949ead · Merge pull request #120 from lnis-uofu/ganesh_dev · Updated 2021-04-06 23:41:14 -05:00

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fd56949ead · Merge pull request #120 from lnis-uofu/ganesh_dev · Updated 2021-04-06 23:41:14 -05:00

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b469faa967 · Merge branch 'master' into tangxifan-patch-2 · Updated 2021-04-05 21:30:42 -05:00

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17c2046d17 · Figure and hyperlink updates for Custom Cells Documentation · Updated 2021-04-05 18:50:06 -05:00

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0d909efcf9 · Changing yosys custom script to run in adder mode and also changing power_analysis to false to avoid ace2 run · Updated 2021-02-15 05:07:41 -06:00

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b4e3440972 · Fix parsing error in FPGA1212_QLSOFA arch file. · Updated 2021-02-05 11:36:29 -06:00

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9318f0e49e · Merge remote-tracking branch 'origin' into ql_ccff_dummy_stdcell_pointer · Updated 2021-02-03 22:25:50 -06:00

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d757605989 · more updates to clock buffer representation · Updated 2021-02-02 11:52:18 -06:00

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78e2a242b3 · Merge remote-tracking branch 'origin/master' into ganesh_dev · Updated 2021-01-25 12:04:28 -06:00

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f1eb4c4f88 · rename module name to IO from EMBEDDED_IO_HD · Updated 2021-01-21 22:52:16 -06:00

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3f5409eee2 · add 4 global clocks · Updated 2021-01-14 04:28:07 -06:00

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1a4b1bc6b4 · Disable generation of formal verification testbench due to disk space · Updated 2021-01-05 21:44:08 -06:00

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054c3d5f28 · Updating conf file to run custom yosys script on a benchmark design · Updated 2020-12-23 02:54:56 -06:00

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44a68c888d · remove dedicated VCC/GND tiles and pb_type · Updated 2020-12-08 13:17:31 -06:00

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