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Updating conf file to run custom yosys script on a benchmark design

This commit is contained in:
Lalit Sharma 2020-12-23 00:54:56 -08:00
parent 01fabc65cc
commit 054c3d5f28
2 changed files with 9 additions and 2 deletions
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5
SCRIPT/skywater_openfpga_task/k4_N8_reset_softadder_caravel_cc_fdhd_32x32/generate_fabric/config/task_template.conf
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@ -29,10 +29,11 @@ external_fabric_key_file=${SKYWATER_OPENFPGA_HOME}/ARCH/fabric_key/fabric_key_12
arch0=${SKYWATER_OPENFPGA_HOME}/ARCH/vpr_arch/k4_N8_tileable_reset_softadder_register_scan_chain_nonLR_caravel_io_skywater130nm.xml
[BENCHMARKS]
bench0=${SKYWATER_OPENFPGA_HOME}/BENCHMARK/and2/and2.v
bench0=${SKYWATER_OPENFPGA_HOME}/BENCHMARK/Simon_bit_serial_top_module/rtl/*.v
[SYNTHESIS_PARAM]
bench0_top = and2
bench0_top = Simon_bit_serial_top
bench0_yosys=${SKYWATER_OPENFPGA_HOME}/SCRIPT/skywater_openfpga_task/k4_N8_reset_softadder_caravel_cc_fdhd_32x32/quicklogic_yosys_flow_ap3.ys
[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
#end_flow_with_test=

6
SCRIPT/skywater_openfpga_task/k4_N8_reset_softadder_caravel_cc_fdhd_32x32/quicklogic_yosys_flow_ap3.ys Normal file
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@ -0,0 +1,6 @@
# Yosys synthesis script for ${TOP_MODULE}
# Read verilog files
${READ_VERILOG_FILE}
synth_quicklogic -blif ${OUTPUT_BLIF} -family ap3 -vpr -openfpga -top ${TOP_MODULE}