From 054c3d5f28b6b9f9a27b36c1f242b76d41c7a114 Mon Sep 17 00:00:00 2001
From: Lalit Sharma <lsharma@quicklogic.com>
Date: Wed, 23 Dec 2020 00:54:56 -0800
Subject: [PATCH] Updating conf file to run custom yosys script on a benchmark
 design

---
 .../generate_fabric/config/task_template.conf               | 5 +++--
 .../quicklogic_yosys_flow_ap3.ys                            | 6 ++++++
 2 files changed, 9 insertions(+), 2 deletions(-)
 create mode 100644 SCRIPT/skywater_openfpga_task/k4_N8_reset_softadder_caravel_cc_fdhd_32x32/quicklogic_yosys_flow_ap3.ys

diff --git a/SCRIPT/skywater_openfpga_task/k4_N8_reset_softadder_caravel_cc_fdhd_32x32/generate_fabric/config/task_template.conf b/SCRIPT/skywater_openfpga_task/k4_N8_reset_softadder_caravel_cc_fdhd_32x32/generate_fabric/config/task_template.conf
index b9f99be..42c880d 100644
--- a/SCRIPT/skywater_openfpga_task/k4_N8_reset_softadder_caravel_cc_fdhd_32x32/generate_fabric/config/task_template.conf
+++ b/SCRIPT/skywater_openfpga_task/k4_N8_reset_softadder_caravel_cc_fdhd_32x32/generate_fabric/config/task_template.conf
@@ -29,10 +29,11 @@ external_fabric_key_file=${SKYWATER_OPENFPGA_HOME}/ARCH/fabric_key/fabric_key_12
 arch0=${SKYWATER_OPENFPGA_HOME}/ARCH/vpr_arch/k4_N8_tileable_reset_softadder_register_scan_chain_nonLR_caravel_io_skywater130nm.xml
 
 [BENCHMARKS]
-bench0=${SKYWATER_OPENFPGA_HOME}/BENCHMARK/and2/and2.v
+bench0=${SKYWATER_OPENFPGA_HOME}/BENCHMARK/Simon_bit_serial_top_module/rtl/*.v
 
 [SYNTHESIS_PARAM]
-bench0_top = and2
+bench0_top = Simon_bit_serial_top
+bench0_yosys=${SKYWATER_OPENFPGA_HOME}/SCRIPT/skywater_openfpga_task/k4_N8_reset_softadder_caravel_cc_fdhd_32x32/quicklogic_yosys_flow_ap3.ys
 
 [SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
 #end_flow_with_test=
diff --git a/SCRIPT/skywater_openfpga_task/k4_N8_reset_softadder_caravel_cc_fdhd_32x32/quicklogic_yosys_flow_ap3.ys b/SCRIPT/skywater_openfpga_task/k4_N8_reset_softadder_caravel_cc_fdhd_32x32/quicklogic_yosys_flow_ap3.ys
new file mode 100644
index 0000000..314a323
--- /dev/null
+++ b/SCRIPT/skywater_openfpga_task/k4_N8_reset_softadder_caravel_cc_fdhd_32x32/quicklogic_yosys_flow_ap3.ys
@@ -0,0 +1,6 @@
+# Yosys synthesis script for ${TOP_MODULE}
+# Read verilog files
+${READ_VERILOG_FILE}
+
+synth_quicklogic -blif ${OUTPUT_BLIF} -family ap3 -vpr -openfpga -top ${TOP_MODULE}
+