mirror of https://github.com/lnis-uofu/SOFA.git
added a new architecture with LUT4, Soft adder and cross local routing with 24 clb inputs and feedback
This commit is contained in:
Tarachand Pagarani
parent
8d5036f108
commit
01fabc65cc
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<!-- Architecture annotation for OpenFPGA framework
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This annotation supports the k4_frac_cc_sky130nm.xml
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- General purpose logic block
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- K = 6, N = 10, I = 40
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- Single mode
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- Routing architecture
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- L = 4, fc_in = 0.15, fc_out = 0.1
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- Skywater 130nm PDK
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- circuit models are binded to the opensource skywater
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foundry middle-speed (ms) standard cell library
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-->
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<openfpga_architecture>
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<technology_library>
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<device_library>
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<device_model name="logic" type="transistor">
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<lib type="industry" corner="TOP_TT" ref="M" path="${OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.pm"/>
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<design vdd="0.9" pn_ratio="2"/>
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<pmos name="pch" chan_length="40e-9" min_width="140e-9" variation="logic_transistor_var"/>
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<nmos name="nch" chan_length="40e-9" min_width="140e-9" variation="logic_transistor_var"/>
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</device_model>
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<device_model name="io" type="transistor">
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<lib type="academia" ref="M" path="${OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.pm"/>
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<design vdd="2.5" pn_ratio="3"/>
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<pmos name="pch_25" chan_length="270e-9" min_width="320e-9" variation="io_transistor_var"/>
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<nmos name="nch_25" chan_length="270e-9" min_width="320e-9" variation="io_transistor_var"/>
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</device_model>
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</device_library>
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<variation_library>
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<variation name="logic_transistor_var" abs_deviation="0.1" num_sigma="3"/>
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<variation name="io_transistor_var" abs_deviation="0.1" num_sigma="3"/>
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</variation_library>
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</technology_library>
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<circuit_library>
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<circuit_model type="inv_buf" name="sky130_fd_sc_hd__inv_1" prefix="sky130_fd_sc_hd__inv_1" is_default="true" verilog_netlist="${SKYWATER_OPENFPGA_HOME}/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/inv/sky130_fd_sc_hd__inv_1.v">
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<design_technology type="cmos" topology="inverter" size="1"/>
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<device_technology device_model_name="logic"/>
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<port type="input" prefix="in" lib_name="A" size="1"/>
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<port type="output" prefix="out" lib_name="Y" size="1"/>
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<delay_matrix type="rise" in_port="in" out_port="out">
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10e-12
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</delay_matrix>
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<delay_matrix type="fall" in_port="in" out_port="out">
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10e-12
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</delay_matrix>
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</circuit_model>
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<circuit_model type="inv_buf" name="sky130_fd_sc_hd__buf_2" prefix="sky130_fd_sc_hd__buf_2" is_default="false" verilog_netlist="${SKYWATER_OPENFPGA_HOME}/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/buf/sky130_fd_sc_hd__buf_2.v">
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<design_technology type="cmos" topology="buffer" size="1" num_level="2" f_per_stage="2"/>
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<device_technology device_model_name="logic"/>
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<port type="input" prefix="in" lib_name="A" size="1"/>
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<port type="output" prefix="out" lib_name="X" size="1"/>
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<delay_matrix type="rise" in_port="in" out_port="out">
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10e-12
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</delay_matrix>
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<delay_matrix type="fall" in_port="in" out_port="out">
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10e-12
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</delay_matrix>
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</circuit_model>
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<circuit_model type="inv_buf" name="sky130_fd_sc_hd__buf_4" prefix="sky130_fd_sc_hd__buf_4" is_default="false" verilog_netlist="${SKYWATER_OPENFPGA_HOME}/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/buf/sky130_fd_sc_hd__buf_4.v">
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<design_technology type="cmos" topology="buffer" size="1" num_level="2" f_per_stage="4"/>
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<device_technology device_model_name="logic"/>
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<port type="input" prefix="in" lib_name="A" size="1"/>
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<port type="output" prefix="out" lib_name="X" size="1"/>
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<delay_matrix type="rise" in_port="in" out_port="out">
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10e-12
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</delay_matrix>
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<delay_matrix type="fall" in_port="in" out_port="out">
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10e-12
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</delay_matrix>
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</circuit_model>
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<circuit_model type="inv_buf" name="sky130_fd_sc_hd__inv_2" prefix="sky130_fd_sc_hd__inv_2" is_default="false" verilog_netlist="${SKYWATER_OPENFPGA_HOME}/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/inv/sky130_fd_sc_hd__inv_2.v">
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<design_technology type="cmos" topology="buffer" size="1"/>
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<device_technology device_model_name="logic"/>
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<port type="input" prefix="in" lib_name="A" size="1"/>
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<port type="output" prefix="out" lib_name="Y" size="1"/>
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<delay_matrix type="rise" in_port="in" out_port="out">
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10e-12
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</delay_matrix>
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<delay_matrix type="fall" in_port="in" out_port="out">
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10e-12
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</delay_matrix>
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</circuit_model>
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<circuit_model type="gate" name="sky130_fd_sc_hd__or2_1" prefix="sky130_fd_sc_hd__or2_1" is_default="true" verilog_netlist="${SKYWATER_OPENFPGA_HOME}/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/or2/sky130_fd_sc_hd__or2_1.v">
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<design_technology type="cmos" topology="OR"/>
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<device_technology device_model_name="logic"/>
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<input_buffer exist="false"/>
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<output_buffer exist="false"/>
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<port type="input" prefix="a" lib_name="A" size="1"/>
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<port type="input" prefix="b" lib_name="B" size="1"/>
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<port type="output" prefix="out" lib_name="X" size="1"/>
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<delay_matrix type="rise" in_port="a b" out_port="out">
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10e-12 5e-12
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</delay_matrix>
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<delay_matrix type="fall" in_port="a b" out_port="out">
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10e-12 5e-12
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</delay_matrix>
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</circuit_model>
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<!-- Define a circuit model for the standard cell MUX2
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OpenFPGA requires the following truth table for the MUX2
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When the select signal sel is enabled, the first input, i.e., in0
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will be propagated to the output, i.e., out
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If your standard cell provider does not offer the exact truth table,
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you can simply swap the inputs as shown in the example below
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-->
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<circuit_model type="gate" name="sky130_fd_sc_hd__mux2_1" prefix="sky130_fd_sc_hd__mux2_1" verilog_netlist="${SKYWATER_OPENFPGA_HOME}/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/mux2/sky130_fd_sc_hd__mux2_1.v">
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<design_technology type="cmos" topology="MUX2"/>
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<device_technology device_model_name="logic"/>
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<input_buffer exist="false"/>
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<output_buffer exist="false"/>
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<port type="input" prefix="in0" lib_name="A1" size="1"/>
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<port type="input" prefix="in1" lib_name="A0" size="1"/>
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<port type="input" prefix="sel" lib_name="S" size="1"/>
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<port type="output" prefix="out" lib_name="X" size="1"/>
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</circuit_model>
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<circuit_model type="chan_wire" name="chan_segment" prefix="track_seg" is_default="true">
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<design_technology type="cmos"/>
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<input_buffer exist="false"/>
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<output_buffer exist="false"/>
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<port type="input" prefix="in" size="1"/>
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<port type="output" prefix="out" size="1"/>
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<wire_param model_type="pi" R="101" C="22.5e-15" num_level="1"/>
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<!-- model_type could be T, res_val and cap_val DON'T CARE -->
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</circuit_model>
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<circuit_model type="wire" name="direct_interc" prefix="direct_interc" is_default="true">
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<design_technology type="cmos"/>
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<input_buffer exist="false"/>
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<output_buffer exist="false"/>
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<port type="input" prefix="in" size="1"/>
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<port type="output" prefix="out" size="1"/>
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<wire_param model_type="pi" R="0" C="0" num_level="1"/>
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<!-- model_type could be T, res_val cap_val should be defined -->
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</circuit_model>
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<circuit_model type="mux" name="mux_tree" prefix="mux_tree" is_default="true" dump_structural_verilog="true">
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<design_technology type="cmos" structure="tree" add_const_input="true" const_input_val="1"/>
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<input_buffer exist="false"/>
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<output_buffer exist="false"/>
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<pass_gate_logic circuit_model_name="sky130_fd_sc_hd__mux2_1"/>
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<port type="input" prefix="in" size="1"/>
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<port type="output" prefix="out" size="1"/>
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<port type="sram" prefix="sram" size="1"/>
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</circuit_model>
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<circuit_model type="mux" name="mux_tree_tapbuf" prefix="mux_tree_tapbuf" dump_structural_verilog="true">
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<design_technology type="cmos" structure="tree" add_const_input="true" const_input_val="1"/>
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<input_buffer exist="false"/>
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<output_buffer exist="true" circuit_model_name="sky130_fd_sc_hd__buf_4"/>
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<pass_gate_logic circuit_model_name="sky130_fd_sc_hd__mux2_1"/>
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<port type="input" prefix="in" size="1"/>
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<port type="output" prefix="out" size="1"/>
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<port type="sram" prefix="sram" size="1"/>
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</circuit_model>
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<!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET> -->
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<circuit_model type="ff" name="sky130_fd_sc_hd__sdfrtp_1" prefix="sky130_fd_sc_hd__sdfrtp_1" verilog_netlist="${SKYWATER_OPENFPGA_HOME}/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/sdfrtp/sky130_fd_sc_hd__sdfrtp_1.v">
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<design_technology type="cmos"/>
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<input_buffer exist="true" circuit_model_name="sky130_fd_sc_hd__inv_1"/>
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<output_buffer exist="true" circuit_model_name="sky130_fd_sc_hd__inv_1"/>
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<port type="input" prefix="D" size="1"/>
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<port type="input" prefix="DI" lib_name="SCD" size="1"/>
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<port type="input" prefix="Test_en" lib_name="SCE" size="1" is_global="true" default_val="0"/>
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<port type="input" prefix="reset" lib_name="RESET_B" size="1" default_val="1"/>
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<port type="output" prefix="Q" size="1"/>
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<port type="clock" prefix="clk" lib_name="CLK" size="1" is_global="false" default_val="0" />
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</circuit_model>
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<circuit_model type="lut" name="frac_lut4" prefix="frac_lut4" dump_structural_verilog="true">
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<design_technology type="cmos" fracturable_lut="true"/>
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<input_buffer exist="false"/>
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<output_buffer exist="true" circuit_model_name="sky130_fd_sc_hd__buf_2"/>
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<lut_input_inverter exist="true" circuit_model_name="sky130_fd_sc_hd__inv_1"/>
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<lut_input_buffer exist="true" circuit_model_name="sky130_fd_sc_hd__buf_2"/>
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<lut_intermediate_buffer exist="true" circuit_model_name="sky130_fd_sc_hd__buf_2" location_map="-1-"/>
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<pass_gate_logic circuit_model_name="sky130_fd_sc_hd__mux2_1"/>
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<port type="input" prefix="in" size="4" tri_state_map="---1" circuit_model_name="sky130_fd_sc_hd__or2_1"/>
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<port type="output" prefix="lut2_out" size="2" lut_frac_level="2" lut_output_mask="2,3"/>
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<port type="output" prefix="lut4_out" size="1" lut_output_mask="0"/>
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<port type="sram" prefix="sram" size="16"/>
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<port type="sram" prefix="mode" size="1" mode_select="true" circuit_model_name="sky130_fd_sc_hd__dfrtp_1" default_val="1"/>
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</circuit_model>
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<!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET> -->
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<circuit_model type="ccff" name="sky130_fd_sc_hd__dfrtp_1" prefix="sky130_fd_sc_hd__dfrtp_1" verilog_netlist="${SKYWATER_OPENFPGA_HOME}/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/dfrtp/sky130_fd_sc_hd__dfrtp_1.v">
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<design_technology type="cmos"/>
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<input_buffer exist="true" circuit_model_name="sky130_fd_sc_hd__inv_1"/>
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<output_buffer exist="true" circuit_model_name="sky130_fd_sc_hd__inv_1"/>
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<port type="input" prefix="D" size="1"/>
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<port type="output" prefix="Q" size="1"/>
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<port type="clock" prefix="prog_clk" lib_name="CLK" size="1" is_global="true" default_val="0" is_prog="true"/>
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<port type="input" prefix="pReset" lib_name="RESET_B" size="1" is_global="true" default_val="1" is_prog="true" is_reset="true"/>
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</circuit_model>
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<circuit_model type="iopad" name="EMBEDDED_IO_HD" prefix="EMBEDDED_IO_HD" is_default="true" verilog_netlist="${SKYWATER_OPENFPGA_HOME}/HDL/common/digital_io_hd.v">
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<design_technology type="cmos"/>
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<input_buffer exist="true" circuit_model_name="sky130_fd_sc_hd__inv_1"/>
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<output_buffer exist="true" circuit_model_name="sky130_fd_sc_hd__inv_1"/>
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<port type="input" prefix="SOC_IN" lib_name="SOC_IN" size="1" is_global="true" is_io="true" is_data_io="true"/>
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<port type="output" prefix="SOC_OUT" lib_name="SOC_OUT" size="1" is_global="true" is_io="true" is_data_io="true"/>
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<port type="output" prefix="SOC_DIR" lib_name="SOC_DIR" size="1" is_global="true" is_io="true"/>
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<port type="input" prefix="IO_ISOL_N" lib_name="IO_ISOL_N" size="1" is_global="true" default_val="1"/>
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<port type="output" prefix="inpad" lib_name="FPGA_IN" size="1"/>
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<port type="input" prefix="outpad" lib_name="FPGA_OUT" size="1"/>
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<port type="sram" prefix="en" lib_name="FPGA_DIR" size="1" mode_select="true" circuit_model_name="sky130_fd_sc_hd__dfrtp_1" default_val="1"/>
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</circuit_model>
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<circuit_model type="hard_logic" name="sky130_fd_sc_hd__mux2_1_wrapper" prefix="sky130_fd_sc_hd__mux2_1_wrapper" verilog_netlist="${SKYWATER_OPENFPGA_HOME}/HDL/common/sky130_fd_sc_hd_wrapper.v">
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<design_technology type="cmos"/>
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<device_technology device_model_name="logic"/>
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<input_buffer exist="false"/>
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<output_buffer exist="false"/>
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<port type="input" prefix="a" lib_name="A0" size="1"/>
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<port type="input" prefix="b" lib_name="A1" size="1"/>
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<port type="input" prefix="cin" lib_name="S" size="1"/>
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<port type="output" prefix="cout" lib_name="X" size="1"/>
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</circuit_model>
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</circuit_library>
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<configuration_protocol>
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<organization type="scan_chain" circuit_model_name="sky130_fd_sc_hd__dfrtp_1" num_regions="1"/>
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</configuration_protocol>
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<connection_block>
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<switch name="ipin_cblock" circuit_model_name="mux_tree_tapbuf"/>
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</connection_block>
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<switch_block>
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<switch name="L1_mux" circuit_model_name="mux_tree_tapbuf"/>
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<switch name="L2_mux" circuit_model_name="mux_tree_tapbuf"/>
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<switch name="L4_mux" circuit_model_name="mux_tree_tapbuf"/>
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</switch_block>
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<routing_segment>
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<segment name="L1" circuit_model_name="chan_segment"/>
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<segment name="L2" circuit_model_name="chan_segment"/>
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<segment name="L4" circuit_model_name="chan_segment"/>
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</routing_segment>
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<direct_connection>
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<direct name="carry_chain" circuit_model_name="direct_interc"/>
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<direct name="shift_register" circuit_model_name="direct_interc"/>
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<direct name="scan_chain" circuit_model_name="direct_interc" type="column" x_dir="positive" y_dir="positive"/>
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</direct_connection>
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<tile_annotations>
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<global_port name="clk" tile_port="clb.clk" is_clock="true" default_val="0"/>
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<global_port name="Reset" tile_port="clb.reset" is_reset="true" default_val="1"/>
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</tile_annotations>
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<pb_type_annotations>
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<!-- physical pb_type binding in complex block IO -->
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<pb_type name="io" physical_mode_name="physical" idle_mode_name="inpad"/>
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<!-- IMPORTANT: must set unused I/Os to operating in INPUT mode !!! -->
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<pb_type name="io[physical].iopad" circuit_model_name="EMBEDDED_IO_HD" mode_bits="1"/>
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<pb_type name="io[inpad].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/>
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<pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/>
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<!-- End physical pb_type binding in complex block IO -->
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<!-- physical pb_type binding in complex block CLB -->
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<!-- physical mode will be the default mode if not specified -->
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<pb_type name="clb.fle" physical_mode_name="physical"/>
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<pb_type name="clb.fle[physical].fabric.frac_logic.frac_lut4" circuit_model_name="frac_lut4" mode_bits="0"/>
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<pb_type name="clb.fle[physical].fabric.frac_logic.carry_follower" circuit_model_name="sky130_fd_sc_hd__mux2_1_wrapper"/>
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<pb_type name="clb.fle[physical].fabric.ff" circuit_model_name="sky130_fd_sc_hd__sdfrtp_1"/>
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<!-- Binding operating pb_type to physical pb_type -->
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<!-- Binding operating pb_types in mode 'ble4' -->
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<pb_type name="clb.fle[n1_lut4].ble4.lut4" physical_pb_type_name="clb.fle[physical].fabric.frac_logic.frac_lut4" mode_bits="0">
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<!-- Binding the lut4 to the first 4 inputs of fracturable lut4 -->
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<port name="in" physical_mode_port="in[0:3]"/>
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<port name="out" physical_mode_port="lut4_out"/>
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</pb_type>
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<pb_type name="clb.fle[n1_lut4].ble4.ff" physical_pb_type_name="clb.fle[physical].fabric.ff"/>
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<!-- Binding operating pb_types in mode 'shift_register' -->
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<pb_type name="clb.fle[shift_register].shift_reg.ff" physical_pb_type_name="clb.fle[physical].fabric.ff"/>
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<!-- End physical pb_type binding in complex block IO -->
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</pb_type_annotations>
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</openfpga_architecture>
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@ -0,0 +1,591 @@
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<!--
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Low-cost homogeneous FPGA Architecture.
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|
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- Skywater 130 nm technology
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- General purpose logic block:
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K = 4, N = 8, fracturable 4 LUTs (can operate as one 4-LUT or two 3-LUTs with all 3 inputs shared)
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with optionally registered outputs
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- Routing architecture:
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- 10% L = 1, fc_in = 0.15, Fc_out = 0.10
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- 10% L = 2, fc_in = 0.15, Fc_out = 0.10
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- 80% L = 4, fc_in = 0.15, Fc_out = 0.10
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- 100 routing tracks per channel
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Authors: Xifan Tang
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-->
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<architecture>
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<!--
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ODIN II specific config begins
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Describes the types of user-specified netlist blocks (in blif, this corresponds to
|
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".model [type_of_block]") that this architecture supports.
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|
||||
Note: Basic LUTs, I/Os, and flip-flops are not included here as there are
|
||||
already special structures in blif (.names, .input, .output, and .latch)
|
||||
that describe them.
|
||||
-->
|
||||
<models>
|
||||
<!-- A virtual model for I/O to be used in the physical mode of io block -->
|
||||
<model name="io">
|
||||
<input_ports>
|
||||
<port name="outpad"/>
|
||||
</input_ports>
|
||||
<output_ports>
|
||||
<port name="inpad"/>
|
||||
</output_ports>
|
||||
</model>
|
||||
|
||||
<model name="frac_lut4">
|
||||
<input_ports>
|
||||
<port name="in"/>
|
||||
</input_ports>
|
||||
<output_ports>
|
||||
<port name="lut2_out"/>
|
||||
<port name="lut4_out"/>
|
||||
</output_ports>
|
||||
</model>
|
||||
<model name="carry_follower">
|
||||
<input_ports>
|
||||
<port name="a"/>
|
||||
<port name="b"/>
|
||||
<port name="cin"/>
|
||||
</input_ports>
|
||||
<output_ports>
|
||||
<port name="cout"/>
|
||||
</output_ports>
|
||||
</model>
|
||||
<!-- A virtual model for scan-chain flip-flop to be used in the physical mode of FF -->
|
||||
<model name="scff">
|
||||
<input_ports>
|
||||
<port name="D" clock="clk"/>
|
||||
<port name="DI" clock="clk"/>
|
||||
<port name="reset" clock="clk"/>
|
||||
<port name="clk" is_clock="1"/>
|
||||
</input_ports>
|
||||
<output_ports>
|
||||
<port name="Q" clock="clk"/>
|
||||
</output_ports>
|
||||
</model>
|
||||
</models>
|
||||
<tiles>
|
||||
<!-- Do NOT add clock pins to I/O here!!! VPR does not build clock network in the way that OpenFPGA can support
|
||||
If you need to register the I/O, define clocks in the circuit models
|
||||
These clocks can be handled in back-end
|
||||
-->
|
||||
<!-- Top-side has 1 I/O per tile -->
|
||||
<tile name="io_top" capacity="32" area="0">
|
||||
<equivalent_sites>
|
||||
<site pb_type="io"/>
|
||||
</equivalent_sites>
|
||||
<input name="outpad" num_pins="1"/>
|
||||
<output name="inpad" num_pins="1"/>
|
||||
<fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
|
||||
<pinlocations pattern="custom">
|
||||
<loc side="bottom">io_top.outpad io_top.inpad</loc>
|
||||
</pinlocations>
|
||||
</tile>
|
||||
<!-- Right-side has 1 I/O per tile -->
|
||||
<tile name="io_right" capacity="32" area="0">
|
||||
<equivalent_sites>
|
||||
<site pb_type="io"/>
|
||||
</equivalent_sites>
|
||||
<input name="outpad" num_pins="1"/>
|
||||
<output name="inpad" num_pins="1"/>
|
||||
<fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
|
||||
<pinlocations pattern="custom">
|
||||
<loc side="left">io_right.outpad io_right.inpad</loc>
|
||||
</pinlocations>
|
||||
</tile>
|
||||
<!-- Bottom-side has 9 I/O per tile -->
|
||||
<tile name="io_bottom" capacity="32" area="0">
|
||||
<equivalent_sites>
|
||||
<site pb_type="io"/>
|
||||
</equivalent_sites>
|
||||
<input name="outpad" num_pins="1"/>
|
||||
<output name="inpad" num_pins="1"/>
|
||||
<fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
|
||||
<pinlocations pattern="custom">
|
||||
<loc side="top">io_bottom.outpad io_bottom.inpad</loc>
|
||||
</pinlocations>
|
||||
</tile>
|
||||
<!-- Left-side has 1 I/O per tile -->
|
||||
<tile name="io_left" capacity="32" area="0">
|
||||
<equivalent_sites>
|
||||
<site pb_type="io"/>
|
||||
</equivalent_sites>
|
||||
<input name="outpad" num_pins="1"/>
|
||||
<output name="inpad" num_pins="1"/>
|
||||
<fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
|
||||
<pinlocations pattern="custom">
|
||||
<loc side="right">io_left.outpad io_left.inpad</loc>
|
||||
</pinlocations>
|
||||
</tile>
|
||||
<!-- CLB has most pins on the top and right sides -->
|
||||
<tile name="clb" area="53894">
|
||||
<equivalent_sites>
|
||||
<site pb_type="clb"/>
|
||||
</equivalent_sites>
|
||||
<input name="I" num_pins="24" equivalent="full"/>
|
||||
<input name="reg_in" num_pins="1"/>
|
||||
<input name="sc_in" num_pins="1"/>
|
||||
<input name="cin" num_pins="1"/>
|
||||
<input name="reset" num_pins="1" is_non_clock_global="true"/>
|
||||
<output name="O" num_pins="8" equivalent="none"/>
|
||||
<output name="reg_out" num_pins="1"/>
|
||||
<output name="sc_out" num_pins="1"/>
|
||||
<output name="cout" num_pins="1"/>
|
||||
<clock name="clk" num_pins="1"/>
|
||||
<fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10">
|
||||
<fc_override port_name="reg_in" fc_type="frac" fc_val="0"/>
|
||||
<fc_override port_name="reg_out" fc_type="frac" fc_val="0"/>
|
||||
<fc_override port_name="sc_in" fc_type="frac" fc_val="0"/>
|
||||
<fc_override port_name="sc_out" fc_type="frac" fc_val="0"/>
|
||||
<fc_override port_name="cin" fc_type="frac" fc_val="0"/>
|
||||
<fc_override port_name="cout" fc_type="frac" fc_val="0"/>
|
||||
<fc_override port_name="clk" fc_type="frac" fc_val="0"/>
|
||||
<fc_override port_name="reset" fc_type="frac" fc_val="0"/>
|
||||
</fc>
|
||||
<!--pinlocations pattern="spread"/-->
|
||||
<pinlocations pattern="custom">
|
||||
<loc side="left">clb.clk clb.reset</loc>
|
||||
<loc side="top">clb.reg_in clb.sc_in clb.cin clb.O[7:0] clb.I[11:0]</loc>
|
||||
<loc side="right">clb.I[23:12]</loc>
|
||||
<loc side="bottom">clb.reg_out clb.sc_out clb.cout</loc>
|
||||
</pinlocations>
|
||||
</tile>
|
||||
</tiles>
|
||||
<!-- ODIN II specific config ends -->
|
||||
<!-- Physical descriptions begin -->
|
||||
<layout tileable="true">
|
||||
<auto_layout aspect_ratio="1.0">
|
||||
<!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners-->
|
||||
<row type="io_top" starty="H-1" priority="100"/>
|
||||
<row type="io_bottom" starty="0" priority="100"/>
|
||||
<col type="io_left" startx="0" priority="100"/>
|
||||
<col type="io_right" startx="W-1" priority="100"/>
|
||||
<corners type="EMPTY" priority="101"/>
|
||||
<!--Fill with 'clb'-->
|
||||
<fill type="clb" priority="10"/>
|
||||
</auto_layout>
|
||||
<fixed_layout name="2x2" width="4" height="4">
|
||||
<!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners-->
|
||||
<row type="io_top" starty="H-1" priority="100"/>
|
||||
<row type="io_bottom" starty="0" priority="100"/>
|
||||
<col type="io_left" startx="0" priority="100"/>
|
||||
<col type="io_right" startx="W-1" priority="100"/>
|
||||
<corners type="EMPTY" priority="101"/>
|
||||
<!--Fill with 'clb'-->
|
||||
<fill type="clb" priority="10"/>
|
||||
</fixed_layout>
|
||||
<fixed_layout name="12x12" width="14" height="14">
|
||||
<!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners-->
|
||||
<row type="io_top" starty="H-1" priority="100"/>
|
||||
<row type="io_bottom" starty="0" priority="100"/>
|
||||
<col type="io_left" startx="0" priority="100"/>
|
||||
<col type="io_right" startx="W-1" priority="100"/>
|
||||
<corners type="EMPTY" priority="101"/>
|
||||
<!--Fill with 'clb'-->
|
||||
<fill type="clb" priority="10"/>
|
||||
</fixed_layout>
|
||||
<fixed_layout name="32x32" width="34" height="34">
|
||||
<!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners-->
|
||||
<row type="io_top" starty="H-1" priority="100"/>
|
||||
<row type="io_bottom" starty="0" priority="100"/>
|
||||
<col type="io_left" startx="0" priority="100"/>
|
||||
<col type="io_right" startx="W-1" priority="100"/>
|
||||
<corners type="EMPTY" priority="101"/>
|
||||
<!--Fill with 'clb'-->
|
||||
<fill type="clb" priority="10"/>
|
||||
</fixed_layout>
|
||||
</layout>
|
||||
<device>
|
||||
<!-- VB & JL: Using Ian Kuon's transistor sizing and drive strength data for routing, at 40 nm. Ian used BPTM
|
||||
models. We are modifying the delay values however, to include metal C and R, which allows more architecture
|
||||
experimentation. We are also modifying the relative resistance of PMOS to be 1.8x that of NMOS
|
||||
(vs. Ian's 3x) as 1.8x lines up with Jeff G's data from a 45 nm process (and is more typical of
|
||||
45 nm in general). I'm upping the Rmin_nmos from Ian's just over 6k to nearly 9k, and dropping
|
||||
RminW_pmos from 18k to 16k to hit this 1.8x ratio, while keeping the delays of buffers approximately
|
||||
lined up with Stratix IV.
|
||||
We are using Jeff G.'s capacitance data for 45 nm (in tech/ptm_45nm).
|
||||
Jeff's tables list C in for transistors with widths in multiples of the minimum feature size (45 nm).
|
||||
The minimum contactable transistor is 2.5 * 45 nm, so I need to multiply drive strength sizes in this file
|
||||
by 2.5x when looking up in Jeff's tables.
|
||||
The delay values are lined up with Stratix IV, which has an architecture similar to this
|
||||
proposed FPGA, and which is also 40 nm
|
||||
C_ipin_cblock: input capacitance of a track buffer, which VPR assumes is a single-stage
|
||||
4x minimum drive strength buffer. -->
|
||||
<sizing R_minW_nmos="8926" R_minW_pmos="16067"/>
|
||||
<!-- The grid_logic_tile_area below will be used for all blocks that do not explicitly set their own (non-routing)
|
||||
area; set to 0 since we explicitly set the area of all blocks currently in this architecture file.
|
||||
-->
|
||||
<area grid_logic_tile_area="0"/>
|
||||
<chan_width_distr>
|
||||
<x distr="uniform" peak="1.000000"/>
|
||||
<y distr="uniform" peak="1.000000"/>
|
||||
</chan_width_distr>
|
||||
<switch_block type="wilton" fs="3" sub_type="subset" sub_fs="3"/>
|
||||
<connection_block input_switch_name="ipin_cblock"/>
|
||||
</device>
|
||||
<switchlist>
|
||||
<!-- VB: the mux_trans_size and buf_size data below is in minimum width transistor *areas*, assuming the purple
|
||||
book area formula. This means the mux transistors are about 5x minimum drive strength.
|
||||
We assume the first stage of the buffer is 3x min drive strength to be reasonable given the large
|
||||
mux transistors, and this gives a reasonable stage ratio of a bit over 5x to the second stage. We assume
|
||||
the n and p transistors in the first stage are equal-sized to lower the buffer trip point, since it's fed
|
||||
by a pass transistor mux. We can then reverse engineer the buffer second stage to hit the specified
|
||||
buf_size (really buffer area) - 16.2x minimum drive nmos and 1.8*16.2 = 29.2x minimum drive.
|
||||
I then took the data from Jeff G.'s PTM modeling of 45 nm to get the Cin (gate of first stage) and Cout
|
||||
(diff of second stage) listed below. Jeff's models are in tech/ptm_45nm, and are in min feature multiples.
|
||||
The minimum contactable transistor is 2.5 * 45 nm, so I need to multiply the drive strength sizes above by
|
||||
2.5x when looking up in Jeff's tables.
|
||||
Finally, we choose a switch delay (58 ps) that leads to length 4 wires having a delay equal to that of SIV of 126 ps.
|
||||
This also leads to the switch being 46% of the total wire delay, which is reasonable. -->
|
||||
<switch type="mux" name="L1_mux" R="551" Cin=".77e-15" Cout="4e-15" Tdel="58e-12" mux_trans_size="2.630740" buf_size="27.645901"/>
|
||||
<switch type="mux" name="L2_mux" R="551" Cin=".77e-15" Cout="4e-15" Tdel="58e-12" mux_trans_size="2.630740" buf_size="27.645901"/>
|
||||
<switch type="mux" name="L4_mux" R="551" Cin=".77e-15" Cout="4e-15" Tdel="58e-12" mux_trans_size="2.630740" buf_size="27.645901"/>
|
||||
<!--switch ipin_cblock resistance set to yeild for 4x minimum drive strength buffer-->
|
||||
<switch type="mux" name="ipin_cblock" R="2231.5" Cout="0." Cin="1.47e-15" Tdel="7.247000e-11" mux_trans_size="1.222260" buf_size="auto"/>
|
||||
</switchlist>
|
||||
<segmentlist>
|
||||
<!--- VB & JL: using ITRS metal stack data, 96 nm half pitch wires, which are intermediate metal width/space.
|
||||
With the 96 nm half pitch, such wires would take 60 um of height, vs. a 90 nm high (approximated as square) Stratix IV tile so this seems
|
||||
reasonable. Using a tile length of 90 nm, corresponding to the length of a Stratix IV tile if it were square. -->
|
||||
<!-- GIVE a specific name for the segment! OpenFPGA appreciate that! -->
|
||||
<segment name="L1" freq="0.10" length="1" type="unidir" Rmetal="101" Cmetal="22.5e-15">
|
||||
<mux name="L1_mux"/>
|
||||
<sb type="pattern">1 1</sb>
|
||||
<cb type="pattern">1</cb>
|
||||
</segment>
|
||||
<segment name="L2" freq="0.10" length="2" type="unidir" Rmetal="101" Cmetal="22.5e-15">
|
||||
<mux name="L2_mux"/>
|
||||
<sb type="pattern">1 1 1</sb>
|
||||
<cb type="pattern">1 1</cb>
|
||||
</segment>
|
||||
<segment name="L4" freq="0.80" length="4" type="unidir" Rmetal="101" Cmetal="22.5e-15">
|
||||
<mux name="L4_mux"/>
|
||||
<sb type="pattern">1 1 1 1 1</sb>
|
||||
<cb type="pattern">1 1 1 1</cb>
|
||||
</segment>
|
||||
</segmentlist>
|
||||
<directlist>
|
||||
<direct name="carry_chain" from_pin="clb.cout" to_pin="clb.cin" x_offset="0" y_offset="-1" z_offset="0"/>
|
||||
<direct name="shift_register" from_pin="clb.reg_out" to_pin="clb.reg_in" x_offset="0" y_offset="-1" z_offset="0"/>
|
||||
<direct name="scan_chain" from_pin="clb.sc_out" to_pin="clb.sc_in" x_offset="0" y_offset="-1" z_offset="0"/>
|
||||
</directlist>
|
||||
<complexblocklist>
|
||||
<!-- Define input pads begin -->
|
||||
<pb_type name="io">
|
||||
<input name="outpad" num_pins="1"/>
|
||||
<output name="inpad" num_pins="1"/>
|
||||
<!-- Do NOT add clock pins to I/O here!!! VPR does not build clock network in the way that OpenFPGA can support
|
||||
If you need to register the I/O, define clocks in the circuit models
|
||||
These clocks can be handled in back-end
|
||||
-->
|
||||
<!-- A mode denotes the physical implementation of an I/O
|
||||
This mode will be not packable but is mainly used for fabric verilog generation
|
||||
-->
|
||||
<mode name="physical" disabled_in_pack="true">
|
||||
<pb_type name="iopad" blif_model=".subckt io" num_pb="1">
|
||||
<input name="outpad" num_pins="1"/>
|
||||
<output name="inpad" num_pins="1"/>
|
||||
</pb_type>
|
||||
<interconnect>
|
||||
<direct name="outpad" input="io.outpad" output="iopad.outpad">
|
||||
<delay_constant max="1.394e-11" in_port="io.outpad" out_port="iopad.outpad"/>
|
||||
</direct>
|
||||
<direct name="inpad" input="iopad.inpad" output="io.inpad">
|
||||
<delay_constant max="4.243e-11" in_port="iopad.inpad" out_port="io.inpad"/>
|
||||
</direct>
|
||||
</interconnect>
|
||||
</mode>
|
||||
|
||||
<!-- IOs can operate as either inputs or outputs.
|
||||
Delays below come from Ian Kuon. They are small, so they should be interpreted as
|
||||
the delays to and from registers in the I/O (and generally I/Os are registered
|
||||
today and that is when you timing analyze them.
|
||||
-->
|
||||
<mode name="inpad">
|
||||
<pb_type name="inpad" blif_model=".input" num_pb="1">
|
||||
<output name="inpad" num_pins="1"/>
|
||||
</pb_type>
|
||||
<interconnect>
|
||||
<direct name="inpad" input="inpad.inpad" output="io.inpad">
|
||||
<delay_constant max="4.243e-11" in_port="inpad.inpad" out_port="io.inpad"/>
|
||||
</direct>
|
||||
</interconnect>
|
||||
</mode>
|
||||
<mode name="outpad">
|
||||
<pb_type name="outpad" blif_model=".output" num_pb="1">
|
||||
<input name="outpad" num_pins="1"/>
|
||||
</pb_type>
|
||||
<interconnect>
|
||||
<direct name="outpad" input="io.outpad" output="outpad.outpad">
|
||||
<delay_constant max="1.394e-11" in_port="io.outpad" out_port="outpad.outpad"/>
|
||||
</direct>
|
||||
</interconnect>
|
||||
</mode>
|
||||
<power method="ignore"/>
|
||||
</pb_type>
|
||||
<!-- Define I/O pads ends -->
|
||||
<!-- Define general purpose logic block (CLB) begin -->
|
||||
<!-- -Due to the absence of local routing,
|
||||
the 4 inputs of fracturable LUT4 are no longer equivalent,
|
||||
because the 4th input can not be switched when the dual-LUT3 modes are used.
|
||||
So pin equivalence should be applied to the first 3 inputs only
|
||||
-->
|
||||
<pb_type name="clb">
|
||||
<input name="I" num_pins="24" equivalent="full"/>
|
||||
<input name="reg_in" num_pins="1"/>
|
||||
<input name="sc_in" num_pins="1"/>
|
||||
<input name="cin" num_pins="1"/>
|
||||
<input name="reset" num_pins="1" is_non_clock_global="true"/>
|
||||
<output name="O" num_pins="8" equivalent="none"/>
|
||||
<output name="reg_out" num_pins="1"/>
|
||||
<output name="sc_out" num_pins="1"/>
|
||||
<output name="cout" num_pins="1"/>
|
||||
<clock name="clk" num_pins="1"/>
|
||||
<!-- Describe fracturable logic element.
|
||||
Each fracturable logic element has a 6-LUT that can alternatively operate as two 5-LUTs with shared inputs.
|
||||
The outputs of the fracturable logic element can be optionally registered
|
||||
-->
|
||||
<pb_type name="fle" num_pb="8">
|
||||
<input name="in" num_pins="4"/>
|
||||
<input name="reg_in" num_pins="1"/>
|
||||
<input name="sc_in" num_pins="1"/>
|
||||
<input name="cin" num_pins="1"/>
|
||||
<input name="reset" num_pins="1"/>
|
||||
<output name="out" num_pins="1"/>
|
||||
<output name="reg_out" num_pins="1"/>
|
||||
<output name="sc_out" num_pins="1"/>
|
||||
<output name="cout" num_pins="1"/>
|
||||
<clock name="clk" num_pins="1"/>
|
||||
<!-- Physical mode definition begin (physical implementation of the fle) -->
|
||||
<mode name="physical" disabled_in_pack="true">
|
||||
<pb_type name="fabric" num_pb="1">
|
||||
<input name="in" num_pins="4"/>
|
||||
<input name="reg_in" num_pins="1"/>
|
||||
<input name="sc_in" num_pins="1"/>
|
||||
<input name="cin" num_pins="1"/>
|
||||
<input name="reset" num_pins="1"/>
|
||||
<output name="out" num_pins="1"/>
|
||||
<output name="reg_out" num_pins="1"/>
|
||||
<output name="sc_out" num_pins="1"/>
|
||||
<output name="cout" num_pins="1"/>
|
||||
<clock name="clk" num_pins="1"/>
|
||||
<pb_type name="frac_logic" num_pb="1">
|
||||
<input name="in" num_pins="4"/>
|
||||
<input name="cin" num_pins="1"/>
|
||||
<output name="out" num_pins="1"/>
|
||||
<output name="cout" num_pins="1"/>
|
||||
<!-- Define LUT -->
|
||||
<pb_type name="frac_lut4" blif_model=".subckt frac_lut4" num_pb="1">
|
||||
<input name="in" num_pins="4"/>
|
||||
<output name="lut2_out" num_pins="2"/>
|
||||
<output name="lut4_out" num_pins="1"/>
|
||||
</pb_type>
|
||||
<pb_type name="carry_follower" blif_model=".subckt carry_follower" num_pb="1">
|
||||
<input name="a" num_pins="1"/>
|
||||
<input name="b" num_pins="1"/>
|
||||
<input name="cin" num_pins="1"/>
|
||||
<output name="cout" num_pins="1"/>
|
||||
</pb_type>
|
||||
<interconnect>
|
||||
<direct name="direct1" input="frac_logic.in[0:1]" output="frac_lut4.in[0:1]"/>
|
||||
<direct name="direct2" input="frac_logic.in[3:3]" output="frac_lut4.in[3:3]"/>
|
||||
<direct name="direct3" input="frac_logic.cin" output="carry_follower.b"/>
|
||||
<direct name="direct4" input="frac_lut4.lut2_out[1:1]" output="carry_follower.a"/>
|
||||
<direct name="direct5" input="frac_lut4.lut2_out[0:0]" output="carry_follower.cin"/>
|
||||
<direct name="direct6" input="carry_follower.cout" output="frac_logic.cout"/>
|
||||
<!-- Xifan Tang: I use out[0] because the output of lut6 in lut6 mode is wired to the out[0] -->
|
||||
<direct name="direct7" input="frac_lut4.lut4_out" output="frac_logic.out"/>
|
||||
<mux name="mux2" input="frac_logic.cin frac_logic.in[2:2]" output="frac_lut4.in[2:2]"/>
|
||||
</interconnect>
|
||||
</pb_type>
|
||||
<!-- Define flip-flop with scan-chain capability, DI is the scan-chain data input -->
|
||||
<pb_type name="ff" blif_model=".subckt scff" num_pb="1">
|
||||
<input name="D" num_pins="1"/>
|
||||
<input name="DI" num_pins="1"/>
|
||||
<input name="reset" num_pins="1"/>
|
||||
<output name="Q" num_pins="1"/>
|
||||
<clock name="clk" num_pins="1"/>
|
||||
<T_setup value="66e-12" port="ff.D" clock="clk"/>
|
||||
<T_setup value="66e-12" port="ff.DI" clock="clk"/>
|
||||
<T_setup value="66e-12" port="ff.reset" clock="clk"/>
|
||||
<T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
|
||||
</pb_type>
|
||||
<interconnect>
|
||||
<direct name="direct1" input="fabric.in" output="frac_logic.in"/>
|
||||
<direct name="direct2" input="fabric.sc_in" output="ff.DI"/>
|
||||
<direct name="direct4" input="ff.Q" output="fabric.sc_out"/>
|
||||
<direct name="direct5" input="ff.Q" output="fabric.reg_out"/>
|
||||
<complete name="complete1" input="fabric.clk" output="ff.clk"/>
|
||||
<complete name="complete2" input="fabric.reset" output="ff.reset"/>
|
||||
<mux name="mux1" input="frac_logic.out fabric.reg_in" output="ff.D">
|
||||
<delay_constant max="25e-12" in_port="frac_logic.out" out_port="ff.D"/>
|
||||
<delay_constant max="45e-12" in_port="fabric.reg_in" out_port="ff.D"/>
|
||||
</mux>
|
||||
<mux name="mux2" input="ff.Q frac_logic.out" output="fabric.out">
|
||||
<!-- LUT to output is faster than FF to output on a Stratix IV -->
|
||||
<delay_constant max="25e-12" in_port="frac_logic.out" out_port="fabric.out"/>
|
||||
<delay_constant max="45e-12" in_port="ff.Q" out_port="fabric.out"/>
|
||||
</mux>
|
||||
</interconnect>
|
||||
</pb_type>
|
||||
<interconnect>
|
||||
<direct name="direct1" input="fle.in" output="fabric.in"/>
|
||||
<direct name="direct2" input="fle.reg_in" output="fabric.reg_in"/>
|
||||
<direct name="direct3" input="fle.sc_in" output="fabric.sc_in"/>
|
||||
<direct name="direct4" input="fle.cin" output="fabric.cin"/>
|
||||
<direct name="direct5" input="fabric.out" output="fle.out"/>
|
||||
<direct name="direct6" input="fabric.reg_out" output="fle.reg_out"/>
|
||||
<direct name="direct7" input="fabric.sc_out" output="fle.sc_out"/>
|
||||
<direct name="direct8" input="fabric.cout" output="fle.cout"/>
|
||||
<direct name="direct9" input="fle.clk" output="fabric.clk"/>
|
||||
<direct name="direct10" input="fle.reset" output="fabric.reset"/>
|
||||
</interconnect>
|
||||
</mode>
|
||||
<!-- Physical mode definition end (physical implementation of the fle) -->
|
||||
<mode name="n1_lut4">
|
||||
<!-- Define 4-LUT mode -->
|
||||
<pb_type name="ble4" num_pb="1">
|
||||
<input name="in" num_pins="4"/>
|
||||
<output name="out" num_pins="1"/>
|
||||
<clock name="clk" num_pins="1"/>
|
||||
<!-- Define LUT -->
|
||||
<pb_type name="lut4" blif_model=".names" num_pb="1" class="lut">
|
||||
<input name="in" num_pins="4" port_class="lut_in"/>
|
||||
<output name="out" num_pins="1" port_class="lut_out"/>
|
||||
<!-- LUT timing using delay matrix -->
|
||||
<!-- These are the physical delay inputs on a Stratix IV LUT but because VPR cannot do LUT rebalancing,
|
||||
we instead take the average of these numbers to get more stable results
|
||||
82e-12
|
||||
173e-12
|
||||
261e-12
|
||||
263e-12
|
||||
398e-12
|
||||
397e-12
|
||||
-->
|
||||
<delay_matrix type="max" in_port="lut4.in" out_port="lut4.out">
|
||||
261e-12
|
||||
261e-12
|
||||
261e-12
|
||||
261e-12
|
||||
</delay_matrix>
|
||||
</pb_type>
|
||||
<!-- Define flip-flop -->
|
||||
<pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop">
|
||||
<input name="D" num_pins="1" port_class="D"/>
|
||||
<output name="Q" num_pins="1" port_class="Q"/>
|
||||
<clock name="clk" num_pins="1" port_class="clock"/>
|
||||
<T_setup value="66e-12" port="ff.D" clock="clk"/>
|
||||
<T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
|
||||
</pb_type>
|
||||
<interconnect>
|
||||
<direct name="direct1" input="ble4.in" output="lut4[0:0].in"/>
|
||||
<direct name="direct2" input="lut4.out" output="ff.D">
|
||||
<!-- Advanced user option that tells CAD tool to find LUT+FF pairs in netlist -->
|
||||
<pack_pattern name="ble4" in_port="lut4.out" out_port="ff.D"/>
|
||||
</direct>
|
||||
<direct name="direct3" input="ble4.clk" output="ff.clk"/>
|
||||
<mux name="mux1" input="ff.Q lut4.out" output="ble4.out">
|
||||
<!-- LUT to output is faster than FF to output on a Stratix IV -->
|
||||
<delay_constant max="25e-12" in_port="lut4.out" out_port="ble4.out"/>
|
||||
<delay_constant max="45e-12" in_port="ff.Q" out_port="ble4.out"/>
|
||||
</mux>
|
||||
</interconnect>
|
||||
</pb_type>
|
||||
<interconnect>
|
||||
<direct name="direct1" input="fle.in" output="ble4.in"/>
|
||||
<direct name="direct2" input="ble4.out" output="fle.out"/>
|
||||
<direct name="direct3" input="fle.clk" output="ble4.clk"/>
|
||||
</interconnect>
|
||||
</mode>
|
||||
<!-- 4-LUT mode definition end -->
|
||||
<!-- Define shift register begin -->
|
||||
<mode name="shift_register">
|
||||
<pb_type name="shift_reg" num_pb="1">
|
||||
<input name="reg_in" num_pins="1"/>
|
||||
<output name="ff_out" num_pins="1"/>
|
||||
<output name="reg_out" num_pins="1"/>
|
||||
<clock name="clk" num_pins="1"/>
|
||||
<pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop">
|
||||
<input name="D" num_pins="1" port_class="D"/>
|
||||
<output name="Q" num_pins="1" port_class="Q"/>
|
||||
<clock name="clk" num_pins="1" port_class="clock"/>
|
||||
<T_setup value="66e-12" port="ff.D" clock="clk"/>
|
||||
<T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
|
||||
</pb_type>
|
||||
<interconnect>
|
||||
<direct name="direct1" input="shift_reg.reg_in" output="ff.D"/>
|
||||
<direct name="direct3" input="ff.Q" output="shift_reg.reg_out"/>
|
||||
<direct name="direct4" input="ff.Q" output="shift_reg.ff_out"/>
|
||||
<complete name="complete1" input="shift_reg.clk" output="ff.clk"/>
|
||||
</interconnect>
|
||||
</pb_type>
|
||||
<interconnect>
|
||||
<direct name="direct1" input="fle.reg_in" output="shift_reg.reg_in"/>
|
||||
<direct name="direct2" input="shift_reg.reg_out" output="fle.reg_out"/>
|
||||
<direct name="direct3" input="shift_reg.ff_out" output="fle.out"/>
|
||||
<direct name="direct4" input="fle.clk" output="shift_reg.clk"/>
|
||||
</interconnect>
|
||||
</mode>
|
||||
<!-- Define shift register end -->
|
||||
</pb_type>
|
||||
<interconnect>
|
||||
<!-- We use direct connections to reduce the area to the most
|
||||
The global local routing is going to compensate the loss in routability
|
||||
-->
|
||||
<!-- FIXME: The implicit port definition results in I0[0] connected to
|
||||
in[2]. Such twisted connection is not expected.
|
||||
I[0] should be connected to in[0]
|
||||
-->
|
||||
<complete name="crossbar" input="clb.I fle[7:0].out" output="fle[7:0].in">
|
||||
<!-- TODO: Timing should be backannotated from post-PnR results -->
|
||||
</complete>
|
||||
<complete name="clks" input="clb.clk" output="fle[7:0].clk">
|
||||
</complete>
|
||||
<complete name="resets" input="clb.reset" output="fle[7:0].reset">
|
||||
</complete>
|
||||
<!-- This way of specifying direct connection to clb outputs is important because this architecture uses automatic spreading of opins.
|
||||
By grouping to output pins in this fashion, if a logic block is completely filled by 6-LUTs,
|
||||
then the outputs those 6-LUTs take get evenly distributed across all four sides of the CLB instead of clumped on two sides (which is what happens with a more
|
||||
naive specification).
|
||||
-->
|
||||
<direct name="clbouts1" input="fle[3:0].out" output="clb.O[3:0]"/>
|
||||
<direct name="clbouts2" input="fle[7:4].out" output="clb.O[7:4]"/>
|
||||
<!-- Shift register chain links -->
|
||||
<direct name="shift_register_in" input="clb.reg_in" output="fle[0:0].reg_in">
|
||||
<!-- Put all inter-block carry chain delay on this one edge -->
|
||||
<delay_constant max="0.16e-9" in_port="clb.reg_in" out_port="fle[0:0].reg_in"/>
|
||||
<!--pack_pattern name="chain" in_port="clb.reg_in" out_port="fle[0:0].reg_in"/-->
|
||||
</direct>
|
||||
<direct name="shift_register_out" input="fle[7:7].reg_out" output="clb.reg_out">
|
||||
<!--pack_pattern name="chain" in_port="fle[7:7].reg_out" out_port="clb.reg_out"/-->
|
||||
</direct>
|
||||
<direct name="shift_register_link" input="fle[6:0].reg_out" output="fle[7:1].reg_in">
|
||||
<!--pack_pattern name="chain" in_port="fle[6:0].reg_out" out_port="fle[7:1].reg_in"/-->
|
||||
</direct>
|
||||
<!-- Scan chain links -->
|
||||
<direct name="scan_chain_in" input="clb.sc_in" output="fle[0:0].sc_in">
|
||||
<!-- Put all inter-block carry chain delay on this one edge -->
|
||||
<delay_constant max="0.16e-9" in_port="clb.sc_in" out_port="fle[0:0].sc_in"/>
|
||||
</direct>
|
||||
<direct name="scan_chain_out" input="fle[7:7].sc_out" output="clb.sc_out">
|
||||
</direct>
|
||||
<direct name="scan_chain_link" input="fle[6:0].sc_out" output="fle[7:1].sc_in">
|
||||
</direct>
|
||||
<!-- Carry chain links -->
|
||||
<direct name="carry_chain_in" input="clb.cin" output="fle[0:0].cin">
|
||||
<!-- Put all inter-block carry chain delay on this one edge -->
|
||||
<delay_constant max="0.16e-9" in_port="clb.cin" out_port="fle[0:0].cin"/>
|
||||
</direct>
|
||||
<direct name="carry_chain_out" input="fle[7:7].cout" output="clb.cout">
|
||||
</direct>
|
||||
<direct name="carry_chain_link" input="fle[6:0].cout" output="fle[7:1].cin">
|
||||
</direct>
|
||||
</interconnect>
|
||||
<!-- Every input pin is driven by 15% of the tracks in a channel, every output pin is driven by 10% of the tracks in a channel -->
|
||||
<!-- Place this general purpose logic block in any unspecified column -->
|
||||
</pb_type>
|
||||
<!-- Define general purpose logic block (CLB) ends -->
|
||||
</complexblocklist>
|
||||
</architecture>
|
||||
|
|
@ -17,7 +17,7 @@ fpga_flow=yosys_vpr
|
|||
|
||||
[OpenFPGA_SHELL]
|
||||
openfpga_shell_template=${SKYWATER_OPENFPGA_HOME}/SCRIPT/openfpga_shell_script/skywater_generate_fabric_using_random_key_example_script.openfpga
|
||||
openfpga_arch_file=${SKYWATER_OPENFPGA_HOME}/ARCH/openfpga_arch/k4_frac_N8_reset_softadder_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml
|
||||
openfpga_arch_file=${SKYWATER_OPENFPGA_HOME}/ARCH/openfpga_arch/k4_N8_reset_softadder_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml
|
||||
openfpga_sim_setting_file=${SKYWATER_OPENFPGA_HOME}/SCRIPT/openfpga_simulation_setting/efpga_12x12_sim_openfpga.xml
|
||||
openfpga_vpr_device_layout=32x32
|
||||
openfpga_vpr_route_chan_width=60
|
||||
|
|
@ -26,7 +26,7 @@ openfpga_sdc_output_dir=${SKYWATER_OPENFPGA_HOME}/SDC/k4_N8_reset_softadder_cara
|
|||
external_fabric_key_file=${SKYWATER_OPENFPGA_HOME}/ARCH/fabric_key/fabric_key_12x12.xml
|
||||
|
||||
[ARCHITECTURES]
|
||||
arch0=${SKYWATER_OPENFPGA_HOME}/ARCH/vpr_arch/k4_frac_N8_tileable_reset_softadder_register_scan_chain_nonLR_caravel_io_skywater130nm.xml
|
||||
arch0=${SKYWATER_OPENFPGA_HOME}/ARCH/vpr_arch/k4_N8_tileable_reset_softadder_register_scan_chain_nonLR_caravel_io_skywater130nm.xml
|
||||
|
||||
[BENCHMARKS]
|
||||
bench0=${SKYWATER_OPENFPGA_HOME}/BENCHMARK/and2/and2.v
|
||||
|
|
|
|||
|
|
@ -17,7 +17,7 @@ fpga_flow=yosys_vpr
|
|||
|
||||
[OpenFPGA_SHELL]
|
||||
openfpga_shell_template=${SKYWATER_OPENFPGA_HOME}/SCRIPT/openfpga_shell_script/skywater_generate_sdc_using_random_key_example_script.openfpga
|
||||
openfpga_arch_file=${SKYWATER_OPENFPGA_HOME}/ARCH/openfpga_arch/k4_frac_N8_reset_softadder_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml
|
||||
openfpga_arch_file=${SKYWATER_OPENFPGA_HOME}/ARCH/openfpga_arch/k4_N8_reset_softadder_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml
|
||||
openfpga_sim_setting_file=${SKYWATER_OPENFPGA_HOME}/SCRIPT/openfpga_simulation_setting/efpga_12x12_sim_openfpga.xml
|
||||
openfpga_vpr_device_layout=32x32
|
||||
openfpga_vpr_route_chan_width=60
|
||||
|
|
@ -25,7 +25,7 @@ openfpga_sdc_output_dir=${SKYWATER_OPENFPGA_HOME}/SDC/k4_N8_reset_softadder_cara
|
|||
external_fabric_key_file=${SKYWATER_OPENFPGA_HOME}/ARCH/fabric_key/fabric_key_12x12.xml
|
||||
|
||||
[ARCHITECTURES]
|
||||
arch0=${SKYWATER_OPENFPGA_HOME}/ARCH/vpr_arch/k4_frac_N8_tileable_reset_softadder_register_scan_chain_nonLR_caravel_io_skywater130nm.xml
|
||||
arch0=${SKYWATER_OPENFPGA_HOME}/ARCH/vpr_arch/k4_N8_tileable_reset_softadder_register_scan_chain_nonLR_caravel_io_skywater130nm.xml
|
||||
|
||||
[BENCHMARKS]
|
||||
bench0=${SKYWATER_OPENFPGA_HOME}/BENCHMARK/and2/and2.v
|
||||
|
|
|
|||
|
|
@ -17,7 +17,7 @@ fpga_flow=yosys_vpr
|
|||
|
||||
[OpenFPGA_SHELL]
|
||||
openfpga_shell_template=${SKYWATER_OPENFPGA_HOME}/SCRIPT/openfpga_shell_script/skywater_generate_testbench_using_random_key_example_script.openfpga
|
||||
openfpga_arch_file=${SKYWATER_OPENFPGA_HOME}/ARCH/openfpga_arch/k4_frac_N8_reset_softadder_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml
|
||||
openfpga_arch_file=${SKYWATER_OPENFPGA_HOME}/ARCH/openfpga_arch/k4_N8_reset_softadder_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml
|
||||
openfpga_sim_setting_file=${SKYWATER_OPENFPGA_HOME}/SCRIPT/openfpga_simulation_setting/efpga_12x12_sim_openfpga.xml
|
||||
openfpga_vpr_device_layout=32x32
|
||||
openfpga_vpr_route_chan_width=60
|
||||
|
|
@ -26,7 +26,7 @@ openfpga_fabric_verilog_netlist=${SKYWATER_OPENFPGA_HOME}/HDL/k4_N8_reset_softad
|
|||
external_fabric_key_file=${SKYWATER_OPENFPGA_HOME}/ARCH/fabric_key/fabric_key_12x12.xml
|
||||
|
||||
[ARCHITECTURES]
|
||||
arch0=${SKYWATER_OPENFPGA_HOME}/ARCH/vpr_arch/k4_frac_N8_tileable_reset_softadder_register_scan_chain_nonLR_caravel_io_skywater130nm.xml
|
||||
arch0=${SKYWATER_OPENFPGA_HOME}/ARCH/vpr_arch/k4_N8_tileable_reset_softadder_register_scan_chain_nonLR_caravel_io_skywater130nm.xml
|
||||
|
||||
[BENCHMARKS]
|
||||
bench0=${SKYWATER_OPENFPGA_HOME}/BENCHMARK/and2/and2.v
|
||||
|
|
@ -43,7 +43,7 @@ bench9=${SKYWATER_OPENFPGA_HOME}/BENCHMARK/cf_fft_256_8/rtl/*.v
|
|||
bench10=${SKYWATER_OPENFPGA_HOME}/BENCHMARK/counter120bitx5/rtl/*.v
|
||||
bench11=${SKYWATER_OPENFPGA_HOME}/BENCHMARK/counter_16bit/rtl/*.v
|
||||
bench12=${SKYWATER_OPENFPGA_HOME}/BENCHMARK/dct_mac/rtl/*.v
|
||||
bench13=${SKYWATER_OPENFPGA_HOME}/BENCHMARK/des_perf/rtl/*.v
|
||||
#bench13=${SKYWATER_OPENFPGA_HOME}/BENCHMARK/des_perf/rtl/*.v
|
||||
bench14=${SKYWATER_OPENFPGA_HOME}/BENCHMARK/diffeq_f_systemC/rtl/*.v
|
||||
#bench15=${SKYWATER_OPENFPGA_HOME}/BENCHMARK/i2c_master_top/rtl/*.v
|
||||
bench16=${SKYWATER_OPENFPGA_HOME}/BENCHMARK/iir/rtl/*.v
|
||||
|
|
@ -68,7 +68,7 @@ bench9_top = cf_fft_256_8
|
|||
bench10_top = counter120bitx5
|
||||
bench11_top = top
|
||||
bench12_top = dct_mac
|
||||
bench13_top = des_perf
|
||||
#bench13_top = des_perf
|
||||
bench14_top = diffeq_f_systemC
|
||||
#bench15_top = i2c_master_top
|
||||
bench16_top = iir
|
||||
|
|
|
|||
Loading…
Reference in New Issue