tangxifan
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3d2f792fa5
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Merge pull request #59 from lnis-uofu/xt_dev
Now modelsim verification is multithreaded
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2020-12-07 18:53:42 -07:00 |
tangxifan
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77dfb469b5
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Update MSIM/common/run_post_pnr_msim_task.py
Co-authored-by: Ashton Snelgrove <ashton.snelgrove@utah.edu>
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2020-12-07 17:41:22 -07:00 |
tangxifan
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7f9c8e2e90
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[Doc] Add Readme for design compiler workspace
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2020-12-07 17:40:08 -07:00 |
tangxifan
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2f741ecc15
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[MSIM] Now modelsim verification is multithreaded
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2020-12-07 15:25:48 -07:00 |
Ganesh Gore
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0e691fe9ca
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[SOFA-HD] Updated reports and screenshots
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2020-12-07 11:55:59 -07:00 |
Ganesh Gore
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40f1e1fae1
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Merge remote-tracking branch 'origin/master' into ganesh_dev
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2020-12-07 10:14:56 -07:00 |
Laboratory for Nano Integrated Systems (LNIS)
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67e0c94c66
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Merge pull request #58 from lnis-uofu/xt_dev
Scripts for Verifications on Custom Cell -based FPGA (SOFA CHD)
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2020-12-07 09:45:43 -07:00 |
tangxifan
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fd074254e9
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Merge pull request #57 from lnis-uofu/ganesh_dev
Added Caravel merge and precheck in action + Updated SOFA-HD and QLSOFA-HD gds
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2020-12-07 09:07:30 -07:00 |
Ganesh Gore
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7967d1da1f
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[Bugfix] Solved merge conflict
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2020-12-06 23:13:59 -07:00 |
Ganesh Gore
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5474ff53c5
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[Fixup] Merge conflict with master
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2020-12-06 21:41:06 -07:00 |
Ganesh Gore
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b90ee124a3
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Resolves merge conflict with master
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2020-12-06 21:35:34 -07:00 |
Ganesh Gore
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b0098ed4b9
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Merge remote-tracking branch 'origin/master' into ganesh_dev
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2020-12-06 21:29:06 -07:00 |
Ganesh Gore
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5679ee0cb4
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[QLSOFA-HD] Fixed reset signal short/GDS precision to 1000
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2020-12-06 20:47:52 -07:00 |
Ganesh Gore
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12ffaed8fa
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[QLSOFA-HD] Added screenshots for top level PnR
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2020-12-06 20:45:31 -07:00 |
tangxifan
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7f53e0ef18
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[HDL] Add HDL for custom cells
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2020-12-06 14:15:03 -07:00 |
tangxifan
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aa90424ada
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[HDL] Add primitive include lines for digital I/O built with HD cells
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2020-12-06 11:35:35 -07:00 |
tangxifan
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21a4928002
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[HDL] Bug fix in custom cell code generator
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2020-12-06 11:28:37 -07:00 |
tangxifan
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da08e505b5
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[MSIM] Support pre-pnr simulation in script-run verification
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2020-12-06 11:13:50 -07:00 |
Ganesh Gore
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328594d8c5
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[Action] Clean up action scripts
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2020-12-06 01:53:21 -07:00 |
Ganesh Gore
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9322afadad
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[Action] Added 30 min timeout ticker
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2020-12-06 01:42:07 -07:00 |
Ganesh Gore
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ea7e2b248b
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[Action] Testing Docker action
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2020-12-06 01:41:58 -07:00 |
Ganesh Gore
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10cab93799
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[Action] Integrated MPW prechecker
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2020-12-06 01:41:58 -07:00 |
Ganesh Gore
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40c131983a
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[FPGA1212_v1] Changed gds precision to 1000
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2020-12-06 01:41:58 -07:00 |
Ganesh Gore
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6af001df11
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Added SynRepoConfig is paths
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2020-12-06 01:41:58 -07:00 |
Ganesh Gore
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2bada6124f
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[Action] Changed Docker workdir
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2020-12-06 01:41:46 -07:00 |
Ganesh Gore
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cfa2bb96c4
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[Action] Removed nojekyll file addition
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2020-12-06 01:41:46 -07:00 |
Ganesh Gore
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51cd5d6630
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[Action] Added Docker itegration
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2020-12-06 01:41:36 -07:00 |
Ganesh Gore
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60060762e5
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[Action] Replaced destination repo url
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2020-12-06 01:41:00 -07:00 |
Ganesh Gore
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2ecc166e95
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[Action] Added destination repo push action
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2020-12-06 01:40:38 -07:00 |
Ganesh Gore
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8105a46f07
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[Actions] Alternate option to modify file
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2020-12-06 01:40:21 -07:00 |
Ganesh Gore
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d63dfa00b7
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[Actions] filename bugfix
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2020-12-06 01:40:21 -07:00 |
Ganesh Gore
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027f0f76a2
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[bugfix] Indentation bug in actions yaml
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2020-12-06 01:40:21 -07:00 |
Ganesh Gore
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41f2844698
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[Action] And modify file and push action
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2020-12-06 01:40:21 -07:00 |
Ganesh Gore
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62e0cffea1
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[Actions] Disables build test in ganesh_dev branch
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2020-12-06 01:40:21 -07:00 |
Ganesh Gore
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d5a5ec5b1d
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[Actions] Testing repository fetch option
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2020-12-06 01:40:21 -07:00 |
Ganesh Gore
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452af85e98
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[Cleanup] Removed/Ignored testbench files from generated source
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2020-12-06 01:40:21 -07:00 |
tangxifan
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f5c1d9c0a0
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[Arch] enable local encoders
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2020-12-06 01:40:21 -07:00 |
tangxifan
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ad120e205b
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[CI] Add new arch to CI test
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2020-12-06 01:40:21 -07:00 |
tangxifan
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004f9dbcca
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[Arch] Bug fix in new arch
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2020-12-06 01:40:21 -07:00 |
tangxifan
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c015d65a03
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[Script] Add task run for custom cell FPGA architectures
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2020-12-06 01:40:21 -07:00 |
tangxifan
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4ddc6955a3
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[Arch] Add architecture using custom cells
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2020-12-06 01:40:21 -07:00 |
tangxifan
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22451870dd
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[CI] Patch github repo path to sync with OpenFPGA repo movement
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2020-12-06 01:39:16 -07:00 |
tangxifan
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87f79d78bb
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[CI] Add wrapper generator examples to CI
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2020-12-06 01:39:16 -07:00 |
tangxifan
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696529b43d
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[Script] Increase routing chan width from 40 to 60 for version 1.2
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2020-12-06 01:39:16 -07:00 |
Laboratory for Nano Integrated Systems (LNIS)
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f572be8fc2
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Merge pull request #56 from lnis-uofu/xt_dev
Python script to adapt OpenFPGA netlist to use custom MUX cells
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2020-12-05 22:11:36 -07:00 |
tangxifan
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443eb12710
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[CI] Add test to CI
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2020-12-05 21:17:59 -07:00 |
tangxifan
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22f2b3aa90
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[HDL] Add python script to adapt OpenFPGA MUX primitives to use custom cells
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2020-12-05 21:14:56 -07:00 |
tangxifan
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6039ae92ca
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[Arch] Bug fix for buffering two-level routing multiplexers using custom cells
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2020-12-05 19:37:34 -07:00 |
Laboratory for Nano Integrated Systems (LNIS)
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52413059f6
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Merge pull request #55 from lnis-uofu/xt_dev
Major Changes in Documentation
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2020-12-04 14:47:52 -07:00 |
tangxifan
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3a75e079ba
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[Doc] Update the frontpage README
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2020-12-04 14:09:40 -07:00 |