[SOFA-HD] Updated reports and screenshots
Ganesh Gore
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BIN
FPGA1212_FLAT_HD_SKY_PNR/fpga_top/fpga_top_icv_in_design.nominal_25.spef (Stored with Git LFS)
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@ -0,0 +1,18 @@
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| Module | Util| Area| Sites| Insts| Std_Cells
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|--------------------|----------|-----------------|-------|-------|-------
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|fpga_core_uut/sb_0__0_ | 31.45 | 8728.371200 | 6976 | 1 | 868
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|fpga_core_uut/sb_0__11_ | 47.54 | 9449.062400 | 7552 | 11 | 945
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|fpga_core_uut/sb_0__12_ | 31.62 | 8728.371200 | 6976 | 1 | 865
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|fpga_core_uut/sb_11__0_ | 47.53 | 10970.521600 | 8768 | 11 | 1033
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|fpga_core_uut/sb_11__11_ | 64.3 | 11691.212800 | 9344 | 121 | 999
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|fpga_core_uut/sb_11__12_ | 47.15 | 10970.521600 | 8768 | 11 | 1021
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|fpga_core_uut/sb_12__0_ | 42.63 | 8728.371200 | 6976 | 1 | 827
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|fpga_core_uut/sb_12__11_ | 54.85 | 9449.062400 | 7552 | 11 | 931
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|fpga_core_uut/sb_12__12_ | 43.81 | 8728.371200 | 6976 | 1 | 823
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|fpga_core_uut/cbx_12__0_ | 63.67 | 5765.529600 | 4608 | 12 | 558
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|fpga_core_uut/cbx_12__11_ | 78.43 | 5765.529600 | 4608 | 132 | 372
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|fpga_core_uut/cbx_12__12_ | 77.47 | 5765.529600 | 4608 | 12 | 366
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|fpga_core_uut/cby_0__12_ | 20.51 | 5044.838400 | 4032 | 12 | 556
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|fpga_core_uut/cby_11__12_ | 82.22 | 5044.838400 | 4032 | 132 | 291
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|fpga_core_uut/cby_12__12_ | 83.28 | 5044.838400 | 4032 | 12 | 267
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|fpga_core_uut/grid_clb_12__12_ | 77.94 | 11531.059200 | 9216 | 144 | 597
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Ref Name Total Area Utilization_% Instance Count
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----------------------------------------------------------------------------------------------------
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sky130_fd_sc_hd__dfxtp_4 1330730.025600 12.95 55977
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sky130_fd_sc_hd__mux2_1 1314450.662400 12.79 116728
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sky130_fd_sc_hd__buf_8 304882.406400 2.97 20306
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sky130_fd_sc_hd__dfxtp_1 237007.308800 2.31 11839
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sky130_fd_sc_hd__buf_6 156502.598400 1.52 13898
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sky130_fd_sc_hd__dlygate4sd3_1 71628.697600 0.70 7156
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sky130_fd_sc_hd__buf_1 71340.921600 0.69 19006
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sky130_fd_sc_hd__sdfxtp_1 60538.060800 0.59 2304
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sky130_fd_sc_hd__inv_8 44953.113600 0.44 3992
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sky130_fd_sc_hd__bufbuf_16 43331.558400 0.42 1332
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sky130_fd_sc_hd__inv_1 40520.112000 0.39 10795
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sky130_fd_sc_hd__conb_1 23561.347200 0.23 6277
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sky130_fd_sc_hd__buf_4 10089.676800 0.10 1344
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sky130_fd_sc_hd__mux2_8 7567.257600 0.07 288
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sky130_fd_sc_hd__or2_0 7206.912000 0.07 1152
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sky130_fd_sc_hd__ebufn_4 5758.022400 0.06 354
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sky130_fd_sc_hd__buf_12 5525.299200 0.05 276
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sky130_fd_sc_hd__inv_6 4195.273600 0.04 479
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sky130_fd_sc_hd__clkbuf_1 3828.672000 0.04 1020
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sky130_fd_sc_hd__dfxtp_2 3062.937600 0.03 144
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sky130_fd_sc_hd__bufbuf_8 2477.376000 0.02 132
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sky130_fd_sc_hd__buf_2 2342.246400 0.02 468
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sky130_fd_sc_hd__inv_2 2207.116800 0.02 588
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sky130_fd_sc_hd__dlygate4sd2_1 1366.310400 0.01 156
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sky130_fd_sc_hd__nand2b_1 825.792000 0.01 132
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sky130_fd_sc_hd__inv_4 675.648000 0.01 108
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sky130_fd_sc_hd__buf_16 330.316800 0.00 12
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sky130_fd_sc_hd__dlygate4sd1_1 324.060800 0.00 37
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sky130_fd_sc_hd__clkbuf_8 165.158400 0.00 12
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sky130_fd_sc_hd__or2b_4 135.129600 0.00 12
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FPGA_BBOX_AREA 5973088.6656
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CORE_BBOX_AREA 10276128.1216
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FPGA_BBOX_UTIL 58.1258679818
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Can't render this file because it has a wrong number of fields in line 2.
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@ -0,0 +1,75 @@
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****************************************
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Report : clock timing
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-type latency
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-launch
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-nworst 1
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-setup
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Design : fpga_top
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Version: P-2019.03-SP4
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Date : Mon Dec 7 11:48:29 2020
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****************************************
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Information: Timer using 'PrimeTime Delay Calculation, AWP'. (TIM-050)
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Mode: full_chip
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Clock: PROG_CLK
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--- Latency ---
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Clock Pin Trans Source Offset Network Total Corner
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---------------------------------------------------------------------------------------------------
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fpga_core_uut/sb_11__1_/mem_bottom_track_1/sky130_fd_sc_hd__dfxtp_1_0_/CLK 4.283 0.000 -- 9.187 9.187 rp-+ nominal
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---------------------------------------------------------------------------------------------------
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Mode: full_chip
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Clock: CLK
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--- Latency ---
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Clock Pin Trans Source Offset Network Total Corner
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---------------------------------------------------------------------------------------------------
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fpga_core_uut/grid_clb_11__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1/sky130_fd_sc_hd__sdfxtp_1_0_/CLK 0.625 0.000 -- 6.546 6.546 rp-+ nominal
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---------------------------------------------------------------------------------------------------
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****************************************
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Report : clock timing
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-type skew
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-nworst 1
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-setup
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Design : fpga_top
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Version: P-2019.03-SP4
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Date : Mon Dec 7 11:48:29 2020
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****************************************
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Information: Timer using 'PrimeTime Delay Calculation, AWP'. (TIM-050)
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Mode: full_chip
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Clock: PROG_CLK
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Clock Pin Latency Skew Corner
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---------------------------------------------------------------------------------------------------
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fpga_core_uut/sb_10__5_/mem_left_track_33/sky130_fd_sc_hd__dfxtp_1_2_/CLK 7.995 rp-+ nominal
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fpga_core_uut/cbx_10__5_/mem_top_ipin_0/sky130_fd_sc_hd__dfxtp_1_0_/CLK 5.257 2.737 rp-+ nominal
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---------------------------------------------------------------------------------------------------
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Mode: full_chip
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Clock: CLK
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Clock Pin Latency Skew Corner
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---------------------------------------------------------------------------------------------------
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fpga_core_uut/grid_clb_8__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1/sky130_fd_sc_hd__sdfxtp_1_0_/CLK 5.962 rp-+ nominal
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fpga_core_uut/grid_clb_8__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0/sky130_fd_sc_hd__sdfxtp_1_0_/CLK 5.241 0.721 rp-+ nominal
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---------------------------------------------------------------------------------------------------
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Information: Timer using 'PrimeTime Delay Calculation, AWP'. (TIM-050)
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****************************************
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Report : global timing
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-format { narrow }
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Design : fpga_top
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Version: P-2019.03-SP4
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Date : Mon Dec 7 11:48:31 2020
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****************************************
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No setup violations found.
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No hold violations found.
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1
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