diff --git a/FPGA1212_FLAT_HD_SKY_PNR/fpga_top/Screenshots/ConfigFlipFLop.png b/FPGA1212_FLAT_HD_SKY_PNR/fpga_top/Screenshots/ConfigFlipFLop.png index 9b2c176..eeb9b77 100644 Binary files a/FPGA1212_FLAT_HD_SKY_PNR/fpga_top/Screenshots/ConfigFlipFLop.png and b/FPGA1212_FLAT_HD_SKY_PNR/fpga_top/Screenshots/ConfigFlipFLop.png differ diff --git a/FPGA1212_FLAT_HD_SKY_PNR/fpga_top/Screenshots/ConfigurationChain.png b/FPGA1212_FLAT_HD_SKY_PNR/fpga_top/Screenshots/ConfigurationChain.png index 2af31ec..b7873a7 100644 Binary files a/FPGA1212_FLAT_HD_SKY_PNR/fpga_top/Screenshots/ConfigurationChain.png and b/FPGA1212_FLAT_HD_SKY_PNR/fpga_top/Screenshots/ConfigurationChain.png differ diff --git a/FPGA1212_FLAT_HD_SKY_PNR/fpga_top/Screenshots/ProgClockTree.png b/FPGA1212_FLAT_HD_SKY_PNR/fpga_top/Screenshots/ProgClockTree.png index c3a1e95..081c547 100644 Binary files a/FPGA1212_FLAT_HD_SKY_PNR/fpga_top/Screenshots/ProgClockTree.png and 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a/FPGA1212_FLAT_HD_SKY_PNR/fpga_top/Screenshots/power_contacts.png and b/FPGA1212_FLAT_HD_SKY_PNR/fpga_top/Screenshots/power_contacts.png differ diff --git a/FPGA1212_FLAT_HD_SKY_PNR/fpga_top/Screenshots/utilization.png b/FPGA1212_FLAT_HD_SKY_PNR/fpga_top/Screenshots/utilization.png index 6c12aae..2d99cd7 100644 Binary files a/FPGA1212_FLAT_HD_SKY_PNR/fpga_top/Screenshots/utilization.png and b/FPGA1212_FLAT_HD_SKY_PNR/fpga_top/Screenshots/utilization.png differ diff --git a/FPGA1212_FLAT_HD_SKY_PNR/fpga_top/fpga_top_icv_in_design.nominal_25.spef b/FPGA1212_FLAT_HD_SKY_PNR/fpga_top/fpga_top_icv_in_design.nominal_25.spef index 824f5ee..4819793 100644 --- a/FPGA1212_FLAT_HD_SKY_PNR/fpga_top/fpga_top_icv_in_design.nominal_25.spef +++ b/FPGA1212_FLAT_HD_SKY_PNR/fpga_top/fpga_top_icv_in_design.nominal_25.spef @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:dbd17e4ac23d211dc77c7055739dc4fc454a3e15a5e2e1697d57c64a02b0628b +oid sha256:3090ec753012c0eb7b9add66be2d98ddf2a367909aad8ab02c16961d71c8102f size 28278825 diff --git a/FPGA1212_FLAT_HD_SKY_PNR/fpga_top/rpts_icc2/module_utilization.tsv b/FPGA1212_FLAT_HD_SKY_PNR/fpga_top/rpts_icc2/module_utilization.tsv new file mode 100644 index 0000000..04f192d --- /dev/null +++ b/FPGA1212_FLAT_HD_SKY_PNR/fpga_top/rpts_icc2/module_utilization.tsv @@ -0,0 +1,18 @@ +| Module | Util| Area| Sites| Insts| Std_Cells +|--------------------|----------|-----------------|-------|-------|------- +|fpga_core_uut/sb_0__0_ | 31.45 | 8728.371200 | 6976 | 1 | 868 +|fpga_core_uut/sb_0__11_ | 47.54 | 9449.062400 | 7552 | 11 | 945 +|fpga_core_uut/sb_0__12_ | 31.62 | 8728.371200 | 6976 | 1 | 865 +|fpga_core_uut/sb_11__0_ | 47.53 | 10970.521600 | 8768 | 11 | 1033 +|fpga_core_uut/sb_11__11_ | 64.3 | 11691.212800 | 9344 | 121 | 999 +|fpga_core_uut/sb_11__12_ | 47.15 | 10970.521600 | 8768 | 11 | 1021 +|fpga_core_uut/sb_12__0_ | 42.63 | 8728.371200 | 6976 | 1 | 827 +|fpga_core_uut/sb_12__11_ | 54.85 | 9449.062400 | 7552 | 11 | 931 +|fpga_core_uut/sb_12__12_ | 43.81 | 8728.371200 | 6976 | 1 | 823 +|fpga_core_uut/cbx_12__0_ | 63.67 | 5765.529600 | 4608 | 12 | 558 +|fpga_core_uut/cbx_12__11_ | 78.43 | 5765.529600 | 4608 | 132 | 372 +|fpga_core_uut/cbx_12__12_ | 77.47 | 5765.529600 | 4608 | 12 | 366 +|fpga_core_uut/cby_0__12_ | 20.51 | 5044.838400 | 4032 | 12 | 556 +|fpga_core_uut/cby_11__12_ | 82.22 | 5044.838400 | 4032 | 132 | 291 +|fpga_core_uut/cby_12__12_ | 83.28 | 5044.838400 | 4032 | 12 | 267 +|fpga_core_uut/grid_clb_12__12_ | 77.94 | 11531.059200 | 9216 | 144 | 597 diff --git a/FPGA1212_FLAT_HD_SKY_PNR/fpga_top/rpts_icc2/std_cell_utilization.tsv b/FPGA1212_FLAT_HD_SKY_PNR/fpga_top/rpts_icc2/std_cell_utilization.tsv new file mode 100644 index 0000000..6160f4f --- /dev/null +++ b/FPGA1212_FLAT_HD_SKY_PNR/fpga_top/rpts_icc2/std_cell_utilization.tsv @@ -0,0 +1,35 @@ + Ref Name Total Area Utilization_% Instance Count + ---------------------------------------------------------------------------------------------------- + sky130_fd_sc_hd__dfxtp_4 1330730.025600 12.95 55977 + sky130_fd_sc_hd__mux2_1 1314450.662400 12.79 116728 + sky130_fd_sc_hd__buf_8 304882.406400 2.97 20306 + sky130_fd_sc_hd__dfxtp_1 237007.308800 2.31 11839 + sky130_fd_sc_hd__buf_6 156502.598400 1.52 13898 + sky130_fd_sc_hd__dlygate4sd3_1 71628.697600 0.70 7156 + sky130_fd_sc_hd__buf_1 71340.921600 0.69 19006 + sky130_fd_sc_hd__sdfxtp_1 60538.060800 0.59 2304 + sky130_fd_sc_hd__inv_8 44953.113600 0.44 3992 + sky130_fd_sc_hd__bufbuf_16 43331.558400 0.42 1332 + sky130_fd_sc_hd__inv_1 40520.112000 0.39 10795 + sky130_fd_sc_hd__conb_1 23561.347200 0.23 6277 + sky130_fd_sc_hd__buf_4 10089.676800 0.10 1344 + sky130_fd_sc_hd__mux2_8 7567.257600 0.07 288 + sky130_fd_sc_hd__or2_0 7206.912000 0.07 1152 + sky130_fd_sc_hd__ebufn_4 5758.022400 0.06 354 + sky130_fd_sc_hd__buf_12 5525.299200 0.05 276 + sky130_fd_sc_hd__inv_6 4195.273600 0.04 479 + sky130_fd_sc_hd__clkbuf_1 3828.672000 0.04 1020 + sky130_fd_sc_hd__dfxtp_2 3062.937600 0.03 144 + sky130_fd_sc_hd__bufbuf_8 2477.376000 0.02 132 + sky130_fd_sc_hd__buf_2 2342.246400 0.02 468 + sky130_fd_sc_hd__inv_2 2207.116800 0.02 588 + sky130_fd_sc_hd__dlygate4sd2_1 1366.310400 0.01 156 + sky130_fd_sc_hd__nand2b_1 825.792000 0.01 132 + sky130_fd_sc_hd__inv_4 675.648000 0.01 108 + sky130_fd_sc_hd__buf_16 330.316800 0.00 12 + sky130_fd_sc_hd__dlygate4sd1_1 324.060800 0.00 37 + sky130_fd_sc_hd__clkbuf_8 165.158400 0.00 12 + sky130_fd_sc_hd__or2b_4 135.129600 0.00 12 +FPGA_BBOX_AREA 5973088.6656 +CORE_BBOX_AREA 10276128.1216 +FPGA_BBOX_UTIL 58.1258679818 diff --git a/FPGA1212_FLAT_HD_SKY_PNR/fpga_top/rpts_icc2/timing_reports.txt b/FPGA1212_FLAT_HD_SKY_PNR/fpga_top/rpts_icc2/timing_reports.txt new file mode 100644 index 0000000..8bb06fd --- /dev/null +++ b/FPGA1212_FLAT_HD_SKY_PNR/fpga_top/rpts_icc2/timing_reports.txt @@ -0,0 +1,75 @@ +**************************************** +Report : clock timing + -type latency + -launch + -nworst 1 + -setup +Design : fpga_top +Version: P-2019.03-SP4 +Date : Mon Dec 7 11:48:29 2020 +**************************************** +Information: Timer using 'PrimeTime Delay Calculation, AWP'. (TIM-050) + + Mode: full_chip + Clock: PROG_CLK + + --- Latency --- + Clock Pin Trans Source Offset Network Total Corner +--------------------------------------------------------------------------------------------------- + fpga_core_uut/sb_11__1_/mem_bottom_track_1/sky130_fd_sc_hd__dfxtp_1_0_/CLK 4.283 0.000 -- 9.187 9.187 rp-+ nominal +--------------------------------------------------------------------------------------------------- + + Mode: full_chip + Clock: CLK + + --- Latency --- + Clock Pin Trans Source Offset Network Total Corner +--------------------------------------------------------------------------------------------------- + fpga_core_uut/grid_clb_11__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1/sky130_fd_sc_hd__sdfxtp_1_0_/CLK 0.625 0.000 -- 6.546 6.546 rp-+ nominal +--------------------------------------------------------------------------------------------------- +**************************************** +Report : clock timing + -type skew + -nworst 1 + -setup +Design : fpga_top +Version: P-2019.03-SP4 +Date : Mon Dec 7 11:48:29 2020 +**************************************** +Information: Timer using 'PrimeTime Delay Calculation, AWP'. (TIM-050) + + Mode: full_chip + Clock: PROG_CLK + + Clock Pin Latency Skew Corner +--------------------------------------------------------------------------------------------------- + fpga_core_uut/sb_10__5_/mem_left_track_33/sky130_fd_sc_hd__dfxtp_1_2_/CLK 7.995 rp-+ nominal + fpga_core_uut/cbx_10__5_/mem_top_ipin_0/sky130_fd_sc_hd__dfxtp_1_0_/CLK 5.257 2.737 rp-+ nominal + +--------------------------------------------------------------------------------------------------- + + Mode: full_chip + Clock: CLK + + Clock Pin Latency Skew Corner +--------------------------------------------------------------------------------------------------- + fpga_core_uut/grid_clb_8__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1/sky130_fd_sc_hd__sdfxtp_1_0_/CLK 5.962 rp-+ nominal + fpga_core_uut/grid_clb_8__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0/sky130_fd_sc_hd__sdfxtp_1_0_/CLK 5.241 0.721 rp-+ nominal + +--------------------------------------------------------------------------------------------------- +Information: Timer using 'PrimeTime Delay Calculation, AWP'. (TIM-050) +**************************************** +Report : global timing + -format { narrow } +Design : fpga_top +Version: P-2019.03-SP4 +Date : Mon Dec 7 11:48:31 2020 +**************************************** + +No setup violations found. + + +No hold violations found. + + +1