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[Cleanup] Removed/Ignored testbench files from generated source

This commit is contained in:
Ganesh Gore 2020-12-02 12:03:24 -07:00
parent f5c1d9c0a0
commit 452af85e98
7 changed files with 1 additions and 150607 deletions
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1
.gitignore vendored
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@ -7,3 +7,4 @@
**/*_Verilog/SRC_Skeleton
**/*_Verilog/SRCBackup
**/DOC/build
**/SRC**/*_tb.v

68509
FPGA1212_FLAT_HD_SKY_PNR/FPGA1212_FLAT_HD_SKY_Verilog/SRC/top_autocheck_top_tb.v
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126
FPGA1212_FLAT_HD_SKY_PNR/FPGA1212_FLAT_HD_SKY_Verilog/SRC/top_formal_random_top_tb.v
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@ -1,126 +0,0 @@
//
//
//
//
//
//
//
//
`timescale 1ns / 1ps
module top_top_formal_verification_random_tb;
//
reg [0:0] clk;
//
reg [0:0] a;
reg [0:0] b;
//
wire [0:0] out:c_gfpga;
`ifdef AUTOCHECKED_SIMULATION
//
wire [0:0] out:c_bench;
//
reg [0:0] out:c_flag;
`endif
//
integer nb_error= 0;
//
top_top_formal_verification FPGA_DUT(
.a_fm(a),
.b_fm(b),
.out:c_fm(out:c_gfpga) );
//
`ifdef AUTOCHECKED_SIMULATION
//
top REF_DUT(
.a(a),
.b(b),
.c(out:c_bench) );
//
`endif
//
initial begin
clk[0] <= 1'b0;
while(1) begin
#0.5551859605
clk[0] <= !clk[0];
end
end
//
initial begin
a <= 1'b0;
b <= 1'b0;
out:c_flag[0] <= 1'b0;
end
//
always@(negedge clk[0]) begin
a <= $random;
b <= $random;
end
`ifdef AUTOCHECKED_SIMULATION
//
//
reg [0:0] sim_start;
always@(negedge clk[0]) begin
if (1'b1 == sim_start[0]) begin
sim_start[0] <= ~sim_start[0];
end else begin
if(!(out:c_gfpga === out:c_bench) && !(out:c_bench === 1'bx)) begin
out:c_flag <= 1'b1;
end else begin
out:c_flag<= 1'b0;
end
end
end
always@(posedge out:c_flag) begin
if(out:c_flag) begin
nb_error = nb_error + 1;
$display("Mismatch on out:c_gfpga at time = %t", $realtime);
end
end
`endif
`ifdef ICARUS_SIMULATOR
//
initial begin
$dumpfile("top_formal.vcd");
$dumpvars(1, top_top_formal_verification_random_tb);
end
`endif
//
initial begin
sim_start[0] <= 1'b1;
$timeformat(-9, 2, "ns", 20);
$display("Simulation start");
//
#444
if(nb_error == 0) begin
$display("Simulation Succeed");
end else begin
$display("Simulation Failed with %d error(s)", nb_error);
end
$finish;
end
endmodule
//

79320
FPGA1212_RESET_HD_SKY_PNR/FPGA1212_RESET_HD_SKY_Verilog/SRC/top_autocheck_top_tb.v
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126
FPGA1212_RESET_HD_SKY_PNR/FPGA1212_RESET_HD_SKY_Verilog/SRC/top_formal_random_top_tb.v
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@ -1,126 +0,0 @@
//
//
//
//
//
//
//
//
`timescale 1ns / 1ps
module top_top_formal_verification_random_tb;
//
reg [0:0] clk;
//
reg [0:0] a;
reg [0:0] b;
//
wire [0:0] out:c_gfpga;
`ifdef AUTOCHECKED_SIMULATION
//
wire [0:0] out:c_bench;
//
reg [0:0] out:c_flag;
`endif
//
integer nb_error= 0;
//
top_top_formal_verification FPGA_DUT(
.a_fm(a),
.b_fm(b),
.out:c_fm(out:c_gfpga) );
//
`ifdef AUTOCHECKED_SIMULATION
//
top REF_DUT(
.a(a),
.b(b),
.c(out:c_bench) );
//
`endif
//
initial begin
clk[0] <= 1'b0;
while(1) begin
#0.4159859701
clk[0] <= !clk[0];
end
end
//
initial begin
a <= 1'b0;
b <= 1'b0;
out:c_flag[0] <= 1'b0;
end
//
always@(negedge clk[0]) begin
a <= $random;
b <= $random;
end
`ifdef AUTOCHECKED_SIMULATION
//
//
reg [0:0] sim_start;
always@(negedge clk[0]) begin
if (1'b1 == sim_start[0]) begin
sim_start[0] <= ~sim_start[0];
end else begin
if(!(out:c_gfpga === out:c_bench) && !(out:c_bench === 1'bx)) begin
out:c_flag <= 1'b1;
end else begin
out:c_flag<= 1'b0;
end
end
end
always@(posedge out:c_flag) begin
if(out:c_flag) begin
nb_error = nb_error + 1;
$display("Mismatch on out:c_gfpga at time = %t", $realtime);
end
end
`endif
`ifdef ICARUS_SIMULATOR
//
initial begin
$dumpfile("top_formal.vcd");
$dumpvars(1, top_top_formal_verification_random_tb);
end
`endif
//
initial begin
sim_start[0] <= 1'b1;
$timeformat(-9, 2, "ns", 20);
$display("Simulation start");
//
#332
if(nb_error == 0) begin
$display("Simulation Succeed");
end else begin
$display("Simulation Failed with %d error(s)", nb_error);
end
$finish;
end
endmodule
//

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FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/top_autocheck_top_tb.v
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126
FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/top_formal_random_top_tb.v
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@ -1,126 +0,0 @@
//
//
//
//
//
//
//
//
`timescale 1ns / 1ps
module top_top_formal_verification_random_tb;
//
reg [0:0] clk;
//
reg [0:0] a;
reg [0:0] b;
//
wire [0:0] out:c_gfpga;
`ifdef AUTOCHECKED_SIMULATION
//
wire [0:0] out:c_bench;
//
reg [0:0] out:c_flag;
`endif
//
integer nb_error= 0;
//
top_top_formal_verification FPGA_DUT(
.a_fm(a),
.b_fm(b),
.out:c_fm(out:c_gfpga) );
//
`ifdef AUTOCHECKED_SIMULATION
//
top REF_DUT(
.a(a),
.b(b),
.c(out:c_bench) );
//
`endif
//
initial begin
clk[0] <= 1'b0;
while(1) begin
#0.5203860242
clk[0] <= !clk[0];
end
end
//
initial begin
a <= 1'b0;
b <= 1'b0;
out:c_flag[0] <= 1'b0;
end
//
always@(negedge clk[0]) begin
a <= $random;
b <= $random;
end
`ifdef AUTOCHECKED_SIMULATION
//
//
reg [0:0] sim_start;
always@(negedge clk[0]) begin
if (1'b1 == sim_start[0]) begin
sim_start[0] <= ~sim_start[0];
end else begin
if(!(out:c_gfpga === out:c_bench) && !(out:c_bench === 1'bx)) begin
out:c_flag <= 1'b1;
end else begin
out:c_flag<= 1'b0;
end
end
end
always@(posedge out:c_flag) begin
if(out:c_flag) begin
nb_error = nb_error + 1;
$display("Mismatch on out:c_gfpga at time = %t", $realtime);
end
end
`endif
`ifdef ICARUS_SIMULATOR
//
initial begin
$dumpfile("top_formal.vcd");
$dumpvars(1, top_top_formal_verification_random_tb);
end
`endif
//
initial begin
sim_start[0] <= 1'b1;
$timeformat(-9, 2, "ns", 20);
$display("Simulation start");
//
#416
if(nb_error == 0) begin
$display("Simulation Succeed");
end else begin
$display("Simulation Failed with %d error(s)", nb_error);
end
$finish;
end
endmodule
//