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[HDL] Add primitive include lines for digital I/O built with HD cells

This commit is contained in:
tangxifan 2020-12-06 11:35:35 -07:00
parent 21a4928002
commit aa90424ada
1 changed files with 6 additions and 0 deletions
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HDL/common/digital_io_hd_primitives.v Normal file
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`timescale 1ns/1ps
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/or2b/sky130_fd_sc_hd__or2b_4.v"
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/inv/sky130_fd_sc_hd__inv_1.v"
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/ebufn/sky130_fd_sc_hd__ebufn_4.v"