From aa90424adacee891357aa76371fd0ce3bae9bee1 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Sun, 6 Dec 2020 11:35:35 -0700 Subject: [PATCH] [HDL] Add primitive include lines for digital I/O built with HD cells --- HDL/common/digital_io_hd_primitives.v | 6 ++++++ 1 file changed, 6 insertions(+) create mode 100644 HDL/common/digital_io_hd_primitives.v diff --git a/HDL/common/digital_io_hd_primitives.v b/HDL/common/digital_io_hd_primitives.v new file mode 100644 index 0000000..5e387e4 --- /dev/null +++ b/HDL/common/digital_io_hd_primitives.v @@ -0,0 +1,6 @@ +`timescale 1ns/1ps + +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/or2b/sky130_fd_sc_hd__or2b_4.v" +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/inv/sky130_fd_sc_hd__inv_1.v" +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/ebufn/sky130_fd_sc_hd__ebufn_4.v" +