tangxifan
|
a5055e9d26
|
add support about loading external fabric key
|
2020-06-12 13:03:11 -06:00 |
|
tangxifan
|
9dbf536306
|
add shuffled configurable children support for top module
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2020-06-12 11:16:53 -06:00 |
|
tangxifan
|
cf9c3b0f44
|
add write fabric to test cases
|
2020-06-12 10:50:23 -06:00 |
|
tangxifan
|
3499b4d3e7
|
add fabric key writer for top-level module
|
2020-06-12 10:41:34 -06:00 |
|
tangxifan
|
278acee216
|
bug fix for 'build_fabric' command
|
2020-06-11 23:59:24 -06:00 |
|
tangxifan
|
9167b288b6
|
add options for fabric key
|
2020-06-11 21:50:46 -06:00 |
|
tangxifan
|
8a4ec85c39
|
add configurable children-related methods to module manager
|
2020-06-11 21:44:25 -06:00 |
|
tangxifan
|
58807bfcb3
|
remove simulation settings from openfpga arch data structure
|
2020-06-11 19:31:16 -06:00 |
|
tangxifan
|
96b58dfdbb
|
use new simulation setting command in openfpga shell
|
2020-06-11 19:31:15 -06:00 |
|
tangxifan
|
4a2f6dfae2
|
add read/write simulation setting commands to openfpga shell
|
2020-06-11 19:31:15 -06:00 |
|
tangxifan
|
3c10af7f2b
|
bug fixed in memory bank configuration protocol which is due to the wrong Verilog port merging algorithm
|
2020-06-11 19:31:14 -06:00 |
|
tangxifan
|
8267dad8ef
|
add decoder support for Z signals
|
2020-06-11 19:31:14 -06:00 |
|
tangxifan
|
5368485bd6
|
keep bug fixing for memory bank configuration protocol. Reduce number of BL/WLs at the top-level
|
2020-06-11 19:31:14 -06:00 |
|
tangxifan
|
c85ccceac7
|
try bug fixing in memory bank configuration protocol
|
2020-06-11 19:31:14 -06:00 |
|
tangxifan
|
0bee70bee6
|
finish memory bank configuration protocol support.
|
2020-06-11 19:31:13 -06:00 |
|
tangxifan
|
e14c39e14c
|
update Verilog full testbench generation to support memory bank configuration protocol
|
2020-06-11 19:31:13 -06:00 |
|
tangxifan
|
51e1559352
|
add fabric bitstream support for memory bank configuration protocol
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2020-06-11 19:31:13 -06:00 |
|
tangxifan
|
0e16ee1030
|
add configuration bus nets for memory bank decoders at top module
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2020-06-11 19:31:13 -06:00 |
|
tangxifan
|
fa8dfc1fbd
|
add configuration protocol ports to top module for memory bank organization
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2020-06-11 19:31:13 -06:00 |
|
tangxifan
|
ad7422359d
|
deploy compact constant values in Verilog codes
|
2020-06-11 19:31:13 -06:00 |
|
tangxifan
|
8ec8ac4118
|
bug fixed in flatten memory organization. Passed verification
|
2020-06-11 19:31:12 -06:00 |
|
tangxifan
|
b9aac3cbdf
|
updated fpga verilog testbench generation to support vanilla (standalone) configuration protocol
|
2020-06-11 19:31:12 -06:00 |
|
tangxifan
|
fbe05963e0
|
add configuration bus builder for flatten memory organization (applicable to memory bank and standalone configuration protocol)
|
2020-06-11 19:31:12 -06:00 |
|
tangxifan
|
d2d443a988
|
start developing memory bank and standalone configuration protocol
|
2020-06-11 19:31:12 -06:00 |
|
tangxifan
|
9e176b8d38
|
add fast configuration stats to log
|
2020-06-11 19:31:12 -06:00 |
|
tangxifan
|
8b3e79766c
|
add fast configuration option to fpga_verilog to speed up full testbench simulation
|
2020-06-11 19:31:12 -06:00 |
|
tangxifan
|
b5e5182f52
|
frame-based configuration protocol is working on k4n4 arch now. Spot bugs in iVerilog about negedge flip-flops
|
2020-06-11 19:31:11 -06:00 |
|
tangxifan
|
31c9a011dd
|
keep bug fixing for arch decoders
|
2020-06-11 19:31:11 -06:00 |
|
tangxifan
|
bdc9efb38f
|
bug fix in top-level testbench for frame-based decoders
|
2020-06-11 19:31:11 -06:00 |
|
tangxifan
|
986956e474
|
bug fix for arch decoder Verilog codes. Now Modelsim compiles ok.
|
2020-06-11 19:31:11 -06:00 |
|
tangxifan
|
6a72c66eb8
|
bug fixed for frame-based configuration memory in top-level full testbench
|
2020-06-11 19:31:11 -06:00 |
|
tangxifan
|
8aa665b3b2
|
bug fix in the Verilog codes for frame decoders
|
2020-06-11 19:31:10 -06:00 |
|
tangxifan
|
8298bbff78
|
bug fixed in the fabric bitstream for frame-based configurable memories.
|
2020-06-11 19:31:10 -06:00 |
|
tangxifan
|
bf9f62f0f7
|
keep bug fixing for frame-based configuration protocol.
|
2020-06-11 19:31:10 -06:00 |
|
tangxifan
|
65df309419
|
bug fixing for frame-based configuration protocol and rename some naming function to be generic
|
2020-06-11 19:31:10 -06:00 |
|
tangxifan
|
ece651ade2
|
bug fixed in the configuration chian errrors
|
2020-06-11 19:31:10 -06:00 |
|
tangxifan
|
cff5b5cfc1
|
break the configuration testbench. This commit is to spot which modification leads to the problem
|
2020-06-11 19:31:10 -06:00 |
|
tangxifan
|
85921dcc05
|
add fabric bitstream builder for frame-based configuration protocol
|
2020-06-11 19:31:10 -06:00 |
|
tangxifan
|
4a0e1cd908
|
add fabric bitstream data structure and deploy it to Verilog testbench generation
|
2020-06-11 19:31:10 -06:00 |
|
tangxifan
|
8c14cced84
|
start improve fabric bitstream database to support frame-based configuration protocol
|
2020-06-11 19:31:09 -06:00 |
|
tangxifan
|
5c5a044c68
|
add architecture decoder (for frame-based config memory) to Verilog writer
|
2020-06-11 19:31:09 -06:00 |
|
tangxifan
|
c696e3d20f
|
refine frame-based memory addition to compact the area
|
2020-06-11 19:31:09 -06:00 |
|
tangxifan
|
ed2325ec9e
|
add frame decoder build-up to top-level module
|
2020-06-11 19:31:09 -06:00 |
|
tangxifan
|
290dd1a8a6
|
add frame decoder builder to all the module graph builder except the top-level
|
2020-06-11 19:31:09 -06:00 |
|
tangxifan
|
8864920460
|
add frame-based memory module builder
|
2020-06-11 19:31:09 -06:00 |
|
tangxifan
|
3a26bb5eef
|
add advanced check in configurable memories
|
2020-06-11 19:31:09 -06:00 |
|
tangxifan
|
bba476fef4
|
add explicit port mapping support to Verilog testbench generator
|
2020-06-11 19:31:07 -06:00 |
|
tangxifan
|
e089b0ef22
|
use constant string for inverted port naming
|
2020-06-11 19:31:07 -06:00 |
|
tangxifan
|
8915d10d27
|
add verbose output option to configure port disable timing writer
|
2020-06-11 19:31:07 -06:00 |
|
tangxifan
|
6177921d4c
|
bug fixed in configure port disable timing. Now we disable the right ports of LUTs
|
2020-06-11 19:31:07 -06:00 |
|
tangxifan
|
f52b5d5b4c
|
use error code in read_arch command
|
2020-06-11 19:31:07 -06:00 |
|
tangxifan
|
e9ceedb01b
|
use constant openfpga context in SDC generator
|
2020-06-11 19:31:07 -06:00 |
|
tangxifan
|
067d09f954
|
bug fix for configure port disable_timing writer
|
2020-06-11 19:31:06 -06:00 |
|
tangxifan
|
13f591cacf
|
add new command to disable timing for configure ports of programmable modules
|
2020-06-11 19:31:06 -06:00 |
|
tangxifan
|
ae9f1fbd90
|
critical bug fixed in the disable MUX output
|
2020-06-11 19:31:06 -06:00 |
|
tangxifan
|
99751b84f5
|
bug fix in configuration chain sdc writer
|
2020-06-11 19:31:06 -06:00 |
|
tangxifan
|
02e86c565a
|
bug fix in configuration chain SDC writer
|
2020-06-11 19:31:06 -06:00 |
|
tangxifan
|
4c0953415b
|
add configuration chain sdc writer
|
2020-06-11 19:31:06 -06:00 |
|
tangxifan
|
dad99d13a2
|
bug fixed in SDC timing writer for primitive pb_type
|
2020-06-11 19:31:06 -06:00 |
|
tangxifan
|
8d2360a710
|
simplify include_netlist.v
|
2020-06-11 19:31:05 -06:00 |
|
tangxifan
|
b8a79c563d
|
bug fix in the SDC port generation
|
2020-06-11 19:31:05 -06:00 |
|
tangxifan
|
84d24ad075
|
bug fix in pnr sdc grid writer for module paths in hierarchical view
|
2020-06-11 19:31:05 -06:00 |
|
tangxifan
|
99fa51cb49
|
bug fixed in the SDC CB hierarchy writer
|
2020-06-11 19:31:05 -06:00 |
|
tangxifan
|
10e1a4b2fe
|
format fix in the fabric hierarchy and grid SDC hierarchy to be complaint to YAML format
|
2020-06-11 19:31:05 -06:00 |
|
tangxifan
|
cc6d988872
|
bug fix in grid SDC generator
|
2020-06-11 19:31:05 -06:00 |
|
tangxifan
|
b167c85980
|
fully expand grid hierarchy in SDC writer
|
2020-06-11 19:31:05 -06:00 |
|
tangxifan
|
55518f4cec
|
minor fix in the sdc hierarchy writer for grids
|
2020-06-11 19:31:05 -06:00 |
|
tangxifan
|
b57a90a6ca
|
add SDC hierarchy writer for grids and now support flatten hierarchy in grid timing constraints
|
2020-06-11 19:31:05 -06:00 |
|
tangxifan
|
5a8c05378e
|
add --depth option to fabric hierarchy writer
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2020-06-11 19:31:04 -06:00 |
|
tangxifan
|
d9dc7160a7
|
minor fix on the hierarchy writer in SDC generator
|
2020-06-11 19:31:04 -06:00 |
|
tangxifan
|
17c254a370
|
add missing file to follow up the previous commit
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2020-06-11 19:31:04 -06:00 |
|
tangxifan
|
c651df6421
|
add hierarchy writer to SDC generator
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2020-06-11 19:31:04 -06:00 |
|
tangxifan
|
6aff33dd35
|
add fabric hierarchy writer
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2020-06-11 19:31:04 -06:00 |
|
tangxifan
|
0985c720e9
|
remove regexp in SDC generation.
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2020-06-11 19:31:04 -06:00 |
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tangxifan
|
8726c618eb
|
add time unit support on SDC generator. Now users can define time_unit thru cmd-line options
|
2020-06-11 19:31:03 -06:00 |
|
tangxifan
|
0e44cf3ea3
|
now SDC to disable routing multiplexer outputs can use wildcards
|
2020-06-11 19:31:03 -06:00 |
|
tangxifan
|
609115e51f
|
now hierarchical SDC generation is applicable to CB timing constraints
|
2020-06-11 19:31:03 -06:00 |
|
tangxifan
|
7e82c23f52
|
now add SDC generator supports both hierarchical and flatten in writing timing constraints
|
2020-06-11 19:31:03 -06:00 |
|
tangxifan
|
7503c58fb2
|
small fix on SDC generator for SB which do not exist in FPGA
|
2020-06-11 19:31:02 -06:00 |
|
tangxifan
|
d0793d9029
|
now disable_sb_output support wildcard
|
2020-06-11 19:31:02 -06:00 |
|
tangxifan
|
8695c5ee78
|
add options to use general-purpose wildcards in SDC generator
|
2020-06-11 19:31:02 -06:00 |
|
tangxifan
|
facd87dafe
|
use wildcard in SDC generation for multiple-instanced-blocks
|
2020-06-11 19:31:02 -06:00 |
|
tangxifan
|
1e2226e1c3
|
now use explicit port mapping in the verilog testbenches for reference benchmarks
|
2020-06-11 19:31:02 -06:00 |
|
tangxifan
|
69306faf22
|
add a new include netlist for all the fabric-related netlists
|
2020-06-11 19:31:01 -06:00 |
|
tangxifan
|
8f5a684b10
|
removed redundant include files in all the verilog netlists except the top one
|
2020-06-11 19:28:13 -06:00 |
|
tangxifan
|
185e574738
|
removed redundant include files in all the verilog netlists except the top one
|
2020-04-24 20:21:32 -06:00 |
|
tangxifan
|
e811f8bb21
|
plug in netlist manager and now the include_netlist appears in one unique file
|
2020-04-23 20:42:11 -06:00 |
|
tangxifan
|
87b17fc25f
|
add netlist manager data structure
|
2020-04-23 18:59:09 -06:00 |
|
tangxifan
|
bf841b9a8e
|
bug fixed in identifying wired LUT
|
2020-04-22 17:28:16 -06:00 |
|
tangxifan
|
8ac6e10727
|
bug fix in lut and mux module generation on supporting spypads
|
2020-04-22 14:41:16 -06:00 |
|
tangxifan
|
73e9006372
|
add arch file with spy pads
|
2020-04-22 12:56:09 -06:00 |
|
tangxifan
|
9960625b01
|
add example spypad architecture
|
2020-04-22 11:10:59 -06:00 |
|
tangxifan
|
2e3054f79a
|
bug fixed for SDC generation for LUTs
|
2020-04-21 14:34:51 -06:00 |
|
tangxifan
|
68b7991a46
|
bug fixed for sdc on memory blocks
|
2020-04-21 13:37:56 -06:00 |
|
tangxifan
|
d325bede68
|
add fabric bitstream writer
|
2020-04-21 12:02:10 -06:00 |
|
tangxifan
|
3f1fb70d16
|
FPGA SDC now constrain max and min delay for primitive modules in grids
|
2020-04-21 11:00:28 -06:00 |
|
tangxifan
|
c2804a4c1f
|
bug fix for RC delay computing in SDC generation
|
2020-04-20 22:20:00 -06:00 |
|
tangxifan
|
1a8968cb37
|
now FPGA-SDC will constrain timing for routing tracks using the VPR Rmetal parameter in ARCH XML
|
2020-04-20 21:12:51 -06:00 |
|
tangxifan
|
e10cafe0a5
|
Critical patch on repacking about wire LUT support.
Previously, the wire LUT identification is too naive and does not consider all the cases
|
2020-04-19 16:42:31 -06:00 |
|
tangxifan
|
2e3a811f4f
|
critical bug fixed in repacking. This is due to depop50% local routing where the same net may be mapped to two different pins in the same pb_graph_pin. Now we restrict the pin searching. But in long term, we should sync the pb_route results to post routing results
|
2020-04-18 21:04:46 -06:00 |