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OpenFPGA
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307 Commits

Author SHA1 Message Date
tangxifan f0ecc51b51 bug fixing to resolve the conflicts between explicit port map and standard cell map 2019-07-12 10:38:20 -06:00
Baudouin Chauviere e461cd0b99 Merge branch 'tileable_routing' of https://github.com/LNIS-Projects/OpenFPGA into tileable_routing 2019-07-11 22:09:49 -06:00
Baudouin Chauviere 1431ee2f82 Fix Explicit verilog 2019-07-11 22:09:34 -06:00
tangxifan cffdebd912 bug fixed for the tileable RR graph generator for heterogeneous blocks 2019-07-11 21:02:09 -06:00
Baudouin Chauviere c9b84f61c9 Hot fix 2019-07-11 17:39:02 -06:00
Baudouin Chauviere d0cd5a2bc1 Hot fix 2019-07-11 17:27:31 -06:00
tangxifan 9c203ca4d2 bug fixing in SDC generator 2019-07-11 17:10:08 -06:00
tangxifan 31749fe62b fix bugs in fpga_flow.pl 2019-07-10 21:12:00 -06:00
tangxifan a90316e9f4 Merge branch 'dev' of https://github.com/LNIS-Projects/OpenFPGA into dev 2019-07-10 15:13:46 -06:00
tangxifan acee0161c7 Merge branch 'tileable_routing' into dev 2019-07-10 15:13:24 -06:00
Baudouin Chauviere 6441f2ebe7 Merge branch 'dev' of https://github.com/LNIS-Projects/OpenFPGA into dev 2019-07-10 14:16:55 -06:00
Baudouin Chauviere 0a978db866 Fix regression test 2019-07-10 14:16:34 -06:00
tangxifan b7f9831bd2 add statistics for unique GSBs 2019-07-10 13:08:03 -06:00
tangxifan c6a4d29ed8 Merge branch 'tileable_routing' into dev 2019-07-10 12:05:43 -06:00
tangxifan 57ae5dbbec bug fixing for rectangle FPGA sizes 2019-07-09 20:47:52 -06:00
tangxifan edfe3144c3 update profiling, found where runtime is lost 2019-07-09 20:28:01 -06:00
tangxifan 737cc2874f Merge branch 'tileable_routing' into dev 2019-07-09 17:42:44 -06:00
tangxifan 65f696c1d7 fix critical bugs in rectangle floorplan 2019-07-09 17:41:20 -06:00
Baudouin Chauviere 4ca0967453 Merge branch 'dev' of https://github.com/LNIS-Projects/OpenFPGA into dev 2019-07-09 14:35:51 -06:00
Baudouin Chauviere 792ba23f4f Correction pre-merge 2019-07-09 14:34:34 -06:00
Baudouin Chauviere 589f58b55e Regression test succeeded 2019-07-09 09:18:06 -06:00
Baudouin Chauviere 25f5bc7792 Latest version, not stable yet but close 2019-07-09 08:34:01 -06:00
tangxifan 5d5e09fcdb minor fix in trying to accelerate the unique routing functions 2019-07-08 17:12:36 -06:00
Baudouin Chauviere df0a3d23a3 Correction top module 2019-07-08 10:23:14 -06:00
Baudouin Chauviere ae05c553d5 Top module done 2019-07-08 09:48:33 -06:00
tangxifan 76fefdb876 bug fixing in Fc_in and be serious in the performance of rr_graph 2019-07-05 16:23:15 -06:00
tangxifan c62762ce59 bug fixing in assign ipins to tracks using Fc_in 2019-07-05 13:42:22 -06:00
tangxifan 64d8e9663a minor fix to satisfy Fc_in and Fc_out 2019-07-05 13:13:35 -06:00
tangxifan 3077efa74f add option to compact tileable routing arch 2019-07-04 17:13:34 -06:00
tangxifan d64aeef5c4 add profiling to routing compact process 2019-07-03 16:57:34 -06:00
tangxifan 1a1da30ae9 fixed a critical bug in using tileable route chan W 2019-07-03 16:46:43 -06:00
tangxifan b79d276ea9 add profiling to fpga_x2p_setup 2019-07-03 14:44:54 -06:00
tangxifan d5137eb424 Merge branch 'dev' of https://github.com/LNIS-Projects/OpenFPGA into tileable_routing 2019-07-03 14:31:18 -06:00
tangxifan 5195faab8b Merge branch 'dev' into tileable_routing 2019-07-03 14:30:39 -06:00
tangxifan 4f3cb0bdf3 added tileable routing chanW adaption to fixed W router 2019-07-03 14:29:50 -06:00
Ganesh Gore 443a73954f Removed all local files 
+ Removed local configurations and scripts from previous commit
 2019-07-03 14:26:06 -06:00
Ganesh Gore 57ad71438b Merging ganesh_dev to dev 
- Added spice_tool option in fpga_flow
- Some local customization
 2019-07-03 13:39:52 -06:00
tangxifan 0c3e8bb70a add a new option to the router to enable conversion of route_chan_width to be tileable 2019-07-03 12:11:48 -06:00
tangxifan 02398818a9 update fpga_flow scripts to support matlab data format. Minor fix on rr_graph_area 2019-07-03 10:33:02 -06:00
tangxifan 4392c6bc3a bug fixing in fpga_flow scripts and add more print-out message for VPR 2019-07-02 15:34:59 -06:00
Baudouin Chauviere b08513d902 Big chunk added on the routing part of the explicit mapping 2019-07-02 14:12:42 -06:00
Baudouin Chauviere 8f5ad2eb67 Snapshot of progress 2019-07-02 10:10:48 -06:00
tangxifan 95674c4687 added Switch Block SubType and SubFs for tileable rr_graph generation 2019-07-02 10:00:02 -06:00
tangxifan 44301bfd77 updated SPICE generator to avoid issues on clb2clb_direct 2019-07-02 09:01:52 -06:00
tangxifan 5b25bbb120 bug fixed for direct connection in CBs and direct connection in top netlist 2019-07-01 17:25:00 -06:00
Baudouin Chauviere f189ef1d8f Done with the submodules 2019-07-01 14:24:09 -06:00
Baudouin Chauviere 370ce23646 Mux explicit verilog done 2019-07-01 13:58:24 -06:00
Baudouin Chauviere 863e8677c0 Further add new functions to tree 2019-07-01 12:12:36 -06:00
Baudouin Chauviere 0e04b88c8f Include new files in the parameter spreading 2019-07-01 11:27:48 -06:00
tangxifan 1332ba62e8 update tileable rr_graph generator to improve routability and also enable assoicated testing 2019-06-27 17:52:25 -06:00