a137f7148c
[arch] fixed a bug
2022-09-20 15:47:15 -07:00
3f8106f12e
[arch] fixed a bug in the custom I/O location assignment: no more I/Os on the corner of centre fabric
2022-09-20 15:19:32 -07:00
b3449a338f
[arch] update out-of-date vpr arch from v1.1 to v1.2
2022-09-20 09:51:43 -07:00
373566416c
Merge branch 'master' of https://github.com/lnis-uofu/OpenFPGA into vtr_upgrade
2022-09-16 16:47:21 -07:00
f2e13e5ea9
[arch] add more flexible layout to test I/O center features
2022-09-16 10:00:08 -07:00
ec38b3990f
[arch] update to check OpenFPGA I/O indexing
2022-09-14 13:58:12 -07:00
83c89ae1bf
[arch] add more corner case to test the custom I/O location feature
2022-09-13 23:05:41 -07:00
a37e270f25
[arch] now custom I/O loc test case cover I/Os in the center of the fabric
2022-09-13 16:57:18 -07:00
cc974a80f7
[arch] added a new architecture to test the local routing architecture where reset is on LUT
2022-09-09 16:48:10 -07:00
95d7a17b3c
Merge branch 'master' into vtr_upgrade
2022-09-09 14:32:42 -07:00
419a3a1e46
[arch] fixed a bug
2022-09-08 16:53:52 -07:00
122a323668
[arch] fixed bugs
2022-09-08 16:50:33 -07:00
218e6d0a47
[arch] fixed syntax errors
2022-09-08 16:31:52 -07:00
b1fad0b4e5
[arch] add an example architecture to show the use extended syntax
2022-09-08 16:19:21 -07:00
9e1abf5898
Merge branch 'master' into vtr_upgrade
2022-09-01 21:39:14 -07:00
c48f750f86
[test] now reduce the size for ql memory bank from 96x96 to 72x72; 96x96 requires >15G memory which exceeds github runner machine's RAM limit
2022-09-01 20:10:29 -07:00
dbacee8a0a
[script] turn off equivalent for soft adder architecture as we do not expect any routing optimization
2022-08-27 20:25:50 -07:00
bdb051f787
[arch] update arch files
2022-08-22 18:24:37 -07:00
2bbf2f02c9
[script] now return status on each arch upgrade task
2022-08-22 18:23:00 -07:00
b6e1175517
[script] update doc and avoid modify README.MD when updating arch files
2022-08-22 18:19:23 -07:00
8d45903dc2
[script] makefile for vpr arch
2022-08-22 18:13:48 -07:00
9832722056
[test] now add QuickLogic memory bank to fpga bitstream regression tests
2022-05-25 11:42:32 +08:00
9f56e61342
[arch] syntax
2022-05-09 17:13:57 +08:00
812af4f722
[arch] add arch that supports negative edge triggered flip-flop
2022-05-09 16:32:01 +08:00
f8ef3df560
[Test] Now use 4x4 fabric in testing write_rr_gsb commands
2022-01-26 11:41:48 -08:00
27caeb1d1f
[Arch] Patched VPR arch
2022-01-02 20:47:22 -08:00
384a1e58d6
[Arch] Patch architecture using DSP with registers
2022-01-02 20:44:43 -08:00
e3baec63f8
[Arch] Bug fix on architecture with registerable DSP
2022-01-02 20:35:48 -08:00
f667065f75
[Arch] Bug fix in DSP with registers architecture
2022-01-02 20:34:26 -08:00
9c476ed5db
[Arch] Syntax error fix
2022-01-02 20:27:00 -08:00
7598455497
[Doc] Update naming convention for architecture files
2022-01-02 19:51:09 -08:00
48491fcf52
[Flow] Add example architecture for DSP with input and output registers
2022-01-02 19:47:39 -08:00
81966c2131
[Doc] Update README for DSP blocks
2022-01-02 18:27:37 -08:00
be47e78289
[Arch] Change arch for Sapone test
2021-10-30 15:23:19 -07:00
dcb89cb16b
[Arch] Patch architecture due to missing mode bit definition
2021-07-02 11:41:29 -06:00
fd85f956c9
[Arch] Update k4n4 arch with true multi-mode flip-flop
2021-07-02 11:08:39 -06:00
bc34efe337
[Arch] Bug fix in the architecture using BRAM spanning two columns
2021-04-28 14:32:17 -06:00
be98775ae5
[Arch] Reduce the size of DPRAM in example architecture to accelerate testing
2021-04-28 10:45:10 -06:00
79b27a6329
[Arch] Patch arch using DPRAM block with wide = 2
2021-04-28 10:29:09 -06:00
834657f2da
[Arch] Patch arch using 16kbit DPRAM due to wrong addr sizes
2021-04-27 23:41:14 -06:00
0f8aaae2bc
[Arch] Patch architecture using 16kbit dual port RAM
2021-04-27 19:54:34 -06:00
8c007c7c49
[Arch] Add a new example architecture where a DSP block occupies a 2x2 grid
2021-04-26 16:28:10 -06:00
7d4c5e3cd1
[Arch] Patch pin location of dsp8 to be evenly placed on the right side of a height=2 block
2021-04-26 12:00:57 -06:00
6e87b8875b
[Arch] Patch the pin location of frac dsp16 to appear on the top side of a height=2 block
2021-04-26 11:59:25 -06:00
5adffad602
[Arch] Changes to the arch to avoid a bug where the rr_nodes at top side of a heterogenenous block have no fan-in!!!
2021-04-24 15:49:53 -06:00
4f454abfde
[Arch] Add a new architecture using fracturable 16-bit DSP blocks
2021-04-24 14:01:42 -06:00
ce6018e123
[Arch] Enriched DFF model to support active-low/high FFs
2021-04-21 22:48:31 -06:00
9d9840d9b7
[Arch] Add architecture using multi-mode DFFs
2021-04-21 19:49:48 -06:00
e3dafe99da
[Arch] Revert to old version arch due to editing by mistake
2021-04-16 20:58:32 -06:00
16e02ef485
[Arch] patch architectures to be consistent with port mapping of custom DFF in yosys script
2021-04-16 20:47:39 -06:00
4239bb4e68
[Arch] Patch architecture files using multi-mode DFFs
2021-04-16 19:59:55 -06:00
f2f7f010ea
[Arch] Add new architectures using DFF with reset in VPR
2021-04-16 19:26:18 -06:00
64294ae4eb
[Doc] Update README for architecture files due to new architecture features
2021-04-16 19:25:54 -06:00
44d97ead86
Merge branch 'master' into hetergeneous_arch
2021-03-23 17:05:03 -06:00
fdec72b5bc
[Arch] Add an example architecture with 8-bit single-mode multiplier
2021-03-23 15:35:06 -06:00
911979a731
[Arch] Update heterogenous architecture for vtr benchmark by adding mult36
2021-03-20 18:04:59 -06:00
910f8471dd
[Arch] Add a representative heterogeneous FPGA architecture with single-mode BRAM (which can be synthesized by Yosys)
2021-03-17 15:10:05 -06:00
ad25944e59
[Arch] Patched superLUT architecture example when trying adder8 synthesis script
2021-02-23 19:00:27 -07:00
ca135f3325
[Arch] Add flagship architecture with 8-clock
2021-02-22 15:01:18 -07:00
1c09c55e9f
[Arch] Add hetergenenous 8-clock FPGA architecture
2021-02-22 13:38:50 -07:00
0ac75723af
[Arch] Add new architecture with 8 clocks
2021-02-22 11:00:45 -07:00
b9c2564a7e
[Arch] Add VPR architecture with 5 clocks to test counter with 5 clocks
2021-02-22 10:49:21 -07:00
7dcc14d73f
[Arch] Bug fix in the example arch with super LUT
2021-02-09 15:52:22 -07:00
304b26c97f
[Arch] Add example architectures for superLUT circuit model
2021-02-09 15:11:12 -07:00
00fc3d7622
Merge pull request #217 from lnis-uofu/dev
...
Synchronize the out-of-date XML syntax 'disable_in_pack' with VPR upstream
2021-02-05 09:53:28 -07:00
dc09c47411
[Arch] Remove packable from architecture files and replace with disable_packing
2021-02-04 18:03:56 -07:00
66bc370c4d
[Arch] Use disable_packing in architecture library
2021-02-04 16:29:03 -07:00
a4c266d59a
[Arch] Add pack patterns for soft adders; Still fail in packing
2021-02-03 19:11:15 -07:00
cac1160bf7
[Arch] Patch QLSOFA architecture to support carry chain pattern; Still buggy for VPR packer; Looking for a solution
2021-02-03 11:20:56 -07:00
021520783b
[Arch] Add dummy timing info to adder_lut4 and carry_follower model
2021-02-02 15:49:43 -07:00
10302752a7
[Arch] Bug fix in architecture. Now soft adder modes are accepted
2021-02-01 13:43:39 -07:00
d8927e12e8
[Arch] Add soft adder operating mode to test architecture
2021-02-01 12:25:37 -07:00
9bbf214456
[Arch] Update the caravel architecture
2021-01-29 17:00:17 -07:00
3f5cc59c0a
Microbenchmarks of Single-Port RAM and Associated Example Architecture Files as well as Test Cases ( #200 )
...
* Add required files for LUTRAM integration and testing
* Add task for lutram
* Repair format (tab and space mismatched)
* Add disclaimer in architecture file
Co-authored-by: Aur??Lien ALACCHI <u1235811@lnissrv4.eng.utah.edu>
2021-01-29 10:19:05 -07:00
16b4e89326
[Doc] Update documentation for VPR architectures
2021-01-12 17:57:40 -07:00
7ccdff4543
[Arch] Add an architecture using 4 clocks
2021-01-12 17:55:57 -07:00
aaf582acc5
[Arch] Bug fix
2021-01-10 11:05:57 -07:00
f21d22f691
[Doc] Update README for new architectures
2021-01-10 10:54:59 -07:00
853e7b1a40
[Arch] Add vpr architecture where I/O can be either combinational or registered
2021-01-10 10:54:09 -07:00
891e2f8aa3
Adding arch xml from SOFA repo. Also updating the script with its file location
2020-12-16 04:14:18 -08:00
6001da3a40
[Arch] Bug fix in tileable I/O arch example
2020-12-04 17:56:54 -07:00
1d0bdcfeca
[Arch] Simplify the grid layout modeling
2020-12-04 17:38:44 -07:00
1c3f625e41
[Arch] Force empty tiles at corners for tileable I/O arch example
2020-12-04 17:11:06 -07:00
186eb0f0a4
[Arch] Add tileable I/O architecture example
2020-12-04 15:59:39 -07:00
7a0a3398d4
[Arch] Add new architecture to test global reset ports defined thru tile ports
2020-11-30 17:43:41 -07:00
a60bd4d14a
[Arch] Bug fix in nature fracturable architecture
2020-11-25 22:48:26 -07:00
eda671592e
[Doc] Update README about new keyword about fracturable LUT
2020-11-25 22:12:56 -07:00
0f841aa6d1
[Arch] Add an example architecture using native fracturable LUT
2020-11-25 22:11:14 -07:00
a6531d9e8d
[Arch] Add k4 arch using global clock from tile port (with zero fc)
2020-11-10 19:17:34 -07:00
bce8233019
[Arch] Bug fix in caravel arch
2020-11-04 20:58:58 -07:00
aebf7453d0
[Arch] Add architecture files with compatible I/O capacity with caravel SoC
2020-11-04 16:57:00 -07:00
cf455df555
[Arch] Add architecture for bottom-right and top-left tile organization
2020-11-04 16:24:36 -07:00
46ca406f10
[Arch] Add a new vpr architecture with new tile organization
2020-11-04 16:20:01 -07:00
049ca14461
[Doc] Add new naming rules for vpr architecture files
2020-11-04 16:17:56 -07:00
3b49e6d090
[Arch] Patch embedded IO architecture by forcing only 1 pad per block
2020-11-02 15:39:31 -07:00
a7e7fa2005
[Arch] Update arch with true embedded I/O definition
2020-11-02 13:29:40 -07:00
8c8190047f
[Arch] Rename architecture files for embedded I/Os
2020-11-02 13:15:19 -07:00
795b30f76b
[Arch] Add VPR architecture with partial pin equivalence
2020-11-02 11:54:25 -07:00
951a47b19c
[Architecture] Add k4 series architecture using pattern-based local routing
2020-09-23 16:05:39 -06:00
70b8b02f74
[Architecture] Add vpr architecture for k4n4 with fracturable 32-bit multiplier
2020-09-22 15:32:11 -06:00
tangxifan
AurelienAlacchi
Lalit Sharma