tangxifan
|
dff03e7993
|
[test] enable missing options in the arch used by benchmark sweeping tests
|
2023-11-14 09:45:02 -08:00 |
|
tangxifan
|
0b473e3454
|
[test] fixed the bug in single-mode lut testcase
|
2023-11-14 09:35:26 -08:00 |
|
tangxifan
|
d108284105
|
[test] update arch to keep golden outputs
|
2023-11-14 09:31:07 -08:00 |
|
tangxifan
|
913434b70d
|
[test] fixed the bug that golden netlists are modified
|
2023-11-14 09:28:57 -08:00 |
|
tangxifan
|
59d086a27f
|
[test] try to keep the golden inputs
|
2023-11-14 09:25:45 -08:00 |
|
tangxifan
|
1b8748abb4
|
[core] update vtr
|
2023-11-13 14:21:34 -08:00 |
|
tangxifan
|
d78f18d235
|
[test] add new testcase
|
2023-11-13 14:11:34 -08:00 |
|
tangxifan
|
56cedf6c8b
|
[test] added a new test case to validate the support on different wire segment distribution on X and Y
|
2023-08-22 11:20:14 -07:00 |
|
tangxifan
|
1b132fd667
|
[test] add a new testcase to validate the support on different routing channel width on X and Y
|
2023-08-22 11:06:12 -07:00 |
|
tangxifan
|
e4c5265b68
|
[test] arch syntax
|
2023-08-18 21:40:56 -07:00 |
|
tangxifan
|
5ac8919ce0
|
[test] add a new testcase to validate subtile with tile annotations
|
2023-08-18 21:37:15 -07:00 |
|
tangxifan
|
f69520d0c3
|
[arch] format
|
2023-08-18 11:15:25 -07:00 |
|
tangxifan
|
170a49c34f
|
[test] fix a bug in arch file
|
2023-08-18 11:15:05 -07:00 |
|
tangxifan
|
e82e4f487e
|
[test] add a new test to validate io subtile support
|
2023-08-18 11:13:34 -07:00 |
|
tangxifan
|
4afd48d930
|
[test] format
|
2023-08-17 15:33:09 -07:00 |
|
tangxifan
|
463897f78e
|
[test] fixed a bug in arch
|
2023-08-17 15:28:59 -07:00 |
|
tangxifan
|
3ac3eb4624
|
[test] adding more flavor to the L shape
|
2023-08-17 15:08:27 -07:00 |
|
tangxifan
|
253d5fa26c
|
[core] a new test to validate the L shape in homo geneous fpga
|
2023-08-11 13:05:46 -07:00 |
|
tangxifan
|
dc0eec8b81
|
[test] added a new test to validate L shapre
|
2023-08-11 12:49:38 -07:00 |
|
tangxifan
|
5685fbd5e8
|
[test] adding a new test case to validate the tile modules on 4x4 fabric
|
2023-07-26 22:17:39 -07:00 |
|
tangxifan
|
f89b7a82cf
|
[arch] fixed a bug where the array size mismatch the layout name
|
2023-05-03 22:23:20 +08:00 |
|
tangxifan
|
a3f2ae3c33
|
[arch] format
|
2023-05-03 15:23:47 +08:00 |
|
tangxifan
|
68f2d9fe5e
|
[arch] add new example arch using subtile in I/O blocks; Updated documentation
|
2023-05-03 15:16:39 +08:00 |
|
tangxifan
|
02b02d18a5
|
[test] fixed a bug in clock arch
|
2023-04-20 11:35:36 +08:00 |
|
tangxifan
|
b242fd97d6
|
[test] adding new arch and testcase for 2-clock network
|
2023-04-20 11:31:49 +08:00 |
|
tangxifan
|
571a012724
|
[test] xml format
|
2023-03-07 18:47:55 -08:00 |
|
tangxifan
|
7e3b656c51
|
[test] fixed a bug in arch
|
2023-03-06 23:06:32 -08:00 |
|
tangxifan
|
b9f7c72a96
|
[test] fixed some bugs in arch
|
2023-03-02 18:16:59 -08:00 |
|
tangxifan
|
5917446fbe
|
[arch] code format
|
2023-02-28 22:01:49 -08:00 |
|
tangxifan
|
780dec6b1b
|
[test] add a new test to validate the programmable clock arch
|
2023-02-28 21:46:57 -08:00 |
|
tangxifan
|
d1e951e52e
|
[test] debugging
|
2023-01-24 17:57:34 -08:00 |
|
tangxifan
|
1d8c1a6803
|
[arch] adding a new arch to validate fracturable dsp
|
2023-01-24 15:17:50 -08:00 |
|
tangxifan
|
acc905fa11
|
[arch] add support to route reset to LUTs
|
2023-01-18 18:22:37 -08:00 |
|
tangxifan
|
c9e00b7abc
|
[arch] add a new example arch that supports local reset
|
2023-01-18 18:05:52 -08:00 |
|
tangxifan
|
297092f1fe
|
[arch] now use a local clock as an input of a CLB
|
2023-01-14 22:12:00 -08:00 |
|
tangxifan
|
9222d085cd
|
[test] now use local clock as one of the pins in a clock bus, but connected to global routing
|
2023-01-13 22:04:56 -08:00 |
|
tangxifan
|
9e462d96e0
|
[arch] now use a dedicated input for locally generated clock signals
|
2023-01-13 20:46:04 -08:00 |
|
tangxifan
|
1fb39f803b
|
[doc] updated vpr arch naming rules
|
2023-01-13 19:52:58 -08:00 |
|
tangxifan
|
a06ee30ca0
|
[arch] added a new vpr arch where clock can be generated by internal logics
|
2023-01-13 19:35:00 -08:00 |
|
tangxifan
|
32f48f16c7
|
[arch] fixed a few bugs
|
2022-10-13 11:54:58 -07:00 |
|
tangxifan
|
7f67794787
|
[arch]add new arch to test
|
2022-10-13 10:54:40 -07:00 |
|
tangxifan
|
85089cbc88
|
[arch] apply xml format for all the architecture files
|
2022-10-07 10:31:51 -07:00 |
|
tangxifan
|
ab53f88c2b
|
[test] now use a fixed device layout for the single-mode LUT design testcase
|
2022-10-04 10:05:22 -07:00 |
|
tangxifan
|
0565ca7aca
|
[script] add missing files
|
2022-09-29 16:14:38 -07:00 |
|
tangxifan
|
2ed4a60f36
|
[arch] reduce clb inputs to force net remapping during routing
|
2022-09-29 15:52:30 -07:00 |
|
tangxifan
|
ce0fbe1765
|
[test] fixed a few bugs
|
2022-09-29 15:32:31 -07:00 |
|
tangxifan
|
f7a02422b5
|
[arch] add a new arch to reproduce the wire-lut bug in repacker
|
2022-09-29 13:59:08 -07:00 |
|
tangxifan
|
40edf859e3
|
Merge branch 'vtr_upgrade' of github.com:lnis-uofu/OpenFPGA into vtr_upgrade
|
2022-09-20 22:38:06 -07:00 |
|
tangxifan
|
97f0445787
|
[arch] upgrade arch file which was designed for v1.1
|
2022-09-20 22:37:35 -07:00 |
|
tangxifan
|
36603f9772
|
Merge branch 'master' into vtr_upgrade
|
2022-09-20 21:08:06 -07:00 |