tangxifan
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554018449e
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[Test] Update regression test script
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2021-10-06 12:10:37 -07:00 |
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tangxifan
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064ac478f3
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[Test] Deploy news test to fpga-bitstream regression tests
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2021-10-05 19:01:03 -07:00 |
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tangxifan
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b21f212031
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[Test] Replace the multi-region test with the fabric key test because the mutli region of shift-register bank is sensitive to the correctness of fabric key
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2021-10-05 11:39:53 -07:00 |
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tangxifan
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492db50efe
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[Test] Deploy the new test to basic regression tests
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2021-10-05 10:59:26 -07:00 |
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tangxifan
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13c31cb89c
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[Test] Deploy the qlbanksr_wlr to basic regression tests
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2021-10-04 16:37:49 -07:00 |
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tangxifan
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7f75c2b619
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[Test] Deploy shift register -based QL memory bank test case to basic regression test
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2021-10-03 16:06:44 -07:00 |
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tangxifan
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811c898173
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[Test] Add the QL mem flatten BL/WL with WLR test to basic regression tests
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2021-09-28 11:29:45 -07:00 |
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tangxifan
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1ca1b0f3e9
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[Test] Deploy the new test case (flatten BL/WL for QL memory bank) to basic regression tests
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2021-09-22 15:58:05 -07:00 |
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tangxifan
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efed268585
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[Test] Deploy new test (for multi-region QL memory bank) to basic regression tests
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2021-09-22 11:30:08 -07:00 |
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tangxifan
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7db7e2d8f6
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[Test] Deploy the new test case for multi region QL memory bank to basic regression tests
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2021-09-22 10:05:27 -07:00 |
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tangxifan
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f57aceff87
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[Test] Deploy the load external key test case for ql memory bank to basic regression tests
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2021-09-21 16:25:14 -07:00 |
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tangxifan
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7327850cf3
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[Test] Deploy the fabric key test case for ql memory bank to basic regression tests
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2021-09-21 15:43:54 -07:00 |
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tangxifan
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3f6ac41868
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[Test] Deploy the WLR test to the basic regression tests
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2021-09-20 11:21:58 -07:00 |
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tangxifan
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81a2ad58df
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[Test] Deploy the ql memory bank test case to basic regression tests (run on CI)
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2021-09-09 13:48:30 -07:00 |
ANDREW HARRIS POND
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8513b8a4ff
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Merge branch 'verilog_testbench' of github.com:lnis-uofu/OpenFPGA into verilog_testbench
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2021-07-01 15:29:39 -06:00 |
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ANDREW HARRIS POND
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2567fbee05
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ready to merge
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2021-07-01 15:28:59 -06:00 |
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tangxifan
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04ceeefb0a
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Merge branch 'master' into verilog_testbench
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2021-07-01 14:43:26 -06:00 |
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ANDREW HARRIS POND
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db9231c225
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tests failing with initial blocks
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2021-07-01 13:52:28 -06:00 |
Andrew Pond
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fab2b069f0
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added signal gen regression test to shell script
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2021-06-30 16:18:09 -06:00 |
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tangxifan
|
cbea4a3cb6
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[Test] Add the test cases to regression test
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2021-06-29 16:08:22 -06:00 |
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tangxifan
|
b4c587f10b
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[Test] Added the new test cases to regression tests
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2021-06-27 19:58:15 -06:00 |
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tangxifan
|
477cba1c7e
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Merge branch 'master' into verilog_testbench
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2021-06-23 09:18:18 -06:00 |
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tangxifan
|
e34fbf8ecf
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[Test] Deploy MCNC big20 to the micro benchmark regression test
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2021-06-22 16:36:04 -06:00 |
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tangxifan
|
0b2d6eb147
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[Test] Add micro benchmark to a dedicated regression test
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2021-06-21 18:35:41 -06:00 |
|
Andrew Pond
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3cfc42cdf9
|
added testbench CI
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2021-06-15 14:16:31 -06:00 |
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tangxifan
|
c33ca464dc
|
[Test] Deploy new tests to regression test
|
2021-05-07 12:06:46 -06:00 |
|
tangxifan
|
a5e40fbb21
|
Merge branch 'master' into micro_benchmarks
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2021-04-28 14:27:58 -06:00 |
|
tangxifan
|
870432e7f1
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[Test] Patch regression test script due to the change of DPRAM test case
|
2021-04-28 12:45:52 -06:00 |
|
tangxifan
|
6cb4d7d720
|
[Test] Add the new test to regressiont test
|
2021-04-27 14:41:38 -06:00 |
|
tangxifan
|
1d5e926d9e
|
[Test] Deploy new test to CI
|
2021-04-26 16:29:54 -06:00 |
|
tangxifan
|
b7da22501c
|
[Test] Deply new test to regression test
|
2021-04-24 15:55:05 -06:00 |
|
tangxifan
|
784713e88a
|
[Test] Add golden results for IWLS2005 as a simple QoR check
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2021-04-22 19:27:31 -06:00 |
|
tangxifan
|
2fa370d7d5
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[Test] Patch regression tests for fpga bitstream
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2021-04-19 17:15:14 -06:00 |
|
tangxifan
|
18eb5c9de9
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[Test] Deploy new test to CI
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2021-04-19 15:56:41 -06:00 |
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tangxifan
|
c020333512
|
Merge branch 'master' into dff_techmap
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2021-04-16 20:54:28 -06:00 |
|
tangxifan
|
b11d03f9c5
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[Test] Deploy new test to CI
|
2021-04-16 20:01:40 -06:00 |
|
tangxifan
|
87587bbb74
|
[Test] Add iwls2005 benchmarks to regression tests
|
2021-04-16 16:12:05 -06:00 |
|
tangxifan
|
1db8bd7eec
|
[Test] Update regression test with new SDC tests
|
2021-04-11 20:24:32 -06:00 |
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tangxifan
|
44d97ead86
|
Merge branch 'master' into hetergeneous_arch
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2021-03-23 17:05:03 -06:00 |
|
tangxifan
|
d82ffe0cbf
|
[Test] Deploy MAC_8 benchmark to regression test
|
2021-03-23 15:36:28 -06:00 |
|
tangxifan
|
fff16a01ab
|
[Test] Update tolerance when checking VTR benchmark QoR
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2021-03-23 12:27:20 -06:00 |
|
tangxifan
|
e3f8a6cf7a
|
[Test] Deploy QoR check to VTR benchmark regression test
|
2021-03-23 11:15:22 -06:00 |
|
tangxifan
|
08a86e056a
|
[Test] Add vtr benchmark regression test
|
2021-03-17 15:13:58 -06:00 |
|
tangxifan
|
e34380a654
|
Merge branch 'master' into default_net_type
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2021-03-01 08:38:58 -07:00 |
|
tangxifan
|
86930d63d3
|
[Test] Deploy new test to CI
|
2021-02-28 16:18:46 -07:00 |
|
tangxifan
|
6d419fed41
|
[Test] Deploy verilog default net wire type test case to CI
|
2021-02-28 12:33:48 -07:00 |
|
tangxifan
|
27200e3daa
|
[Test] Update regression test cases for fpga verilog
|
2021-02-28 12:24:36 -07:00 |
|
tangxifan
|
86a602d381
|
[Test] Deploy new test to CI
|
2021-02-23 19:55:07 -07:00 |
|
tangxifan
|
b3fed683f9
|
[Test] Deploy test to CI
|
2021-02-22 12:43:30 -07:00 |
|
tangxifan
|
e08ac1a41e
|
[Test] Deploy synthesizable verilog test to CI
|
2021-02-18 19:37:45 -07:00 |