tangxifan
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1ef38b6a64
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[core] now name the port of tiles using the relative index of the subblocks in each tile, rather than the unique index of subblocks across a complete fabric. This avoids all the conflicts in naming
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2023-09-20 20:34:21 -07:00 |
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tangxifan
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fda768bc4a
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Merge pull request #1365 from lnis-uofu/dependabot/submodules/yosys-35a0568
Bump yosys from `e2b6133` to `35a0568`
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2023-09-20 20:19:26 -07:00 |
dependabot[bot]
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8dab580d48
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Bump yosys from `e2b6133` to `35a0568`
Bumps [yosys](https://github.com/YosysHQ/yosys) from `e2b6133` to `35a0568`.
- [Release notes](https://github.com/YosysHQ/yosys/releases)
- [Commits](e2b613355d...35a05686c4)
---
updated-dependencies:
- dependency-name: yosys
dependency-type: direct:production
...
Signed-off-by: dependabot[bot] <support@github.com>
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2023-09-20 06:41:33 +00:00 |
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tangxifan
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6f7c28fa1d
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Merge pull request #1364 from lnis-uofu/patch_update
Pulling refs/heads/master into master
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2023-09-19 11:17:23 -07:00 |
github-actions[bot]
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46abf16931
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Updated Patch Count
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2023-09-19 18:14:23 +00:00 |
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tangxifan
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90a1a8880f
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Merge pull request #1363 from lnis-uofu/dependabot/submodules/yosys-e2b6133
Bump yosys from `b84ed5d` to `e2b6133`
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2023-09-19 09:34:55 -07:00 |
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tangxifan
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b264678242
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Merge pull request #1361 from lnis-uofu/xt_module_naming
Fully Customizable Module Names
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2023-09-19 09:34:30 -07:00 |
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dependabot[bot]
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f21b14c1c0
|
Bump yosys from `b84ed5d` to `e2b6133`
Bumps [yosys](https://github.com/YosysHQ/yosys) from `b84ed5d` to `e2b6133`.
- [Release notes](https://github.com/YosysHQ/yosys/releases)
- [Commits](b84ed5d3ad...e2b613355d)
---
updated-dependencies:
- dependency-name: yosys
dependency-type: direct:production
...
Signed-off-by: dependabot[bot] <support@github.com>
|
2023-09-19 06:53:50 +00:00 |
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tangxifan
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c105b56bf0
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[core] code format
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2023-09-18 23:31:27 -07:00 |
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tangxifan
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43fd08a3fe
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[core] fixed a bug
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2023-09-18 23:31:09 -07:00 |
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tangxifan
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1cf119f8d1
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[doc] comment on the use of fpga_top and fpga_core
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2023-09-18 20:48:06 -07:00 |
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tangxifan
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54475eb7bf
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Merge branch 'master' into xt_module_naming
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2023-09-18 20:44:09 -07:00 |
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tangxifan
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4d11f73471
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[core] fixed a bug
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2023-09-18 20:43:15 -07:00 |
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tangxifan
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e49bed10ca
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Merge pull request #1362 from lnis-uofu/xt_readthdocs
Update .readthedocs.yml to check if python version causes build failures.
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2023-09-18 20:27:25 -07:00 |
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tangxifan
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b52a5b7858
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[doc] debugging
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2023-09-18 18:31:47 -07:00 |
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tangxifan
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9cd4c8498c
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[doc] debugging
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2023-09-18 18:08:01 -07:00 |
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tangxifan
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3217d1f57a
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[doc] debugging
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2023-09-18 18:06:04 -07:00 |
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tangxifan
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973192e5aa
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[doc] update requirements
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2023-09-18 18:01:45 -07:00 |
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tangxifan
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5807af97b1
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Update .readthedocs.yml
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2023-09-18 16:54:06 -07:00 |
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tangxifan
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0495ea67cc
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Merge branch 'xt_module_naming' of github.com:lnis-uofu/OpenFPGA into xt_module_naming
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2023-09-18 16:40:03 -07:00 |
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tangxifan
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a1e609c901
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[core] fixed some bugs
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2023-09-18 16:39:07 -07:00 |
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tangxifan
|
56231ad08a
|
Merge branch 'master' into xt_module_naming
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2023-09-18 15:38:19 -07:00 |
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tangxifan
|
1daabb990e
|
[core] code format
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2023-09-18 15:35:13 -07:00 |
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tangxifan
|
110301a2e4
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[core] now tile port naming can follow index
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2023-09-18 15:34:40 -07:00 |
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tangxifan
|
e46e58527a
|
[core] code format
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2023-09-17 23:16:38 -07:00 |
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tangxifan
|
eeb1bd6662
|
[core] fixed some bugs
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2023-09-17 23:16:15 -07:00 |
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tangxifan
|
c6175aa514
|
[core] code format
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2023-09-17 22:37:48 -07:00 |
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tangxifan
|
ef97127c63
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[core] fixed some bugs in testbenches when renaming top modules
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2023-09-17 22:34:00 -07:00 |
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tangxifan
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c14277a674
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[core] fixing bugs
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2023-09-17 17:57:57 -07:00 |
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tangxifan
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d5152dc16d
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[core] fixed a bug on the hierarchy writer
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2023-09-17 17:42:25 -07:00 |
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tangxifan
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3fd60a165d
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[test] typo
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2023-09-17 17:42:15 -07:00 |
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tangxifan
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11e976ec92
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[test] add a new test to validate renaming on fpga top/core modules
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2023-09-17 17:38:37 -07:00 |
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tangxifan
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4ccb4737be
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[core] code format
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2023-09-17 17:33:10 -07:00 |
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tangxifan
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f79da76656
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[core] supporting renaming on all the verilog modules
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2023-09-17 17:29:11 -07:00 |
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tangxifan
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7e71f655df
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[doc] typo
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2023-09-17 13:46:54 -07:00 |
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tangxifan
|
72a3c05747
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[core] code format
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2023-09-17 13:29:30 -07:00 |
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tangxifan
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0ef1e0bde5
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[test] add a new test to validate renaming rules
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2023-09-17 13:29:12 -07:00 |
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tangxifan
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ccd4c1861b
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[core] developing new command to write module naming rules
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2023-09-16 19:37:06 -07:00 |
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tangxifan
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9e303e9529
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[doc] update for renaming modules
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2023-09-16 19:19:53 -07:00 |
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tangxifan
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32df673d72
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[core] code format
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2023-09-16 18:35:33 -07:00 |
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tangxifan
|
200ecad74a
|
[core] fixed bugs in bitgen
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2023-09-16 18:34:55 -07:00 |
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tangxifan
|
058bb1ef51
|
[core] code format
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2023-09-16 18:24:38 -07:00 |
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tangxifan
|
6fc2924438
|
[core] syntax
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2023-09-16 18:16:30 -07:00 |
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tangxifan
|
d61d88f12e
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[core] fixed some bugs in verilog writer due to renaming
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2023-09-16 18:13:22 -07:00 |
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tangxifan
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559fa45d89
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[test] add a new test to validate module renaming using index
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2023-09-16 17:55:52 -07:00 |
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tangxifan
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67deac9f47
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Merge pull request #1359 from lnis-uofu/patch_update
Pulling refs/heads/master into master
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2023-09-16 12:50:43 -07:00 |
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tangxifan
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37573abc22
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[core] code format
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2023-09-15 23:32:40 -07:00 |
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tangxifan
|
c85c64eb5a
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[core] syntax
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2023-09-15 23:30:34 -07:00 |
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tangxifan
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bc407e5d69
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[core] code complete for rename modules
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2023-09-15 23:22:31 -07:00 |
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tangxifan
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2a45b49890
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[core] developing renaming commands. options and functions
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2023-09-15 19:15:18 -07:00 |