Merge pull request #1361 from lnis-uofu/xt_module_naming

Fully Customizable Module Names

docs/source/manual/file_formats/index.rst

@@ -38,4 +38,6 @@ OpenFPGA widely uses XML format for interchangeable files
 
    io_naming_file
 
+   module_naming_file
+
    tile_config_file

docs/source/manual/file_formats/module_naming_file.rst

@@ -0,0 +1,42 @@
+.. _file_formats_module_naming_file:
+
+Fabric Module Naming (.xml)
+---------------------------
+
+The XML-based description language is used to describe module names for an FPGA fabric, including:
+
+- the built-in name or default name for each module when building an FPGA fabric
+- the customized name which is given by users for each module, in place of the built-in names
+
+Using the description language, users can customize the name for each module in an FPGA fabric, excluding testbenches.
+
+Under the root node ``<module_names>``, naming rules can be defined line-by-line through syntax ``<module_name>``.
+
+.. code-block:: xml
+
+  <module_names> 
+    <module_name default="<string>" given="<string>"/> 
+  </module_names> 
+
+.. note:: If you do not need to rename a module of an FPGA fabric, there is no need to define it explicitly in the naming rules. OpenFPGA can infer it.
+
+Syntax
+``````
+
+Detailed syntax are presented as follows.
+
+.. option:: default="<string>"
+
+  Define the default or built-in name of a module. This follows fixed naming rules of OpenFPGA. Suggest to run command :ref:`openfpga_setup_commands_write_module_naming_rules` to obtain an initial version for your fabric. For example, 
+
+  .. code-block:: xml
+
+   default="cbx_1__2_"
+
+.. option:: given="<string>"
+
+  Define the customized name of a module, this is the final name will appear in netlists. For example, 
+
+  .. code-block:: xml
+
+    given="cbx_corner_left_bottom"

docs/source/manual/openfpga_shell/openfpga_commands/fpga_verilog_commands.rst

@@ -55,6 +55,8 @@ write_full_testbench
 
     Specify the name of *Design Under Test* (DUT) module to be considered in the testbench. Can be either ``fpga_top`` or ``fpga_core. By default, it is ``fpga_top``.
 
+  .. note:: Please use the reserved words ``fpga_top`` or ``fpga_core`` even when renaming is applied to the modules (See details in :ref:`openfpga_setup_commands_rename_modules`). Renaming will be applied automatically.
+
   .. option:: --bitstream <string>     
 
     The bitstream file to be loaded to the full testbench, which should be in the same file format that OpenFPGA can outputs (See detailes in :ref:`file_formats_fabric_bitstream_plain_text`). For example, ``--bitstream and2.bit``
@@ -130,6 +132,8 @@ write_preconfigured_fabric_wrapper
 
     Specify the name of *Design Under Test* (DUT) module to be considered in the testbench. Can be either ``fpga_top`` or ``fpga_core. By default, it is ``fpga_top``.
 
+  .. note:: Please use the reserved words ``fpga_top`` or ``fpga_core`` even when renaming is applied to the modules (See details in :ref:`openfpga_setup_commands_rename_modules`). Renaming will be applied automatically.
+
   .. option:: --pin_constraints_file <string> or -pcf <string>
 
     Specify the *Pin Constraints File* (PCF) if you want to custom stimulus in testbenches. For example, ``-pin_constraints_file pin_constraints.xml``

docs/source/manual/openfpga_shell/openfpga_commands/setup_commands.rst

@@ -279,6 +279,9 @@ build_fabric
   
      Netlist hierarchy on grouped configuable blocks
 
+  .. option:: --name_module_using_index
+
+     Use index in module names, e.g., ``cbx_2_``. This is applied to routing modules, as well as tile modules when option ``--group_tile`` is enabled. If disabled, the module name consist of coordinates, e.g., ``cbx_1__2_``.
  
   .. option:: --duplicate_grid_pin
 
@@ -435,3 +438,37 @@ pcf2place
   .. option:: --verbose
 
     Show verbose log
+
+.. _openfpga_setup_commands_rename_modules:
+
+rename_modules
+~~~~~~~~~~~~~~
+
+  Rename modules of an FPGA fabric with a given set of naming rules
+
+  .. option:: --file <string>
+  
+    Specify the file path which contain the naming rules. See details in :ref:`file_formats_module_naming_file`. 
+
+  .. option:: --verbose
+
+    Show verbose log
+
+.. _openfpga_setup_commands_write_module_naming_rules:
+
+write_module_naming_rules
+~~~~~~~~~~~~~~~~~~~~~~~~~
+
+  Output the naming rules for each module of an FPGA fabric to a given file
+
+  .. option:: --file <string>
+  
+    Specify the file path to be written to
+
+  .. option:: --no_time_stamp
+
+    Do not print time stamp in bitstream files
+
+  .. option:: --verbose
+
+    Show verbose log

libs/CMakeLists.txt

@@ -8,5 +8,5 @@ add_subdirectory(libfabrickey)
 add_subdirectory(libfpgabitstream)
 add_subdirectory(libpcf)
 add_subdirectory(libbusgroup)
-add_subdirectory(libionamemap)
+add_subdirectory(libnamemanager)
 add_subdirectory(libtileconfig)

libs/libnamemanager/CMakeLists.txt

@@ -1,6 +1,6 @@
 cmake_minimum_required(VERSION 3.9)
 
-project("libionamemap")
+project("libnamemanager")
 
 file(GLOB_RECURSE EXEC_SOURCES test/*.cpp)
 file(GLOB_RECURSE LIB_SOURCES src/*/*.cpp)
@@ -11,14 +11,14 @@ files_to_dirs(LIB_HEADERS LIB_INCLUDE_DIRS)
 list(REMOVE_ITEM LIB_SOURCES ${EXEC_SOURCES})
 
 #Create the library
-add_library(libionamemap STATIC
+add_library(libnamemanager STATIC
             ${LIB_HEADERS}
             ${LIB_SOURCES})
-target_include_directories(libionamemap PUBLIC ${LIB_INCLUDE_DIRS})
-set_target_properties(libionamemap PROPERTIES PREFIX "") #Avoid extra 'lib' prefix
+target_include_directories(libnamemanager PUBLIC ${LIB_INCLUDE_DIRS})
+set_target_properties(libnamemanager PROPERTIES PREFIX "") #Avoid extra 'lib' prefix
 
 #Specify link-time dependancies
-target_link_libraries(libionamemap
+target_link_libraries(libnamemanager
                       libarchopenfpga
                       libopenfpgautil
                       libopenfpgashell
@@ -31,7 +31,7 @@ foreach(testsourcefile ${EXEC_SOURCES})
     get_filename_component(testname ${testsourcefile} NAME_WE)
     add_executable(${testname} ${testsourcefile})
     # Make sure the library is linked to each test executable
-    target_link_libraries(${testname} libionamemap)
+    target_link_libraries(${testname} libnamemanager)
 endforeach(testsourcefile ${EXEC_SOURCES})
 
-install(TARGETS libionamemap DESTINATION bin)
+install(TARGETS libnamemanager DESTINATION bin)

libs/libnamemanager/example/example_module_names.xml

@@ -0,0 +1,5 @@
+<module_names>
+  <module_name default="tile_0__1_" given="tile_io_bottom"/>
+  <module_name default="tile_1__1_" given="tile_clb"/>
+  <module_name default="tile_1__0_" given="tile_io_left"/>
+</module_names>

libs/libnamemanager/example/example_module_names_expect_errors.xml

@@ -0,0 +1,6 @@
+<module_names>
+  <module_name default="tile_0__1_" given="tile_io_bottom"/>
+  <module_name default="tile_1__1_" given="tile_clb"/>
+  <module_name default="tile_1__0_" given="tile_io_left"/>
+  <module_name default="tile_3__0_" given="tile_io_left"/>
+</module_names>

libs/libnamemanager/src/base/module_name_map.cpp

@@ -0,0 +1,74 @@
+/******************************************************************************
+ * Memember functions for data structure ModuleNameMap
+ ******************************************************************************/
+/* Headers from vtrutil library */
+#include "module_name_map.h"
+
+#include <algorithm>
+
+#include "command_exit_codes.h"
+#include "vtr_assert.h"
+#include "vtr_log.h"
+#include "vtr_time.h"
+
+/* begin namespace openfpga */
+namespace openfpga {
+
+/**************************************************
+ * Public Accessors
+ *************************************************/
+std::string ModuleNameMap::name(const std::string& tag) const {
+  auto result = tag2names_.find(tag);
+  if (result == tag2names_.end()) {
+    VTR_LOG_ERROR("The given built-in name '%s' does not exist!\n",
+                  tag.c_str());
+    return std::string();
+  }
+  return result->second;
+}
+
+bool ModuleNameMap::name_exist(const std::string& tag) const {
+  auto result = tag2names_.find(tag);
+  return result != tag2names_.end();
+}
+
+std::vector<std::string> ModuleNameMap::tags() const {
+  std::vector<std::string> keys;
+  for (auto const& element : tag2names_) {
+    keys.push_back(element.first);
+  }
+  return keys;
+}
+
+int ModuleNameMap::set_tag_to_name_pair(const std::string& tag,
+                                        const std::string& name) {
+  /*  tagA <--x--> nameA
+   *        |
+   *        +----> nameB
+   *  tagB <--x--> nameB
+   * Scenarios to be considered:
+   * - Remove the double links between tagA and nameA
+   * - nameB should NOT be mapped to any other tags!
+   */
+  auto result = name2tags_.find(name);
+  if (result != name2tags_.end() && result->second != tag) {
+    VTR_LOG_ERROR(
+      "The customized name '%s' has already been mapped to a built-in name "
+      "'%s'! Fail to bind it to a new built-in name '%s'\n",
+      name.c_str(), result->second.c_str(), tag.c_str());
+    return CMD_EXEC_FATAL_ERROR;
+  }
+  /* Clean up */
+  name2tags_.erase(name);
+  /* Create double link */
+  name2tags_[name] = tag;
+  tag2names_[tag] = name;
+  return CMD_EXEC_SUCCESS;
+}
+
+void ModuleNameMap::clear() {
+  tag2names_.clear();
+  name2tags_.clear();
+}
+
+} /* end namespace openfpga */

libs/libnamemanager/src/base/module_name_map.h

@@ -0,0 +1,46 @@
+#ifndef MODULE_NAME_MAP_H
+#define MODULE_NAME_MAP_H
+
+/********************************************************************
+ * Include header files required by the data structure definition
+ *******************************************************************/
+#include <map>
+#include <string>
+#include <vector>
+
+/* Begin namespace openfpga */
+namespace openfpga {
+
+/**
+ * @brief Module name map is a data structure to show mapping between a tag
+ * (built-in name) and customized names (may be given by users)
+ */
+class ModuleNameMap {
+ public: /* Public accessors */
+  /** @brief Get customized name with a given tag */
+  std::string name(const std::string& tag) const;
+  /** @brief Check if a name does exist with a given tag. Return true if there
+   * is a tag-to-name mapping */
+  bool name_exist(const std::string& tag) const;
+  /** @brief return a list of all the current keys */
+  std::vector<std::string> tags() const;
+
+ public: /* Public mutators */
+  /** @brief Create the one-on-one mapping between an built-in name and a
+   * customized name. Return 0 for success, return 1 for fail */
+  int set_tag_to_name_pair(const std::string& tag, const std::string& name);
+  /** @brief Reset to empty status. Clear all the storage */
+  void clear();
+
+ private: /* Internal Data */
+  /* built-in name -> customized_name
+   * Create a double link to check any customized name is mapped to more than 1
+   * built-in name!
+   */
+  std::map<std::string, std::string> tag2names_;
+  std::map<std::string, std::string> name2tags_;
+};
+
+} /* End namespace openfpga*/
+
+#endif

libs/libnamemanager/src/io/module_name_map_xml_constants.h

@@ -0,0 +1,11 @@
+#ifndef MODULE_NAME_MAP_XML_CONSTANTS_H
+#define MODULE_NAME_MAP_XML_CONSTANTS_H
+
+/* Constants required by XML parser */
+
+constexpr const char* XML_MODULE_NAMES_ROOT_NAME = "module_names";
+constexpr const char* XML_MODULE_NAME_NODE_NAME = "module_name";
+constexpr const char* XML_MODULE_NAME_ATTRIBUTE_DEFAULT = "default";
+constexpr const char* XML_MODULE_NAME_ATTRIBUTE_GIVEN = "given";
+
+#endif

libs/libnamemanager/src/io/read_xml_module_name_map.cpp

@@ -0,0 +1,79 @@
+/********************************************************************
+ * This file includes the top-level function of this library
+ * which reads an XML of clock network file to the associated
+ * data structures
+ *******************************************************************/
+#include <string>
+
+/* Headers from pugi XML library */
+#include "pugixml.hpp"
+#include "pugixml_util.hpp"
+
+/* Headers from vtr util library */
+#include "vtr_assert.h"
+#include "vtr_log.h"
+#include "vtr_time.h"
+
+/* Headers from libarchfpga */
+#include "arch_error.h"
+#include "command_exit_codes.h"
+#include "module_name_map_xml_constants.h"
+#include "read_xml_module_name_map.h"
+#include "read_xml_util.h"
+
+namespace openfpga {  // Begin namespace openfpga
+
+/********************************************************************
+ * Parse XML codes of a <port> to an object of I/O naming
+ *******************************************************************/
+static int read_xml_module_name_binding(pugi::xml_node& xml_binding,
+                                        const pugiutil::loc_data& loc_data,
+                                        ModuleNameMap& module_name_map) {
+  std::string default_name =
+    get_attribute(xml_binding, XML_MODULE_NAME_ATTRIBUTE_DEFAULT, loc_data)
+      .as_string();
+  std::string given_name =
+    get_attribute(xml_binding, XML_MODULE_NAME_ATTRIBUTE_GIVEN, loc_data)
+      .as_string();
+
+  return module_name_map.set_tag_to_name_pair(default_name, given_name);
+}
+
+/********************************************************************
+ * Parse XML codes about <ports> to an object of ClockNetwork
+ *******************************************************************/
+int read_xml_module_name_map(const char* fname,
+                             ModuleNameMap& module_name_map) {
+  vtr::ScopedStartFinishTimer timer("Read module rename rules");
+
+  int status = CMD_EXEC_SUCCESS;
+
+  /* Parse the file */
+  pugi::xml_document doc;
+  pugiutil::loc_data loc_data;
+
+  try {
+    loc_data = pugiutil::load_xml(doc, fname);
+
+    pugi::xml_node xml_root =
+      get_single_child(doc, XML_MODULE_NAMES_ROOT_NAME, loc_data);
+
+    for (pugi::xml_node xml_binding : xml_root.children()) {
+      /* Error out if the XML child has an invalid name! */
+      if (xml_binding.name() != std::string(XML_MODULE_NAME_NODE_NAME)) {
+        bad_tag(xml_binding, loc_data, xml_root, {XML_MODULE_NAME_NODE_NAME});
+      }
+      status =
+        read_xml_module_name_binding(xml_binding, loc_data, module_name_map);
+      if (status != CMD_EXEC_SUCCESS) {
+        return CMD_EXEC_FATAL_ERROR;
+      }
+    }
+  } catch (pugiutil::XmlError& e) {
+    archfpga_throw(fname, e.line(), "%s", e.what());
+  }
+
+  return status;
+}
+
+}  // End of namespace openfpga

libs/libnamemanager/src/io/read_xml_module_name_map.h

@@ -0,0 +1,21 @@
+#ifndef READ_XML_MODULE_NAME_MAP_H
+#define READ_XML_MODULE_NAME_MAP_H
+
+/********************************************************************
+ * Include header files that are required by function declaration
+ *******************************************************************/
+#include "module_name_map.h"
+#include "pugixml.hpp"
+#include "pugixml_util.hpp"
+
+/********************************************************************
+ * Function declaration
+ *******************************************************************/
+
+namespace openfpga {  // Begin namespace openfpga
+
+int read_xml_module_name_map(const char* fname, ModuleNameMap& module_name_map);
+
+}  // End of namespace openfpga
+
+#endif

libs/libnamemanager/src/io/write_xml_module_name_map.cpp

@@ -0,0 +1,137 @@
+/********************************************************************
+ * This file includes functions that outputs a clock network object to XML
+ *format
+ *******************************************************************/
+/* Headers from system goes first */
+#include <algorithm>
+#include <chrono>
+#include <ctime>
+#include <string>
+
+/* Headers from vtr util library */
+#include "vtr_assert.h"
+#include "vtr_log.h"
+#include "vtr_time.h"
+
+/* Headers from openfpga util library */
+#include "openfpga_digest.h"
+
+/* Headers from arch openfpga library */
+#include "write_xml_utils.h"
+
+/* Headers from pin constraint library */
+#include "module_name_map_xml_constants.h"
+#include "write_xml_module_name_map.h"
+
+namespace openfpga {  // Begin namespace openfpga
+
+/********************************************************************
+ * This function write header information to a bitstream file
+ *******************************************************************/
+static void write_xml_module_name_map_file_head(
+  std::fstream& fp, const bool& include_time_stamp) {
+  valid_file_stream(fp);
+
+  fp << "<!--" << std::endl;
+  fp << "\t- Module Naming rules" << std::endl;
+  fp << "\t- Author: Xifan TANG" << std::endl;
+  fp << "\t- Organization: RapidFlex" << std::endl;
+
+  if (include_time_stamp) {
+    auto end = std::chrono::system_clock::now();
+    std::time_t end_time = std::chrono::system_clock::to_time_t(end);
+    fp << "\t- Date: " << std::ctime(&end_time);
+  }
+
+  fp << "-->" << std::endl;
+  fp << std::endl;
+}
+
+/********************************************************************
+ * A writer to output a I/O name mapping to XML format
+ *
+ * Return 0 if successful
+ * Return 1 if there are more serious bugs in the architecture
+ * Return 2 if fail when creating files
+ *******************************************************************/
+static int write_xml_module_name_binding(std::fstream& fp,
+                                         const ModuleNameMap& module_name_map,
+                                         const std::string& built_in_name) {
+  /* Validate the file stream */
+  if (false == openfpga::valid_file_stream(fp)) {
+    return 2;
+  }
+
+  openfpga::write_tab_to_file(fp, 1);
+  fp << "<" << XML_MODULE_NAME_NODE_NAME << "";
+  write_xml_attribute(fp, XML_MODULE_NAME_ATTRIBUTE_DEFAULT,
+                      built_in_name.c_str());
+
+  std::string given_name = module_name_map.name(built_in_name);
+  if (given_name.empty()) {
+    VTR_LOG_ERROR("Default name '%s' is not mapped to any given name!\n",
+                  built_in_name.c_str());
+    return 1;
+  }
+  write_xml_attribute(fp, XML_MODULE_NAME_ATTRIBUTE_GIVEN, given_name.c_str());
+  fp << ">"
+     << "\n";
+
+  return 0;
+}
+
+/********************************************************************
+ * A writer to output an object to XML format
+ *
+ * Return 0 if successful
+ * Return 1 if there are more serious bugs in the architecture
+ * Return 2 if fail when creating files
+ *******************************************************************/
+int write_xml_module_name_map(const char* fname,
+                              const ModuleNameMap& module_name_map,
+                              const bool& include_time_stamp,
+                              const bool& verbose) {
+  vtr::ScopedStartFinishTimer timer("Write module renaming rules");
+
+  /* Create a file handler */
+  std::fstream fp;
+  /* Open the file stream */
+  fp.open(std::string(fname), std::fstream::out | std::fstream::trunc);
+
+  /* Validate the file stream */
+  openfpga::check_file_stream(fname, fp);
+
+  write_xml_module_name_map_file_head(fp, include_time_stamp);
+
+  /* Write the root node */
+  fp << "<" << XML_MODULE_NAMES_ROOT_NAME;
+  fp << ">"
+     << "\n";
+
+  int err_code = 0;
+
+  /* Write each port */
+  size_t cnt = 0;
+  for (std::string built_in_name : module_name_map.tags()) {
+    /* Write bus */
+    err_code =
+      write_xml_module_name_binding(fp, module_name_map, built_in_name);
+    if (0 != err_code) {
+      return err_code;
+    }
+    cnt++;
+  }
+
+  /* Finish writing the root node */
+  fp << "</" << XML_MODULE_NAMES_ROOT_NAME << ">"
+     << "\n";
+
+  /* Close the file stream */
+  fp.close();
+
+  VTR_LOGV(verbose, "Outputted %lu naming rules.\n", cnt);
+
+  return err_code;
+}
+
+}  // End of namespace openfpga

libs/libnamemanager/src/io/write_xml_module_name_map.h

@@ -0,0 +1,23 @@
+#ifndef WRITE_XML_MODULE_NAME_MAP_H
+#define WRITE_XML_MODULE_NAME_MAP_H
+
+/********************************************************************
+ * Include header files that are required by function declaration
+ *******************************************************************/
+#include <fstream>
+
+#include "module_name_map.h"
+
+/********************************************************************
+ * Function declaration
+ *******************************************************************/
+namespace openfpga {  // Begin namespace openfpga
+
+int write_xml_module_name_map(const char* fname,
+                              const ModuleNameMap& module_name_map,
+                              const bool& include_time_stamp,
+                              const bool& verbose);
+
+}  // End of namespace openfpga
+
+#endif

libs/libnamemanager/test/xml_io_module_name_map.cpp

@@ -0,0 +1,39 @@
+/********************************************************************
+ * Unit test functions to validate the correctness of
+ * 1. parser of data structures
+ * 2. writer of data structures
+ *******************************************************************/
+/* Headers from vtrutils */
+#include "vtr_assert.h"
+#include "vtr_log.h"
+
+/* Headers from readarchopenfpga */
+#include "read_xml_module_name_map.h"
+#include "write_xml_module_name_map.h"
+
+int main(int argc, const char** argv) {
+  /* Ensure we have only one or two argument */
+  VTR_ASSERT((2 == argc) || (3 == argc));
+
+  int status = 0;
+
+  /* Parse the circuit library from an XML file */
+  openfpga::ModuleNameMap module_name_map;
+  status = openfpga::read_xml_module_name_map(argv[1], module_name_map);
+  if (status != 0) {
+    return status;
+  }
+  VTR_LOG("Parsed %lu default names from XML.\n",
+          module_name_map.tags().size());
+
+  /* Output the bus group to an XML file
+   * This is optional only used when there is a second argument
+   */
+  if (3 <= argc) {
+    status =
+      openfpga::write_xml_module_name_map(argv[2], module_name_map, true, true);
+    VTR_LOG("Write the module name mapping to an XML file: %s.\n", argv[2]);
+  }
+
+  return status;
+}

openfpga/CMakeLists.txt

@@ -41,7 +41,7 @@ target_link_libraries(libopenfpga
                       libpcf
                       libvtrutil
                       libbusgroup
-                      libionamemap
+                      libnamemanager
                       libtileconfig
                       libpugixml
                       libvpr)

openfpga/src/base/openfpga_bitstream_template.h

@@ -73,7 +73,8 @@ int build_fabric_bitstream_template(T& openfpga_ctx, const Command& cmd,
   /* Build fabric bitstream here */
   openfpga_ctx.mutable_fabric_bitstream() = build_fabric_dependent_bitstream(
     openfpga_ctx.bitstream_manager(), openfpga_ctx.module_graph(),
-    openfpga_ctx.arch().circuit_lib, openfpga_ctx.arch().config_protocol,
+    openfpga_ctx.module_name_map(), openfpga_ctx.arch().circuit_lib,
+    openfpga_ctx.arch().config_protocol,
     cmd_context.option_enable(cmd, opt_verbose));
 
   /* TODO: should identify the error code from internal function execution */

openfpga/src/base/openfpga_build_fabric_template.h

@@ -18,9 +18,12 @@
 #include "openfpga_naming.h"
 #include "read_xml_fabric_key.h"
 #include "read_xml_io_name_map.h"
+#include "read_xml_module_name_map.h"
 #include "read_xml_tile_config.h"
+#include "rename_modules.h"
 #include "vtr_log.h"
 #include "vtr_time.h"
+#include "write_xml_module_name_map.h"
 
 /* begin namespace openfpga */
 namespace openfpga {
@@ -103,6 +106,8 @@ int build_fabric_template(T& openfpga_ctx, const Command& cmd,
   CommandOptionId opt_load_fabric_key = cmd.option("load_fabric_key");
   CommandOptionId opt_group_tile = cmd.option("group_tile");
   CommandOptionId opt_group_config_block = cmd.option("group_config_block");
+  CommandOptionId opt_name_module_using_index =
+    cmd.option("name_module_using_index");
   CommandOptionId opt_verbose = cmd.option("verbose");
 
   /* Report conflicts with options:
@@ -173,12 +178,14 @@ int build_fabric_template(T& openfpga_ctx, const Command& cmd,
   curr_status = build_device_module_graph(
     openfpga_ctx.mutable_module_graph(), openfpga_ctx.mutable_decoder_lib(),
     openfpga_ctx.mutable_blwl_shift_register_banks(),
-    openfpga_ctx.mutable_fabric_tile(), const_cast<const T&>(openfpga_ctx),
-    g_vpr_ctx.device(), cmd_context.option_enable(cmd, opt_frame_view),
+    openfpga_ctx.mutable_fabric_tile(), openfpga_ctx.mutable_module_name_map(),
+    const_cast<const T&>(openfpga_ctx), g_vpr_ctx.device(),
+    cmd_context.option_enable(cmd, opt_frame_view),
     cmd_context.option_enable(cmd, opt_compress_routing),
     cmd_context.option_enable(cmd, opt_duplicate_grid_pin),
     predefined_fabric_key, tile_config,
     cmd_context.option_enable(cmd, opt_group_config_block),
+    cmd_context.option_enable(cmd, opt_name_module_using_index),
     cmd_context.option_enable(cmd, opt_gen_random_fabric_key),
     cmd_context.option_enable(cmd, opt_verbose));
 
@@ -278,8 +285,8 @@ int write_fabric_hierarchy_template(const T& openfpga_ctx, const Command& cmd,
 
   /* Write hierarchy to a file */
   return write_fabric_hierarchy_to_text_file(
-    openfpga_ctx.module_graph(), hie_file_name, size_t(depth),
-    cmd_context.option_enable(cmd, opt_verbose));
+    openfpga_ctx.module_graph(), openfpga_ctx.module_name_map(), hie_file_name,
+    size_t(depth), cmd_context.option_enable(cmd, opt_verbose));
 }
 
 /********************************************************************
@@ -332,8 +339,65 @@ int add_fpga_core_to_fabric_template(T& openfpga_ctx, const Command& cmd,
   }
 
   return add_fpga_core_to_device_module_graph(
-    openfpga_ctx.mutable_module_graph(), openfpga_ctx.io_name_map(),
-    core_inst_name, frame_view, verbose_output);
+    openfpga_ctx.mutable_module_graph(), openfpga_ctx.mutable_module_name_map(),
+    openfpga_ctx.io_name_map(), core_inst_name, frame_view, verbose_output);
+}
+
+/********************************************************************
+ * Rename modules in module graph with a set of given rules
+ *******************************************************************/
+template <class T>
+int rename_modules_template(T& openfpga_ctx, const Command& cmd,
+                            const CommandContext& cmd_context) {
+  CommandOptionId opt_verbose = cmd.option("verbose");
+
+  /* Check the option '--file' is enabled or not
+   * Actually, it must be enabled as the shell interface will check
+   * before reaching this fuction
+   */
+  CommandOptionId opt_file = cmd.option("file");
+  VTR_ASSERT(true == cmd_context.option_enable(cmd, opt_file));
+  VTR_ASSERT(false == cmd_context.option_value(cmd, opt_file).empty());
+
+  std::string file_name = cmd_context.option_value(cmd, opt_file);
+
+  if (CMD_EXEC_SUCCESS !=
+      read_xml_module_name_map(file_name.c_str(),
+                               openfpga_ctx.mutable_module_name_map())) {
+    return CMD_EXEC_FATAL_ERROR;
+  }
+
+  /* Write hierarchy to a file */
+  return rename_fabric_modules(openfpga_ctx.mutable_module_graph(),
+                               openfpga_ctx.module_name_map(),
+                               cmd_context.option_enable(cmd, opt_verbose));
+}
+
+/********************************************************************
+ * Write module naming rules to a file
+ *******************************************************************/
+template <class T>
+int write_module_naming_rules_template(const T& openfpga_ctx,
+                                       const Command& cmd,
+                                       const CommandContext& cmd_context) {
+  CommandOptionId opt_verbose = cmd.option("verbose");
+  CommandOptionId opt_no_time_stamp = cmd.option("no_time_stamp");
+
+  /* Check the option '--file' is enabled or not
+   * Actually, it must be enabled as the shell interface will check
+   * before reaching this fuction
+   */
+  CommandOptionId opt_file = cmd.option("file");
+  VTR_ASSERT(true == cmd_context.option_enable(cmd, opt_file));
+  VTR_ASSERT(false == cmd_context.option_value(cmd, opt_file).empty());
+
+  std::string file_name = cmd_context.option_value(cmd, opt_file);
+
+  /* Write hierarchy to a file */
+  return write_xml_module_name_map(
+    file_name.c_str(), openfpga_ctx.module_name_map(),
+    !cmd_context.option_enable(cmd, opt_no_time_stamp),
+    cmd_context.option_enable(cmd, opt_verbose));
 }
 
 } /* end namespace openfpga */

openfpga/src/base/openfpga_context.h

@@ -15,6 +15,7 @@
 #include "io_name_map.h"
 #include "memory_bank_shift_register_banks.h"
 #include "module_manager.h"
+#include "module_name_map.h"
 #include "mux_library.h"
 #include "netlist_manager.h"
 #include "openfpga_arch.h"
@@ -107,6 +108,9 @@ class OpenfpgaContext : public Context {
     return io_location_map_;
   }
   const openfpga::IoNameMap& io_name_map() const { return io_name_map_; }
+  const openfpga::ModuleNameMap& module_name_map() const {
+    return module_name_map_;
+  }
   const openfpga::FabricTile& fabric_tile() const { return fabric_tile_; }
   const openfpga::FabricGlobalPortInfo& fabric_global_port_info() const {
     return fabric_global_port_info_;
@@ -167,6 +171,9 @@ class OpenfpgaContext : public Context {
     return io_location_map_;
   }
   openfpga::IoNameMap& mutable_io_name_map() { return io_name_map_; }
+  openfpga::ModuleNameMap& mutable_module_name_map() {
+    return module_name_map_;
+  }
   openfpga::FabricTile& mutable_fabric_tile() { return fabric_tile_; }
   openfpga::FabricGlobalPortInfo& mutable_fabric_global_port_info() {
     return fabric_global_port_info_;
@@ -223,6 +230,7 @@ class OpenfpgaContext : public Context {
   openfpga::ModuleManager module_graph_;
   openfpga::IoLocationMap io_location_map_;
   openfpga::IoNameMap io_name_map_;
+  openfpga::ModuleNameMap module_name_map_;
   openfpga::FabricTile fabric_tile_;
   openfpga::FabricGlobalPortInfo fabric_global_port_info_;
 

openfpga/src/base/openfpga_naming.cpp

@@ -503,6 +503,13 @@ std::string generate_switch_block_module_name(
                      std::string("_"));
 }
 
+/*********************************************************************
+ * Generate the module name for a switch block with a given index
+ *********************************************************************/
+std::string generate_switch_block_module_name_using_index(const size_t& index) {
+  return std::string("sb_" + std::to_string(index) + std::string("_"));
+}
+
 /*********************************************************************
  * Generate the module name for a tile module with a given coordinate
  *********************************************************************/
@@ -511,6 +518,13 @@ std::string generate_tile_module_name(const vtr::Point<size_t>& tile_coord) {
                      std::to_string(tile_coord.y()) + "_");
 }
 
+/*********************************************************************
+ * Generate the module name for a tile module with a given index
+ *********************************************************************/
+std::string generate_tile_module_name_using_index(const size_t& index) {
+  return std::string("tile_" + std::to_string(index) + "_");
+}
+
 /*********************************************************************
  * Generate the port name for a tile. Note that use the index to make the tile
  *port name unique!
@@ -560,6 +574,27 @@ std::string generate_connection_block_module_name(
                      std::string("_"));
 }
 
+/*********************************************************************
+ * Generate the module name for a connection block with a given index
+ *********************************************************************/
+std::string generate_connection_block_module_name_using_index(
+  const t_rr_type& cb_type, const size_t& index) {
+  std::string prefix("cb");
+  switch (cb_type) {
+    case CHANX:
+      prefix += std::string("x_");
+      break;
+    case CHANY:
+      prefix += std::string("y_");
+      break;
+    default:
+      VTR_LOG_ERROR("Invalid type of connection block!\n");
+      exit(1);
+  }
+
+  return std::string(prefix + std::to_string(index) + std::string("_"));
+}
+
 /*********************************************************************
  * Generate the port name for a grid in top-level netlists, i.e., full FPGA
  *fabric This function will generate a full port name including coordinates so

openfpga/src/base/openfpga_naming.h

@@ -108,11 +108,18 @@ std::string generate_routing_track_middle_output_port_name(
 std::string generate_switch_block_module_name(
   const vtr::Point<size_t>& coordinate);
 
+std::string generate_switch_block_module_name_using_index(const size_t& index);
+
 std::string generate_connection_block_module_name(
   const t_rr_type& cb_type, const vtr::Point<size_t>& coordinate);
 
+std::string generate_connection_block_module_name_using_index(
+  const t_rr_type& cb_type, const size_t& index);
+
 std::string generate_tile_module_name(const vtr::Point<size_t>& tile_coord);
 
+std::string generate_tile_module_name_using_index(const size_t& index);
+
 std::string generate_tile_module_port_name(const std::string& prefix,
                                            const std::string& port_name);
 

openfpga/src/base/openfpga_setup_command_template.h

@@ -395,6 +395,11 @@ ShellCommandId add_build_fabric_command_template(
   shell_cmd.add_option("duplicate_grid_pin", false,
                        "Duplicate the pins on the same side of a grid");
 
+  /* Add an option '--name_module_using_index' */
+  shell_cmd.add_option("name_module_using_index", false,
+                       "Use index to name modules, such as cbx_0_, rather than "
+                       "coordinates, such as cbx_1__0_");
+
   /* Add an option '--load_fabric_key' */
   CommandOptionId opt_load_fkey = shell_cmd.add_option(
     "load_fabric_key", false, "load the fabric key from the given file");
@@ -786,6 +791,73 @@ ShellCommandId add_write_fabric_key_command_template(
   return shell_cmd_id;
 }
 
+/********************************************************************
+ * - Add a command to Shell environment: rename_modules
+ * - Add associated options
+ * - Add command dependency
+ *******************************************************************/
+template <class T>
+ShellCommandId add_rename_modules_command_template(
+  openfpga::Shell<T>& shell, const ShellCommandClassId& cmd_class_id,
+  const std::vector<ShellCommandId>& dependent_cmds, const bool& hidden) {
+  Command shell_cmd("rename_modules");
+  /* Add an option '--file' in short '-f'*/
+  CommandOptionId opt_file = shell_cmd.add_option(
+    "file", true, "file path to the XML file that contains renaming rules");
+  shell_cmd.set_option_short_name(opt_file, "f");
+  shell_cmd.set_option_require_value(opt_file, openfpga::OPT_STRING);
+
+  shell_cmd.add_option("verbose", false, "Show verbose outputs");
+
+  /* Add command to the Shell */
+  ShellCommandId shell_cmd_id = shell.add_command(
+    shell_cmd, "Rename modules with a set of given rules", hidden);
+  shell.set_command_class(shell_cmd_id, cmd_class_id);
+  shell.set_command_execute_function(shell_cmd_id, rename_modules_template<T>);
+
+  /* Add command dependency to the Shell */
+  shell.set_command_dependency(shell_cmd_id, dependent_cmds);
+
+  return shell_cmd_id;
+}
+
+/********************************************************************
+ * - Add a command to Shell environment: write_module_naming_rules
+ * - Add associated options
+ * - Add command dependency
+ *******************************************************************/
+template <class T>
+ShellCommandId add_write_module_naming_rules_command_template(
+  openfpga::Shell<T>& shell, const ShellCommandClassId& cmd_class_id,
+  const std::vector<ShellCommandId>& dependent_cmds, const bool& hidden) {
+  Command shell_cmd("write_module_naming_rules");
+  /* Add an option '--file' in short '-f'*/
+  CommandOptionId opt_file = shell_cmd.add_option(
+    "file", true, "file path to the XML file that contains renaming rules");
+  shell_cmd.set_option_short_name(opt_file, "f");
+  shell_cmd.set_option_require_value(opt_file, openfpga::OPT_STRING);
+
+  /* Add an option '--no_time_stamp' */
+  shell_cmd.add_option("no_time_stamp", false,
+                       "Do not print time stamp in output files");
+
+  shell_cmd.add_option("verbose", false, "Show verbose outputs");
+
+  /* Add command to the Shell */
+  ShellCommandId shell_cmd_id = shell.add_command(
+    shell_cmd,
+    "Output the naming rules for each module of an FPGA fabric to a given file",
+    hidden);
+  shell.set_command_class(shell_cmd_id, cmd_class_id);
+  shell.set_command_const_execute_function(
+    shell_cmd_id, write_module_naming_rules_template<T>);
+
+  /* Add command dependency to the Shell */
+  shell.set_command_dependency(shell_cmd_id, dependent_cmds);
+
+  return shell_cmd_id;
+}
+
 template <class T>
 void add_setup_command_templates(openfpga::Shell<T>& shell,
                                  const bool& hidden = false) {
@@ -1005,6 +1077,27 @@ void add_setup_command_templates(openfpga::Shell<T>& shell,
   add_write_fabric_io_info_command_template<T>(
     shell, openfpga_setup_cmd_class, cmd_dependency_write_fabric_io_info,
     hidden);
+
+  /********************************
+   * Command 'rename_modules'
+   */
+  /* The 'rename_modules' command should NOT be executed before
+   * 'build_fabric' */
+  std::vector<ShellCommandId> cmd_dependency_rename_modules;
+  cmd_dependency_rename_modules.push_back(build_fabric_cmd_id);
+  add_rename_modules_command_template<T>(shell, openfpga_setup_cmd_class,
+                                         cmd_dependency_rename_modules, hidden);
+
+  /********************************
+   * Command 'write_module_naming_rules'
+   */
+  /* The 'write_module_naming_rules' command should NOT be executed before
+   * 'build_fabric' */
+  std::vector<ShellCommandId> cmd_dependency_write_module_naming_rules;
+  cmd_dependency_write_module_naming_rules.push_back(build_fabric_cmd_id);
+  add_write_module_naming_rules_command_template<T>(
+    shell, openfpga_setup_cmd_class, cmd_dependency_write_module_naming_rules,
+    hidden);
 }
 
 } /* end namespace openfpga */

openfpga/src/base/openfpga_verilog_template.h

@@ -63,7 +63,7 @@ int write_fabric_verilog_template(T& openfpga_ctx, const Command& cmd,
     openfpga_ctx.blwl_shift_register_banks(), openfpga_ctx.arch().circuit_lib,
     openfpga_ctx.mux_lib(), openfpga_ctx.decoder_lib(), g_vpr_ctx.device(),
     openfpga_ctx.vpr_device_annotation(), openfpga_ctx.device_rr_gsb(),
-    openfpga_ctx.fabric_tile(), options);
+    openfpga_ctx.fabric_tile(), openfpga_ctx.module_name_map(), options);
 }
 
 /********************************************************************
@@ -138,7 +138,7 @@ int write_full_testbench_template(const T& openfpga_ctx, const Command& cmd,
     g_vpr_ctx.atom(), g_vpr_ctx.placement(), pin_constraints, bus_group,
     cmd_context.option_value(cmd, opt_bitstream),
     openfpga_ctx.io_location_map(), openfpga_ctx.io_name_map(),
-    openfpga_ctx.fabric_global_port_info(),
+    openfpga_ctx.module_name_map(), openfpga_ctx.fabric_global_port_info(),
     openfpga_ctx.vpr_netlist_annotation(), openfpga_ctx.arch().circuit_lib,
     openfpga_ctx.simulation_setting(), openfpga_ctx.arch().config_protocol,
     options);
@@ -212,7 +212,7 @@ int write_preconfigured_fabric_wrapper_template(
     openfpga_ctx.module_graph(), openfpga_ctx.bitstream_manager(),
     g_vpr_ctx.atom(), g_vpr_ctx.placement(), pin_constraints, bus_group,
     openfpga_ctx.io_location_map(), openfpga_ctx.io_name_map(),
-    openfpga_ctx.fabric_global_port_info(),
+    openfpga_ctx.module_name_map(), openfpga_ctx.fabric_global_port_info(),
     openfpga_ctx.vpr_netlist_annotation(), openfpga_ctx.arch().circuit_lib,
     openfpga_ctx.arch().config_protocol, options);
 }
@@ -273,7 +273,8 @@ int write_mock_fpga_wrapper_template(const T& openfpga_ctx, const Command& cmd,
   return fpga_verilog_mock_fpga_wrapper(
     openfpga_ctx.module_graph(), g_vpr_ctx.atom(), g_vpr_ctx.placement(),
     pin_constraints, bus_group, openfpga_ctx.io_location_map(),
-    openfpga_ctx.io_name_map(), openfpga_ctx.fabric_global_port_info(),
+    openfpga_ctx.io_name_map(), openfpga_ctx.module_name_map(),
+    openfpga_ctx.fabric_global_port_info(),
     openfpga_ctx.vpr_netlist_annotation(), options);
 }
 
@@ -334,7 +335,8 @@ int write_preconfigured_testbench_template(const T& openfpga_ctx,
   }
 
   return fpga_verilog_preconfigured_testbench(
-    openfpga_ctx.module_graph(), g_vpr_ctx.atom(), pin_constraints, bus_group,
+    openfpga_ctx.module_graph(), openfpga_ctx.module_name_map(),
+    g_vpr_ctx.atom(), pin_constraints, bus_group,
     openfpga_ctx.fabric_global_port_info(),
     openfpga_ctx.vpr_netlist_annotation(), openfpga_ctx.simulation_setting(),
     options);

openfpga/src/fabric/build_device_module.cpp

@@ -23,6 +23,7 @@
 #include "build_wire_modules.h"
 #include "command_exit_codes.h"
 #include "openfpga_naming.h"
+#include "rename_modules.h"
 
 /* begin namespace openfpga */
 namespace openfpga {
@@ -34,10 +35,11 @@ namespace openfpga {
 int build_device_module_graph(
   ModuleManager& module_manager, DecoderLibrary& decoder_lib,
   MemoryBankShiftRegisterBanks& blwl_sr_banks, FabricTile& fabric_tile,
-  const OpenfpgaContext& openfpga_ctx, const DeviceContext& vpr_device_ctx,
-  const bool& frame_view, const bool& compress_routing,
-  const bool& duplicate_grid_pin, const FabricKey& fabric_key,
-  const TileConfig& tile_config, const bool& group_config_block,
+  ModuleNameMap& module_name_map, const OpenfpgaContext& openfpga_ctx,
+  const DeviceContext& vpr_device_ctx, const bool& frame_view,
+  const bool& compress_routing, const bool& duplicate_grid_pin,
+  const FabricKey& fabric_key, const TileConfig& tile_config,
+  const bool& group_config_block, const bool& name_module_using_index,
   const bool& generate_random_fabric_key, const bool& verbose) {
   vtr::ScopedStartFinishTimer timer("Build fabric module graph");
 
@@ -118,12 +120,13 @@ int build_device_module_graph(
       return status;
     }
     /* Build the modules */
-    build_tile_modules(
-      module_manager, decoder_lib, openfpga_ctx.fabric_tile(),
-      vpr_device_ctx.grid, openfpga_ctx.vpr_device_annotation(),
-      openfpga_ctx.device_rr_gsb(), vpr_device_ctx.rr_graph,
-      openfpga_ctx.arch().circuit_lib, sram_model,
-      openfpga_ctx.arch().config_protocol.type(), frame_view, verbose);
+    build_tile_modules(module_manager, decoder_lib, openfpga_ctx.fabric_tile(),
+                       vpr_device_ctx.grid,
+                       openfpga_ctx.vpr_device_annotation(),
+                       openfpga_ctx.device_rr_gsb(), vpr_device_ctx.rr_graph,
+                       openfpga_ctx.arch().circuit_lib, sram_model,
+                       openfpga_ctx.arch().config_protocol.type(),
+                       name_module_using_index, frame_view, verbose);
   }
 
   /* Build FPGA fabric top-level module */
@@ -134,8 +137,9 @@ int build_device_module_graph(
     openfpga_ctx.arch().tile_annotations, vpr_device_ctx.rr_graph,
     openfpga_ctx.device_rr_gsb(), openfpga_ctx.tile_direct(),
     openfpga_ctx.arch().arch_direct, openfpga_ctx.arch().config_protocol,
-    sram_model, fabric_tile, frame_view, compress_routing, duplicate_grid_pin,
-    fabric_key, generate_random_fabric_key, group_config_block, verbose);
+    sram_model, fabric_tile, name_module_using_index, frame_view,
+    compress_routing, duplicate_grid_pin, fabric_key,
+    generate_random_fabric_key, group_config_block, verbose);
 
   if (CMD_EXEC_FATAL_ERROR == status) {
     return status;
@@ -151,6 +155,26 @@ int build_device_module_graph(
   rename_primitive_module_port_names(module_manager,
                                      openfpga_ctx.arch().circuit_lib);
 
+  /* Collect module names and initialize module name mapping */
+  status =
+    init_fabric_module_name_map(module_name_map, module_manager, verbose);
+  if (CMD_EXEC_FATAL_ERROR == status) {
+    return status;
+  }
+  if (name_module_using_index) {
+    /* Update module name data */
+    status = update_module_map_name_with_indexing_names(
+      module_name_map, openfpga_ctx.device_rr_gsb(), fabric_tile, verbose);
+    if (CMD_EXEC_FATAL_ERROR == status) {
+      return status;
+    }
+    /* Apply module naming */
+    status = rename_fabric_modules(module_manager, module_name_map, verbose);
+    if (CMD_EXEC_FATAL_ERROR == status) {
+      return status;
+    }
+  }
+
   return status;
 }
 

openfpga/src/fabric/build_device_module.h

@@ -7,6 +7,7 @@
 #include "fabric_key.h"
 #include "fabric_tile.h"
 #include "io_name_map.h"
+#include "module_name_map.h"
 #include "openfpga_context.h"
 #include "tile_config.h"
 #include "vpr_context.h"
@@ -21,10 +22,11 @@ namespace openfpga {
 int build_device_module_graph(
   ModuleManager& module_manager, DecoderLibrary& decoder_lib,
   MemoryBankShiftRegisterBanks& blwl_sr_banks, FabricTile& fabric_tile,
-  const OpenfpgaContext& openfpga_ctx, const DeviceContext& vpr_device_ctx,
-  const bool& frame_view, const bool& compress_routing,
-  const bool& duplicate_grid_pin, const FabricKey& fabric_key,
-  const TileConfig& tile_config, const bool& group_config_block,
+  ModuleNameMap& module_name_map, const OpenfpgaContext& openfpga_ctx,
+  const DeviceContext& vpr_device_ctx, const bool& frame_view,
+  const bool& compress_routing, const bool& duplicate_grid_pin,
+  const FabricKey& fabric_key, const TileConfig& tile_config,
+  const bool& group_config_block, const bool& name_module_using_index,
   const bool& generate_random_fabric_key, const bool& verbose);
 
 } /* end namespace openfpga */

openfpga/src/fabric/build_fpga_core_wrapper_module.cpp

@@ -333,6 +333,7 @@ static int create_fpga_top_module_using_naming_rules(
  * - Create a wrapper module 'fpga_top' on the fpga_core
  *******************************************************************/
 int add_fpga_core_to_device_module_graph(ModuleManager& module_manager,
+                                         ModuleNameMap& module_name_map,
                                          const IoNameMap& io_naming,
                                          const std::string& core_inst_name,
                                          const bool& frame_view,
@@ -340,7 +341,8 @@ int add_fpga_core_to_device_module_graph(ModuleManager& module_manager,
   int status = CMD_EXEC_SUCCESS;
 
   /* Execute the module graph api */
-  std::string top_module_name = generate_fpga_top_module_name();
+  std::string top_module_name =
+    module_name_map.name(generate_fpga_top_module_name());
   ModuleId top_module = module_manager.find_module(top_module_name);
   if (!module_manager.valid_module_id(top_module)) {
     return CMD_EXEC_FATAL_ERROR;
@@ -379,6 +381,17 @@ int add_fpga_core_to_device_module_graph(ModuleManager& module_manager,
   VTR_LOGV(verbose, "Created a wrapper module '%s' on top of '%s'\n",
            top_module_name.c_str(), core_module_name.c_str());
 
+  /* Update module name map */
+  status =
+    module_name_map.set_tag_to_name_pair(core_module_name, core_module_name);
+  if (CMD_EXEC_SUCCESS != status) {
+    VTR_LOG_ERROR(
+      "Failed to register fpga core module '%s' in module name map!\n",
+      core_module_name.c_str());
+    return CMD_EXEC_FATAL_ERROR;
+  }
+  VTR_LOGV(verbose, "Updated module name map\n");
+
   /* Now fpga_core should be the only configurable child under the top-level
    * module */
   module_manager.add_configurable_child(

openfpga/src/fabric/build_fpga_core_wrapper_module.h

@@ -8,6 +8,7 @@
 
 #include "io_name_map.h"
 #include "module_manager.h"
+#include "module_name_map.h"
 
 /********************************************************************
  * Function declaration
@@ -17,6 +18,7 @@
 namespace openfpga {
 
 int add_fpga_core_to_device_module_graph(ModuleManager& module_manager,
+                                         ModuleNameMap& module_name_map,
                                          const IoNameMap& io_naming,
                                          const std::string& core_inst_name,
                                          const bool& frame_view,

openfpga/src/fabric/build_tile_modules.cpp

@@ -66,8 +66,8 @@ static int build_tile_module_port_and_nets_between_sb_and_pb(
   const RRGSB& rr_gsb, const FabricTile& fabric_tile,
   const FabricTileId& fabric_tile_id, const std::vector<size_t>& pb_instances,
   const std::vector<size_t>& sb_instances, const size_t& isb,
-  const bool& compact_routing_hierarchy, const bool& frame_view,
-  const bool& verbose) {
+  const bool& compact_routing_hierarchy, const bool& name_module_using_index,
+  const bool& frame_view, const bool& verbose) {
   /* Skip those Switch blocks that do not exist */
   if (false == rr_gsb.is_sb_exist(rr_graph)) {
     return CMD_EXEC_SUCCESS;
@@ -200,10 +200,15 @@ static int build_tile_module_port_and_nets_between_sb_and_pb(
       } else {
         /* Create a port on the tile module and create the net if required.
          * Create a proper name to avoid naming conflicts */
+        std::string temp_sb_module_name = generate_switch_block_module_name(
+          fabric_tile.sb_coordinates(fabric_tile_id)[isb]);
+        if (name_module_using_index) {
+          temp_sb_module_name = generate_switch_block_module_name_using_index(
+            device_rr_gsb.get_sb_unique_module_index(
+              fabric_tile.sb_coordinates(fabric_tile_id)[isb]));
+        }
         src_grid_port.set_name(generate_tile_module_port_name(
-          generate_switch_block_module_name(
-            fabric_tile.sb_coordinates(fabric_tile_id)[isb]),
-          sink_sb_port.get_name()));
+          temp_sb_module_name, sink_sb_port.get_name()));
         ModulePortId src_tile_port_id = module_manager.add_port(
           tile_module, src_grid_port,
           ModuleManager::e_module_port_type::MODULE_INPUT_PORT);
@@ -296,7 +301,8 @@ static int build_tile_module_port_and_nets_between_cb_and_pb(
   const std::vector<size_t>& pb_instances,
   const std::map<t_rr_type, std::vector<size_t>>& cb_instances,
   const size_t& icb, const bool& compact_routing_hierarchy,
-  const bool& frame_view, const bool& verbose) {
+  const bool& name_module_using_index, const bool& frame_view,
+  const bool& verbose) {
   size_t cb_instance = cb_instances.at(cb_type)[icb];
   /* We could have two different coordinators, one is the instance, the other is
    * the module */
@@ -422,13 +428,18 @@ static int build_tile_module_port_and_nets_between_cb_and_pb(
           }
         }
       } else {
-        /* Create a port on the tile module and create the net if required.
-         * FIXME: Create a proper name to avoid naming conflicts */
+        /* Create a port on the tile module and create the net if required. */
         const RRGSB& cb_inst_rr_gsb = device_rr_gsb.get_gsb(
           fabric_tile.cb_coordinates(fabric_tile_id, cb_type)[icb]);
         std::string cb_instance_name_in_tile =
           generate_connection_block_module_name(
             cb_type, cb_inst_rr_gsb.get_cb_coordinate(cb_type));
+        if (name_module_using_index) {
+          cb_instance_name_in_tile =
+            generate_connection_block_module_name_using_index(
+              cb_type, device_rr_gsb.get_cb_unique_module_index(
+                         cb_type, cb_inst_rr_gsb.get_cb_coordinate(cb_type)));
+        }
         src_cb_port.set_name(generate_tile_module_port_name(
           cb_instance_name_in_tile, src_cb_port.get_name()));
         ModulePortId sink_tile_port_id = module_manager.add_port(
@@ -504,8 +515,8 @@ static int build_tile_module_port_and_nets_between_sb_and_cb(
   const FabricTileId& fabric_tile_id,
   const std::map<t_rr_type, std::vector<size_t>>& cb_instances,
   const std::vector<size_t>& sb_instances, const size_t& isb,
-  const bool& compact_routing_hierarchy, const bool& frame_view,
-  const bool& verbose) {
+  const bool& compact_routing_hierarchy, const bool& name_module_using_index,
+  const bool& frame_view, const bool& verbose) {
   size_t sb_instance = sb_instances[isb];
   /* We could have two different coordinators, one is the instance, the other is
    * the module */
@@ -684,16 +695,20 @@ static int build_tile_module_port_and_nets_between_sb_and_cb(
       /* Create input and output ports */
       std::string chan_input_port_name = generate_sb_module_track_port_name(
         cb_type, side_manager.get_side(), IN_PORT);
-      /* Create a port on the tile module and create the net if required. FIXME:
-       * Create a proper name to avoid naming conflicts  */
+      /* Create a port on the tile module and create the net if required. */
       ModulePortId sb_chan_input_port_id =
         module_manager.find_module_port(sb_module_id, chan_input_port_name);
       BasicPort chan_input_port =
         module_manager.module_port(sb_module_id, sb_chan_input_port_id);
+      std::string temp_sb_module_name = generate_switch_block_module_name(
+        fabric_tile.sb_coordinates(fabric_tile_id)[isb]);
+      if (name_module_using_index) {
+        temp_sb_module_name = generate_switch_block_module_name_using_index(
+          device_rr_gsb.get_sb_unique_module_index(
+            fabric_tile.sb_coordinates(fabric_tile_id)[isb]));
+      }
       chan_input_port.set_name(generate_tile_module_port_name(
-        generate_switch_block_module_name(
-          fabric_tile.sb_coordinates(fabric_tile_id)[isb]),
-        chan_input_port.get_name()));
+        temp_sb_module_name, chan_input_port.get_name()));
       ModulePortId tile_chan_input_port_id = module_manager.add_port(
         tile_module, chan_input_port,
         ModuleManager::e_module_port_type::MODULE_INPUT_PORT);
@@ -724,9 +739,7 @@ static int build_tile_module_port_and_nets_between_sb_and_cb(
       BasicPort chan_output_port =
         module_manager.module_port(sb_module_id, sb_chan_output_port_id);
       chan_output_port.set_name(generate_tile_module_port_name(
-        generate_switch_block_module_name(
-          fabric_tile.sb_coordinates(fabric_tile_id)[isb]),
-        chan_output_port.get_name()));
+        temp_sb_module_name, chan_output_port.get_name()));
       ModulePortId tile_chan_output_port_id = module_manager.add_port(
         tile_module, chan_output_port,
         ModuleManager::e_module_port_type::MODULE_OUTPUT_PORT);
@@ -866,7 +879,8 @@ static int build_tile_module_ports_from_cb(
   const t_rr_type& cb_type,
   const std::map<t_rr_type, std::vector<size_t>>& cb_instances,
   const size_t& icb, const bool& compact_routing_hierarchy,
-  const bool& frame_view, const bool& verbose) {
+  const bool& name_module_using_index, const bool& frame_view,
+  const bool& verbose) {
   int status = CMD_EXEC_SUCCESS;
 
   size_t cb_instance = cb_instances.at(cb_type)[icb];
@@ -909,6 +923,12 @@ static int build_tile_module_ports_from_cb(
   const RRGSB& unique_rr_gsb = device_rr_gsb.get_gsb(cb_coord_in_unique_tile);
   std::string cb_instance_name_in_tile = generate_connection_block_module_name(
     cb_type, unique_rr_gsb.get_cb_coordinate(cb_type));
+  if (name_module_using_index) {
+    cb_instance_name_in_tile =
+      generate_connection_block_module_name_using_index(
+        cb_type, device_rr_gsb.get_cb_unique_module_index(
+                   cb_type, unique_rr_gsb.get_cb_coordinate(cb_type)));
+  }
   vtr::Point<size_t> tile_coord =
     fabric_tile.tile_coordinate(curr_fabric_tile_id);
 
@@ -1182,8 +1202,8 @@ static int build_tile_module_ports_and_nets(
   const FabricTile& fabric_tile, const FabricTileId& fabric_tile_id,
   const std::vector<size_t>& pb_instances,
   const std::map<t_rr_type, std::vector<size_t>>& cb_instances,
-  const std::vector<size_t>& sb_instances, const bool& frame_view,
-  const bool& verbose) {
+  const std::vector<size_t>& sb_instances, const bool& name_module_using_index,
+  const bool& frame_view, const bool& verbose) {
   int status_code = CMD_EXEC_SUCCESS;
 
   /* Get the submodule of Switch blocks one by one, build connections between sb
@@ -1196,7 +1216,8 @@ static int build_tile_module_ports_and_nets(
     status_code = build_tile_module_port_and_nets_between_sb_and_pb(
       module_manager, tile_module, grids, layer, vpr_device_annotation,
       device_rr_gsb, rr_graph_view, rr_gsb, fabric_tile, fabric_tile_id,
-      pb_instances, sb_instances, isb, true, frame_view, verbose);
+      pb_instances, sb_instances, isb, true, name_module_using_index,
+      frame_view, verbose);
     if (status_code != CMD_EXEC_SUCCESS) {
       return CMD_EXEC_FATAL_ERROR;
     }
@@ -1213,7 +1234,8 @@ static int build_tile_module_ports_and_nets(
       status_code = build_tile_module_port_and_nets_between_cb_and_pb(
         module_manager, tile_module, grids, layer, vpr_device_annotation,
         device_rr_gsb, rr_graph_view, rr_gsb, fabric_tile, fabric_tile_id,
-        cb_type, pb_instances, cb_instances, icb, true, frame_view, verbose);
+        cb_type, pb_instances, cb_instances, icb, true, name_module_using_index,
+        frame_view, verbose);
       if (status_code != CMD_EXEC_SUCCESS) {
         return CMD_EXEC_FATAL_ERROR;
       }
@@ -1230,7 +1252,7 @@ static int build_tile_module_ports_and_nets(
     status_code = build_tile_module_port_and_nets_between_sb_and_cb(
       module_manager, tile_module, device_rr_gsb, rr_graph_view, rr_gsb,
       fabric_tile, fabric_tile_id, cb_instances, sb_instances, isb, true,
-      frame_view, verbose);
+      name_module_using_index, frame_view, verbose);
     if (status_code != CMD_EXEC_SUCCESS) {
       return CMD_EXEC_FATAL_ERROR;
     }
@@ -1262,7 +1284,8 @@ static int build_tile_module_ports_and_nets(
       /* Build any ports missing from connection blocks */
       status_code = build_tile_module_ports_from_cb(
         module_manager, tile_module, device_rr_gsb, rr_gsb, fabric_tile,
-        fabric_tile_id, cb_type, cb_instances, icb, true, frame_view, verbose);
+        fabric_tile_id, cb_type, cb_instances, icb, true,
+        name_module_using_index, frame_view, verbose);
       if (status_code != CMD_EXEC_SUCCESS) {
         return CMD_EXEC_FATAL_ERROR;
       }
@@ -1287,7 +1310,8 @@ static int build_tile_module(
   const VprDeviceAnnotation& vpr_device_annotation,
   const DeviceRRGSB& device_rr_gsb, const RRGraphView& rr_graph_view,
   const CircuitLibrary& circuit_lib, const CircuitModelId& sram_model,
-  const e_config_protocol_type& sram_orgz_type, const bool& frame_view,
+  const e_config_protocol_type& sram_orgz_type,
+  const bool& name_module_using_index, const bool& frame_view,
   const bool& verbose) {
   int status_code = CMD_EXEC_SUCCESS;
 
@@ -1434,7 +1458,7 @@ static int build_tile_module(
   status_code = build_tile_module_ports_and_nets(
     module_manager, tile_module, grids, layer, vpr_device_annotation,
     device_rr_gsb, rr_graph_view, fabric_tile, fabric_tile_id, pb_instances,
-    cb_instances, sb_instances, frame_view, verbose);
+    cb_instances, sb_instances, name_module_using_index, frame_view, verbose);
 
   /* Add global ports to the pb_module:
    * This is a much easier job after adding sub modules (instances),
@@ -1506,6 +1530,7 @@ int build_tile_modules(ModuleManager& module_manager,
                        const CircuitLibrary& circuit_lib,
                        const CircuitModelId& sram_model,
                        const e_config_protocol_type& sram_orgz_type,
+                       const bool& name_module_using_index,
                        const bool& frame_view, const bool& verbose) {
   vtr::ScopedStartFinishTimer timer("Build tile modules for the FPGA fabric");
 
@@ -1518,7 +1543,7 @@ int build_tile_modules(ModuleManager& module_manager,
     status_code = build_tile_module(
       module_manager, decoder_lib, fabric_tile, fabric_tile_id, grids, layer,
       vpr_device_annotation, device_rr_gsb, rr_graph_view, circuit_lib,
-      sram_model, sram_orgz_type, frame_view, verbose);
+      sram_model, sram_orgz_type, name_module_using_index, frame_view, verbose);
     if (status_code != CMD_EXEC_SUCCESS) {
       return CMD_EXEC_FATAL_ERROR;
     }

openfpga/src/fabric/build_tile_modules.h

@@ -33,6 +33,7 @@ int build_tile_modules(ModuleManager& module_manager,
                        const CircuitLibrary& circuit_lib,
                        const CircuitModelId& sram_model,
                        const e_config_protocol_type& sram_orgz_type,
+                       const bool& name_module_using_index,
                        const bool& frame_view, const bool& verbose);
 
 } /* end namespace openfpga */

openfpga/src/fabric/build_top_module.cpp

@@ -55,10 +55,10 @@ int build_top_module(
   const DeviceRRGSB& device_rr_gsb, const TileDirect& tile_direct,
   const ArchDirect& arch_direct, const ConfigProtocol& config_protocol,
   const CircuitModelId& sram_model, const FabricTile& fabric_tile,
-  const bool& frame_view, const bool& compact_routing_hierarchy,
-  const bool& duplicate_grid_pin, const FabricKey& fabric_key,
-  const bool& generate_random_fabric_key, const bool& group_config_block,
-  const bool& verbose) {
+  const bool& name_module_using_index, const bool& frame_view,
+  const bool& compact_routing_hierarchy, const bool& duplicate_grid_pin,
+  const FabricKey& fabric_key, const bool& generate_random_fabric_key,
+  const bool& group_config_block, const bool& verbose) {
   vtr::ScopedStartFinishTimer timer("Build FPGA fabric module");
 
   int status = CMD_EXEC_SUCCESS;
@@ -81,13 +81,13 @@ int build_top_module(
       sram_model, frame_view, compact_routing_hierarchy, duplicate_grid_pin,
       fabric_key, group_config_block);
   } else {
-    /* TODO: Build the tile instances under the top module */
+    /* Build the tile instances under the top module */
     status = build_top_module_tile_child_instances(
       module_manager, top_module, blwl_sr_banks, circuit_lib, clk_ntwk,
       rr_clock_lookup, vpr_device_annotation, grids, layer, tile_annotation,
       rr_graph, device_rr_gsb, tile_direct, arch_direct, fabric_tile,
-      config_protocol, sram_model, fabric_key, group_config_block, frame_view,
-      verbose);
+      config_protocol, sram_model, fabric_key, group_config_block,
+      name_module_using_index, frame_view, verbose);
   }
 
   if (status != CMD_EXEC_SUCCESS) {

openfpga/src/fabric/build_top_module.h

@@ -42,10 +42,10 @@ int build_top_module(
   const DeviceRRGSB& device_rr_gsb, const TileDirect& tile_direct,
   const ArchDirect& arch_direct, const ConfigProtocol& config_protocol,
   const CircuitModelId& sram_model, const FabricTile& fabric_tile,
-  const bool& frame_view, const bool& compact_routing_hierarchy,
-  const bool& duplicate_grid_pin, const FabricKey& fabric_key,
-  const bool& generate_random_fabric_key, const bool& group_config_block,
-  const bool& verbose);
+  const bool& name_module_using_index, const bool& frame_view,
+  const bool& compact_routing_hierarchy, const bool& duplicate_grid_pin,
+  const FabricKey& fabric_key, const bool& generate_random_fabric_key,
+  const bool& group_config_block, const bool& verbose);
 
 } /* end namespace openfpga */
 

openfpga/src/fabric/build_top_module_child_tile_instance.cpp

@@ -290,7 +290,8 @@ static int build_top_module_tile_nets_between_sb_and_pb(
   const RRGSB& rr_gsb, const FabricTile& fabric_tile,
   const FabricTileId& curr_fabric_tile_id,
   const size_t& sb_idx_in_curr_fabric_tile,
-  const bool& compact_routing_hierarchy, const bool& verbose) {
+  const bool& compact_routing_hierarchy, const bool& name_module_using_index,
+  const bool& verbose) {
   /* Skip those Switch blocks that do not exist */
   if (false == rr_gsb.is_sb_exist(rr_graph)) {
     return CMD_EXEC_SUCCESS;
@@ -303,6 +304,11 @@ static int build_top_module_tile_nets_between_sb_and_pb(
     fabric_tile.sb_coordinates(sink_unique_tile)[sb_idx_in_curr_fabric_tile];
   std::string sink_sb_instance_name_in_unique_tile =
     generate_switch_block_module_name(sink_sb_coord_in_unique_tile);
+  if (name_module_using_index) {
+    sink_sb_instance_name_in_unique_tile =
+      generate_switch_block_module_name_using_index(
+        device_rr_gsb.get_sb_unique_module_index(sink_sb_coord_in_unique_tile));
+  }
 
   /* We could have two different coordinators, one is the instance, the other is
    * the module */
@@ -526,7 +532,8 @@ static int build_top_module_tile_nets_between_cb_and_pb(
   const RRGSB& rr_gsb, const FabricTile& fabric_tile,
   const FabricTileId& curr_fabric_tile_id, const t_rr_type& cb_type,
   const size_t& cb_idx_in_curr_fabric_tile,
-  const bool& compact_routing_hierarchy, const bool& verbose) {
+  const bool& compact_routing_hierarchy, const bool& name_module_using_index,
+  const bool& verbose) {
   vtr::Point<size_t> src_tile_coord =
     fabric_tile.tile_coordinate(curr_fabric_tile_id);
   FabricTileId src_unique_tile = fabric_tile.unique_tile(src_tile_coord);
@@ -537,6 +544,12 @@ static int build_top_module_tile_nets_between_cb_and_pb(
   std::string src_cb_instance_name_in_unique_tile =
     generate_connection_block_module_name(
       cb_type, src_cb_inst_rr_gsb.get_cb_coordinate(cb_type));
+  if (name_module_using_index) {
+    src_cb_instance_name_in_unique_tile =
+      generate_connection_block_module_name_using_index(
+        cb_type, device_rr_gsb.get_cb_unique_module_index(
+                   cb_type, src_cb_inst_rr_gsb.get_cb_coordinate(cb_type)));
+  }
 
   /* We could have two different coordinators, one is the instance, the other is
    * the module */
@@ -720,7 +733,8 @@ static int build_top_module_tile_nets_between_sb_and_cb(
   const RRGraphView& rr_graph, const RRGSB& rr_gsb,
   const FabricTile& fabric_tile, const FabricTileId& curr_fabric_tile_id,
   const size_t& sb_idx_in_curr_fabric_tile,
-  const bool& compact_routing_hierarchy, const bool& verbose) {
+  const bool& compact_routing_hierarchy, const bool& name_module_using_index,
+  const bool& verbose) {
   /* We could have two different coordinators, one is the instance, the other is
    * the module */
   vtr::Point<size_t> instance_sb_coordinate(rr_gsb.get_sb_x(),
@@ -734,6 +748,11 @@ static int build_top_module_tile_nets_between_sb_and_cb(
     fabric_tile.sb_coordinates(sb_unique_tile)[sb_idx_in_curr_fabric_tile];
   std::string sb_instance_name_in_unique_tile =
     generate_switch_block_module_name(sb_coord_in_unique_tile);
+  if (name_module_using_index) {
+    sb_instance_name_in_unique_tile =
+      generate_switch_block_module_name_using_index(
+        device_rr_gsb.get_sb_unique_module_index(sb_coord_in_unique_tile));
+  }
 
   /* Skip those Switch blocks that do not exist */
   if (false == rr_gsb.is_sb_exist(rr_graph)) {
@@ -835,6 +854,12 @@ static int build_top_module_tile_nets_between_sb_and_cb(
     std::string cb_instance_name_in_unique_tile =
       generate_connection_block_module_name(
         cb_type, unique_cb_rr_gsb.get_cb_coordinate(cb_type));
+    if (name_module_using_index) {
+      cb_instance_name_in_unique_tile =
+        generate_connection_block_module_name_using_index(
+          cb_type, device_rr_gsb.get_cb_unique_module_index(
+                     cb_type, unique_cb_rr_gsb.get_cb_coordinate(cb_type)));
+    }
     std::string cb_tile_module_name =
       generate_tile_module_name(cb_unique_tile_coord);
     ModuleId cb_tile_module = module_manager.find_module(cb_tile_module_name);
@@ -955,7 +980,7 @@ static int add_top_module_nets_around_one_tile(
   const vtr::Matrix<size_t>& tile_instance_ids,
   const RRGraphView& rr_graph_view, const DeviceRRGSB& device_rr_gsb,
   const FabricTile& fabric_tile, const FabricTileId& curr_fabric_tile_id,
-  const bool& verbose) {
+  const bool& name_module_using_index, const bool& verbose) {
   int status = CMD_EXEC_SUCCESS;
 
   /* Find the module name for this type of tile */
@@ -983,7 +1008,7 @@ static int add_top_module_nets_around_one_tile(
       module_manager, top_module, tile_module, tile_instance_ids,
       tile_instance_id, grids, vpr_device_annotation, device_rr_gsb,
       rr_graph_view, rr_gsb, fabric_tile, curr_fabric_tile_id, isb, true,
-      verbose);
+      name_module_using_index, verbose);
     if (status != CMD_EXEC_SUCCESS) {
       return CMD_EXEC_FATAL_ERROR;
     }
@@ -1001,7 +1026,7 @@ static int add_top_module_nets_around_one_tile(
         module_manager, top_module, tile_module, tile_instance_ids,
         tile_instance_id, grids, vpr_device_annotation, device_rr_gsb,
         rr_graph_view, rr_gsb, fabric_tile, curr_fabric_tile_id, cb_type, icb,
-        true, verbose);
+        true, name_module_using_index, verbose);
       if (status != CMD_EXEC_SUCCESS) {
         return CMD_EXEC_FATAL_ERROR;
       }
@@ -1017,7 +1042,7 @@ static int add_top_module_nets_around_one_tile(
     status = build_top_module_tile_nets_between_sb_and_cb(
       module_manager, top_module, tile_module, tile_instance_ids,
       tile_instance_id, device_rr_gsb, rr_graph_view, rr_gsb, fabric_tile,
-      curr_fabric_tile_id, isb, true, verbose);
+      curr_fabric_tile_id, isb, true, name_module_using_index, verbose);
     if (status != CMD_EXEC_SUCCESS) {
       return CMD_EXEC_FATAL_ERROR;
     }
@@ -1035,7 +1060,7 @@ static int add_top_module_nets_connect_tiles(
   const VprDeviceAnnotation& vpr_device_annotation, const DeviceGrid& grids,
   const vtr::Matrix<size_t>& tile_instance_ids, const RRGraphView& rr_graph,
   const DeviceRRGSB& device_rr_gsb, const FabricTile& fabric_tile,
-  const bool& verbose) {
+  const bool& name_module_using_index, const bool& verbose) {
   vtr::ScopedStartFinishTimer timer("Add module nets between tiles");
   int status = CMD_EXEC_SUCCESS;
 
@@ -1049,7 +1074,7 @@ static int add_top_module_nets_connect_tiles(
       status = add_top_module_nets_around_one_tile(
         module_manager, top_module, vpr_device_annotation, grids,
         tile_instance_ids, rr_graph, device_rr_gsb, fabric_tile,
-        curr_fabric_tile_id, verbose);
+        curr_fabric_tile_id, name_module_using_index, verbose);
       if (status != CMD_EXEC_SUCCESS) {
         return CMD_EXEC_FATAL_ERROR;
       }
@@ -1874,7 +1899,8 @@ int build_top_module_tile_child_instances(
   const TileDirect& tile_direct, const ArchDirect& arch_direct,
   const FabricTile& fabric_tile, const ConfigProtocol& config_protocol,
   const CircuitModelId& sram_model, const FabricKey& fabric_key,
-  const bool& group_config_block, const bool& frame_view, const bool& verbose) {
+  const bool& group_config_block, const bool& name_module_using_index,
+  const bool& frame_view, const bool& verbose) {
   int status = CMD_EXEC_SUCCESS;
   vtr::Matrix<size_t> tile_instance_ids;
   status = add_top_module_tile_instances(module_manager, top_module,
@@ -1894,7 +1920,8 @@ int build_top_module_tile_child_instances(
     /* Regular nets between tiles */
     status = add_top_module_nets_connect_tiles(
       module_manager, top_module, vpr_device_annotation, grids,
-      tile_instance_ids, rr_graph, device_rr_gsb, fabric_tile, verbose);
+      tile_instance_ids, rr_graph, device_rr_gsb, fabric_tile,
+      name_module_using_index, verbose);
     if (status != CMD_EXEC_SUCCESS) {
       return CMD_EXEC_FATAL_ERROR;
     }

openfpga/src/fabric/build_top_module_child_tile_instance.h

@@ -43,7 +43,8 @@ int build_top_module_tile_child_instances(
   const TileDirect& tile_direct, const ArchDirect& arch_direct,
   const FabricTile& fabric_tile, const ConfigProtocol& config_protocol,
   const CircuitModelId& sram_model, const FabricKey& fabric_key,
-  const bool& group_config_block, const bool& frame_view, const bool& verbose);
+  const bool& group_config_block, const bool& name_module_using_index,
+  const bool& frame_view, const bool& verbose);
 
 } /* end namespace openfpga */
 

openfpga/src/fabric/fabric_hierarchy_writer.cpp

@@ -84,6 +84,7 @@ static int rec_output_module_hierarchy_to_text_file(
  * Return 2 if fail when creating files
  ***************************************************************************************/
 int write_fabric_hierarchy_to_text_file(const ModuleManager& module_manager,
+                                        const ModuleNameMap& module_name_map,
                                         const std::string& fname,
                                         const size_t& hie_depth_to_stop,
                                         const bool& verbose) {
@@ -111,7 +112,8 @@ int write_fabric_hierarchy_to_text_file(const ModuleManager& module_manager,
   check_file_stream(fname.c_str(), fp);
 
   /* Find top-level module */
-  std::string top_module_name = generate_fpga_top_module_name();
+  std::string top_module_name =
+    module_name_map.name(generate_fpga_top_module_name());
   ModuleId top_module = module_manager.find_module(top_module_name);
   if (true != module_manager.valid_module_id(top_module)) {
     VTR_LOGV_ERROR(verbose, "Unable to find the top-level module '%s'!\n",

openfpga/src/fabric/fabric_hierarchy_writer.h

@@ -15,6 +15,7 @@
 namespace openfpga {
 
 int write_fabric_hierarchy_to_text_file(const ModuleManager& module_manager,
+                                        const ModuleNameMap& module_name_map,
                                         const std::string& fname,
                                         const size_t& hie_depth_to_stop,
                                         const bool& verbose);

openfpga/src/fabric/rename_modules.cpp

@@ -0,0 +1,115 @@
+/* Headers from vtrutil library */
+#include "rename_modules.h"
+
+#include "command_exit_codes.h"
+#include "openfpga_naming.h"
+#include "vtr_assert.h"
+#include "vtr_log.h"
+#include "vtr_time.h"
+
+/* begin namespace openfpga */
+namespace openfpga {
+
+/** @brief Initialize a module name map with the existing module names from a
+ * module manager. In this case, all the built-in names are the same as
+ * customized names */
+int init_fabric_module_name_map(ModuleNameMap& module_name_map,
+                                const ModuleManager& module_manager,
+                                const bool& verbose) {
+  int status = CMD_EXEC_SUCCESS;
+  /* the module name map should be empty! */
+  module_name_map.clear();
+  size_t cnt = 0;
+  for (ModuleId curr_module : module_manager.modules()) {
+    status = module_name_map.set_tag_to_name_pair(
+      module_manager.module_name(curr_module),
+      module_manager.module_name(curr_module));
+    if (status != CMD_EXEC_SUCCESS) {
+      return CMD_EXEC_SUCCESS;
+    }
+    cnt++;
+  }
+  VTR_LOGV(verbose, "Initialized module name map for '%lu' modules\n", cnt);
+  return CMD_EXEC_SUCCESS;
+}
+
+int update_module_map_name_with_indexing_names(ModuleNameMap& module_name_map,
+                                               const DeviceRRGSB& device_rr_gsb,
+                                               const FabricTile& fabric_tile,
+                                               const bool& verbose) {
+  int status = CMD_EXEC_SUCCESS;
+  /* Walk through the device rr gsb on the unique routing modules */
+  for (size_t isb = 0; isb < device_rr_gsb.get_num_sb_unique_module(); ++isb) {
+    const RRGSB& unique_mirror = device_rr_gsb.get_sb_unique_module(isb);
+    vtr::Point<size_t> gsb_coordinate(unique_mirror.get_sb_x(),
+                                      unique_mirror.get_sb_y());
+    std::string name_using_coord =
+      generate_switch_block_module_name(gsb_coordinate);
+    std::string name_using_index =
+      generate_switch_block_module_name_using_index(isb);
+    status =
+      module_name_map.set_tag_to_name_pair(name_using_coord, name_using_index);
+    if (status != CMD_EXEC_SUCCESS) {
+      return CMD_EXEC_SUCCESS;
+    }
+    VTR_LOGV(verbose, "Now use indexing name for module '%s' (was '%s')\n",
+             name_using_index.c_str(), name_using_coord.c_str());
+  }
+  for (t_rr_type cb_type : {CHANX, CHANY}) {
+    for (size_t icb = 0; icb < device_rr_gsb.get_num_cb_unique_module(cb_type);
+         ++icb) {
+      const RRGSB& unique_mirror =
+        device_rr_gsb.get_cb_unique_module(cb_type, icb);
+      vtr::Point<size_t> gsb_coordinate(unique_mirror.get_cb_x(cb_type),
+                                        unique_mirror.get_cb_y(cb_type));
+      std::string name_using_coord =
+        generate_connection_block_module_name(cb_type, gsb_coordinate);
+      std::string name_using_index =
+        generate_connection_block_module_name_using_index(cb_type, icb);
+      status = module_name_map.set_tag_to_name_pair(name_using_coord,
+                                                    name_using_index);
+      if (status != CMD_EXEC_SUCCESS) {
+        return CMD_EXEC_SUCCESS;
+      }
+      VTR_LOGV(verbose, "Now use indexing name for module '%s' (was '%s')\n",
+               name_using_index.c_str(), name_using_coord.c_str());
+    }
+  }
+  /* Walk through the fabric tile on the unique routing modules */
+  for (size_t itile = 0; itile < fabric_tile.unique_tiles().size(); ++itile) {
+    FabricTileId fabric_tile_id = fabric_tile.unique_tiles()[itile];
+    vtr::Point<size_t> tile_coord = fabric_tile.tile_coordinate(fabric_tile_id);
+    std::string name_using_coord = generate_tile_module_name(tile_coord);
+    std::string name_using_index = generate_tile_module_name_using_index(itile);
+    status =
+      module_name_map.set_tag_to_name_pair(name_using_coord, name_using_index);
+    if (status != CMD_EXEC_SUCCESS) {
+      return CMD_EXEC_SUCCESS;
+    }
+    VTR_LOGV(verbose, "Now use indexing name for module '%s' (was '%s')\n",
+             name_using_index.c_str(), name_using_coord.c_str());
+  }
+  return CMD_EXEC_SUCCESS;
+}
+
+int rename_fabric_modules(ModuleManager& module_manager,
+                          const ModuleNameMap& module_name_map,
+                          const bool& verbose) {
+  int status = CMD_EXEC_SUCCESS;
+  size_t cnt = 0;
+  for (ModuleId curr_module : module_manager.modules()) {
+    std::string new_name =
+      module_name_map.name(module_manager.module_name(curr_module));
+    if (new_name != module_manager.module_name(curr_module)) {
+      VTR_LOGV(verbose, "Rename module '%s' to its new name '%s'\n",
+               module_manager.module_name(curr_module).c_str(),
+               new_name.c_str());
+      module_manager.set_module_name(curr_module, new_name);
+    }
+    cnt++;
+  }
+  VTR_LOG("Renamed %lu modules\n", cnt);
+  return status;
+}
+
+} /* end namespace openfpga */

openfpga/src/fabric/rename_modules.h

@@ -0,0 +1,34 @@
+#ifndef RENAME_MODULES_H
+#define RENAME_MODULES_H
+
+/********************************************************************
+ * Include header files that are required by function declaration
+ *******************************************************************/
+#include "device_rr_gsb.h"
+#include "fabric_tile.h"
+#include "module_manager.h"
+#include "module_name_map.h"
+
+/********************************************************************
+ * Function declaration
+ *******************************************************************/
+
+/* begin namespace openfpga */
+namespace openfpga {
+
+int init_fabric_module_name_map(ModuleNameMap& module_name_map,
+                                const ModuleManager& module_manager,
+                                const bool& verbose);
+
+int update_module_map_name_with_indexing_names(ModuleNameMap& module_name_map,
+                                               const DeviceRRGSB& device_rr_gsb,
+                                               const FabricTile& fabric_tile,
+                                               const bool& verbose);
+
+int rename_fabric_modules(ModuleManager& module_manager,
+                          const ModuleNameMap& module_name_map,
+                          const bool& verbose);
+
+} /* end namespace openfpga */
+
+#endif

openfpga/src/fpga_bitstream/build_device_bitstream.cpp

@@ -161,7 +161,8 @@ BitstreamManager build_device_bitstream(const VprContext& vpr_ctx,
   /* Create the top-level block for bitstream
    * This is related to the top-level module of fpga
    */
-  std::string top_block_name = generate_fpga_top_module_name();
+  std::string top_block_name =
+    openfpga_ctx.module_name_map().name(generate_fpga_top_module_name());
   ConfigBlockId top_block = bitstream_manager.add_block(top_block_name);
   ModuleId top_module = openfpga_ctx.module_graph().find_module(top_block_name);
   VTR_ASSERT(true == openfpga_ctx.module_graph().valid_module_id(top_module));
@@ -169,6 +170,9 @@ BitstreamManager build_device_bitstream(const VprContext& vpr_ctx,
   /* Create the core block when the fpga_core is added */
   size_t num_blocks_to_reserve = 0;
   std::string core_block_name = generate_fpga_core_module_name();
+  if (openfpga_ctx.module_name_map().name_exist(core_block_name)) {
+    core_block_name = openfpga_ctx.module_name_map().name(core_block_name);
+  }
   const ModuleId& core_module =
     openfpga_ctx.module_graph().find_module(core_block_name);
   if (openfpga_ctx.module_graph().valid_module_id(core_module)) {
@@ -206,22 +210,23 @@ BitstreamManager build_device_bitstream(const VprContext& vpr_ctx,
 
   /* Create bitstream from grids */
   VTR_LOGV(verbose, "Building grid bitstream...\n");
-  build_grid_bitstream(bitstream_manager, top_block,
-                       openfpga_ctx.module_graph(), openfpga_ctx.fabric_tile(),
-                       openfpga_ctx.arch().circuit_lib, openfpga_ctx.mux_lib(),
-                       vpr_ctx.device().grid, 0, vpr_ctx.atom(),
-                       openfpga_ctx.vpr_device_annotation(),
-                       openfpga_ctx.vpr_clustering_annotation(),
-                       openfpga_ctx.vpr_placement_annotation(),
-                       openfpga_ctx.vpr_bitstream_annotation(), verbose);
+  build_grid_bitstream(
+    bitstream_manager, top_block, openfpga_ctx.module_graph(),
+    openfpga_ctx.module_name_map(), openfpga_ctx.fabric_tile(),
+    openfpga_ctx.arch().circuit_lib, openfpga_ctx.mux_lib(),
+    vpr_ctx.device().grid, 0, vpr_ctx.atom(),
+    openfpga_ctx.vpr_device_annotation(),
+    openfpga_ctx.vpr_clustering_annotation(),
+    openfpga_ctx.vpr_placement_annotation(),
+    openfpga_ctx.vpr_bitstream_annotation(), verbose);
   VTR_LOGV(verbose, "Done\n");
 
   /* Create bitstream from routing architectures */
   VTR_LOGV(verbose, "Building routing bitstream...\n");
   build_routing_bitstream(
     bitstream_manager, top_block, openfpga_ctx.module_graph(),
-    openfpga_ctx.fabric_tile(), openfpga_ctx.arch().circuit_lib,
-    openfpga_ctx.mux_lib(), vpr_ctx.atom(),
+    openfpga_ctx.module_name_map(), openfpga_ctx.fabric_tile(),
+    openfpga_ctx.arch().circuit_lib, openfpga_ctx.mux_lib(), vpr_ctx.atom(),
     openfpga_ctx.vpr_device_annotation(), openfpga_ctx.vpr_routing_annotation(),
     vpr_ctx.device().rr_graph, openfpga_ctx.device_rr_gsb(),
     openfpga_ctx.flow_manager().compress_routing(), verbose);

openfpga/src/fpga_bitstream/build_fabric_bitstream.cpp

@@ -772,14 +772,16 @@ static void build_module_fabric_dependent_bitstream(
  *******************************************************************/
 FabricBitstream build_fabric_dependent_bitstream(
   const BitstreamManager& bitstream_manager,
-  const ModuleManager& module_manager, const CircuitLibrary& circuit_lib,
-  const ConfigProtocol& config_protocol, const bool& verbose) {
+  const ModuleManager& module_manager, const ModuleNameMap& module_name_map,
+  const CircuitLibrary& circuit_lib, const ConfigProtocol& config_protocol,
+  const bool& verbose) {
   FabricBitstream fabric_bitstream;
 
   vtr::ScopedStartFinishTimer timer("\nBuild fabric dependent bitstream\n");
 
   /* Get the top module name in module manager, which is our starting point */
-  std::string top_module_name = generate_fpga_top_module_name();
+  std::string top_module_name =
+    module_name_map.name(generate_fpga_top_module_name());
   ModuleId top_module = module_manager.find_module(top_module_name);
   VTR_ASSERT(true == module_manager.valid_module_id(top_module));
 
@@ -794,6 +796,9 @@ FabricBitstream build_fabric_dependent_bitstream(
 
   /* Create the core block when the fpga_core is added */
   std::string core_block_name = generate_fpga_core_module_name();
+  if (module_name_map.name_exist(core_block_name)) {
+    core_block_name = module_name_map.name(core_block_name);
+  }
   const ModuleId& core_module = module_manager.find_module(core_block_name);
   if (module_manager.valid_module_id(core_module)) {
     /* Now we use the core_block as the top-level block for the remaining

openfpga/src/fpga_bitstream/build_fabric_bitstream.h

@@ -11,6 +11,7 @@
 #include "config_protocol.h"
 #include "fabric_bitstream.h"
 #include "module_manager.h"
+#include "module_name_map.h"
 
 /********************************************************************
  * Function declaration
@@ -21,8 +22,9 @@ namespace openfpga {
 
 FabricBitstream build_fabric_dependent_bitstream(
   const BitstreamManager& bitstream_manager,
-  const ModuleManager& module_manager, const CircuitLibrary& circuit_lib,
-  const ConfigProtocol& config_protocol, const bool& verbose);
+  const ModuleManager& module_manager, const ModuleNameMap& module_name_map,
+  const CircuitLibrary& circuit_lib, const ConfigProtocol& config_protocol,
+  const bool& verbose);
 
 } /* end namespace openfpga */
 

openfpga/src/fpga_bitstream/build_grid_bitstream.cpp

@@ -180,9 +180,9 @@ static void build_physical_block_pin_interc_bitstream(
   BitstreamManager& bitstream_manager,
   std::map<std::string, size_t>& grouped_mem_inst_scoreboard,
   const ConfigBlockId& parent_configurable_block,
-  const ModuleManager& module_manager, const CircuitLibrary& circuit_lib,
-  const MuxLibrary& mux_lib, const AtomContext& atom_ctx,
-  const VprDeviceAnnotation& device_annotation,
+  const ModuleManager& module_manager, const ModuleNameMap& module_name_map,
+  const CircuitLibrary& circuit_lib, const MuxLibrary& mux_lib,
+  const AtomContext& atom_ctx, const VprDeviceAnnotation& device_annotation,
   const VprBitstreamAnnotation& bitstream_annotation,
   const PhysicalPb& physical_pb, t_pb_graph_pin* des_pb_graph_pin,
   t_mode* physical_mode, const bool& verbose) {
@@ -290,6 +290,7 @@ static void build_physical_block_pin_interc_bitstream(
       std::string mem_module_name =
         generate_mux_subckt_name(circuit_lib, mux_model, datapath_mux_size,
                                  std::string(MEMORY_MODULE_POSTFIX));
+      mem_module_name = module_name_map.name(mem_module_name);
       ModuleId mux_mem_module = module_manager.find_module(mem_module_name);
       VTR_ASSERT(true == module_manager.valid_module_id(mux_mem_module));
       ModulePortId mux_mem_out_port_id = module_manager.find_module_port(
@@ -302,6 +303,9 @@ static void build_physical_block_pin_interc_bitstream(
       std::string feedthru_mem_block_name = generate_mux_subckt_name(
         circuit_lib, mux_model, datapath_mux_size,
         std::string(MEMORY_FEEDTHROUGH_MODULE_POSTFIX));
+      if (module_name_map.name_exist(feedthru_mem_block_name)) {
+        feedthru_mem_block_name = module_name_map.name(feedthru_mem_block_name);
+      }
       ModuleId feedthru_mem_module =
         module_manager.find_module(feedthru_mem_block_name);
       if (module_manager.valid_module_id(feedthru_mem_module)) {
@@ -375,9 +379,9 @@ static void build_physical_block_interc_port_bitstream(
   BitstreamManager& bitstream_manager,
   std::map<std::string, size_t>& grouped_mem_inst_scoreboard,
   const ConfigBlockId& parent_configurable_block,
-  const ModuleManager& module_manager, const CircuitLibrary& circuit_lib,
-  const MuxLibrary& mux_lib, const AtomContext& atom_ctx,
-  const VprDeviceAnnotation& device_annotation,
+  const ModuleManager& module_manager, const ModuleNameMap& module_name_map,
+  const CircuitLibrary& circuit_lib, const MuxLibrary& mux_lib,
+  const AtomContext& atom_ctx, const VprDeviceAnnotation& device_annotation,
   const VprBitstreamAnnotation& bitstream_annotation,
   t_pb_graph_node* physical_pb_graph_node, const PhysicalPb& physical_pb,
   const e_circuit_pb_port_type& pb_port_type, t_mode* physical_mode,
@@ -390,8 +394,9 @@ static void build_physical_block_interc_port_bitstream(
              ++ipin) {
           build_physical_block_pin_interc_bitstream(
             bitstream_manager, grouped_mem_inst_scoreboard,
-            parent_configurable_block, module_manager, circuit_lib, mux_lib,
-            atom_ctx, device_annotation, bitstream_annotation, physical_pb,
+            parent_configurable_block, module_manager, module_name_map,
+            circuit_lib, mux_lib, atom_ctx, device_annotation,
+            bitstream_annotation, physical_pb,
             &(physical_pb_graph_node->input_pins[iport][ipin]), physical_mode,
             verbose);
         }
@@ -404,8 +409,9 @@ static void build_physical_block_interc_port_bitstream(
              ipin < physical_pb_graph_node->num_output_pins[iport]; ++ipin) {
           build_physical_block_pin_interc_bitstream(
             bitstream_manager, grouped_mem_inst_scoreboard,
-            parent_configurable_block, module_manager, circuit_lib, mux_lib,
-            atom_ctx, device_annotation, bitstream_annotation, physical_pb,
+            parent_configurable_block, module_manager, module_name_map,
+            circuit_lib, mux_lib, atom_ctx, device_annotation,
+            bitstream_annotation, physical_pb,
             &(physical_pb_graph_node->output_pins[iport][ipin]), physical_mode,
             verbose);
         }
@@ -418,8 +424,9 @@ static void build_physical_block_interc_port_bitstream(
              ++ipin) {
           build_physical_block_pin_interc_bitstream(
             bitstream_manager, grouped_mem_inst_scoreboard,
-            parent_configurable_block, module_manager, circuit_lib, mux_lib,
-            atom_ctx, device_annotation, bitstream_annotation, physical_pb,
+            parent_configurable_block, module_manager, module_name_map,
+            circuit_lib, mux_lib, atom_ctx, device_annotation,
+            bitstream_annotation, physical_pb,
             &(physical_pb_graph_node->clock_pins[iport][ipin]), physical_mode,
             verbose);
         }
@@ -439,9 +446,9 @@ static void build_physical_block_interc_bitstream(
   BitstreamManager& bitstream_manager,
   std::map<std::string, size_t>& grouped_mem_inst_scoreboard,
   const ConfigBlockId& parent_configurable_block,
-  const ModuleManager& module_manager, const CircuitLibrary& circuit_lib,
-  const MuxLibrary& mux_lib, const AtomContext& atom_ctx,
-  const VprDeviceAnnotation& device_annotation,
+  const ModuleManager& module_manager, const ModuleNameMap& module_name_map,
+  const CircuitLibrary& circuit_lib, const MuxLibrary& mux_lib,
+  const AtomContext& atom_ctx, const VprDeviceAnnotation& device_annotation,
   const VprBitstreamAnnotation& bitstream_annotation,
   t_pb_graph_node* physical_pb_graph_node, const PhysicalPb& physical_pb,
   t_mode* physical_mode, const bool& verbose) {
@@ -463,9 +470,9 @@ static void build_physical_block_interc_bitstream(
    */
   build_physical_block_interc_port_bitstream(
     bitstream_manager, grouped_mem_inst_scoreboard, parent_configurable_block,
-    module_manager, circuit_lib, mux_lib, atom_ctx, device_annotation,
-    bitstream_annotation, physical_pb_graph_node, physical_pb,
-    CIRCUIT_PB_PORT_OUTPUT, physical_mode, verbose);
+    module_manager, module_name_map, circuit_lib, mux_lib, atom_ctx,
+    device_annotation, bitstream_annotation, physical_pb_graph_node,
+    physical_pb, CIRCUIT_PB_PORT_OUTPUT, physical_mode, verbose);
 
   /* We check input_pins of child_pb_graph_node and its the input_edges
    * Iterate over the interconnections between inputs of physical_pb_graph_node
@@ -486,15 +493,17 @@ static void build_physical_block_interc_bitstream(
       /* For each child_pb_graph_node input pins*/
       build_physical_block_interc_port_bitstream(
         bitstream_manager, grouped_mem_inst_scoreboard,
-        parent_configurable_block, module_manager, circuit_lib, mux_lib,
-        atom_ctx, device_annotation, bitstream_annotation, child_pb_graph_node,
-        physical_pb, CIRCUIT_PB_PORT_INPUT, physical_mode, verbose);
+        parent_configurable_block, module_manager, module_name_map, circuit_lib,
+        mux_lib, atom_ctx, device_annotation, bitstream_annotation,
+        child_pb_graph_node, physical_pb, CIRCUIT_PB_PORT_INPUT, physical_mode,
+        verbose);
       /* For clock pins, we should do the same work */
       build_physical_block_interc_port_bitstream(
         bitstream_manager, grouped_mem_inst_scoreboard,
-        parent_configurable_block, module_manager, circuit_lib, mux_lib,
-        atom_ctx, device_annotation, bitstream_annotation, child_pb_graph_node,
-        physical_pb, CIRCUIT_PB_PORT_CLOCK, physical_mode, verbose);
+        parent_configurable_block, module_manager, module_name_map, circuit_lib,
+        mux_lib, atom_ctx, device_annotation, bitstream_annotation,
+        child_pb_graph_node, physical_pb, CIRCUIT_PB_PORT_CLOCK, physical_mode,
+        verbose);
     }
   }
 }
@@ -697,9 +706,9 @@ static void rec_build_physical_block_bitstream(
   BitstreamManager& bitstream_manager,
   std::map<std::string, size_t>& grouped_mem_inst_scoreboard,
   const ConfigBlockId& parent_configurable_block,
-  const ModuleManager& module_manager, const CircuitLibrary& circuit_lib,
-  const MuxLibrary& mux_lib, const AtomContext& atom_ctx,
-  const VprDeviceAnnotation& device_annotation,
+  const ModuleManager& module_manager, const ModuleNameMap& module_name_map,
+  const CircuitLibrary& circuit_lib, const MuxLibrary& mux_lib,
+  const AtomContext& atom_ctx, const VprDeviceAnnotation& device_annotation,
   const VprBitstreamAnnotation& bitstream_annotation, const e_side& border_side,
   const PhysicalPb& physical_pb, const PhysicalPbId& pb_id,
   t_pb_graph_node* physical_pb_graph_node, const size_t& pb_graph_node_index,
@@ -713,6 +722,7 @@ static void rec_build_physical_block_bitstream(
   /* Early exit if this parent module has no configurable child modules */
   std::string pb_module_name =
     generate_physical_block_module_name(physical_pb_type);
+  pb_module_name = module_name_map.name(pb_module_name);
   ModuleId pb_module = module_manager.find_module(pb_module_name);
   VTR_ASSERT(true == module_manager.valid_module_id(pb_module));
 
@@ -758,8 +768,9 @@ static void rec_build_physical_block_bitstream(
         /* Go recursively */
         rec_build_physical_block_bitstream(
           bitstream_manager, grouped_mem_inst_scoreboard, pb_configurable_block,
-          module_manager, circuit_lib, mux_lib, atom_ctx, device_annotation,
-          bitstream_annotation, border_side, physical_pb, child_pb,
+          module_manager, module_name_map, circuit_lib, mux_lib, atom_ctx,
+          device_annotation, bitstream_annotation, border_side, physical_pb,
+          child_pb,
           &(physical_pb_graph_node
               ->child_pb_graph_nodes[physical_mode->index][ipb][jpb]),
           jpb, verbose);
@@ -804,9 +815,9 @@ static void rec_build_physical_block_bitstream(
   /* Generate the bitstream for the interconnection in this physical block */
   build_physical_block_interc_bitstream(
     bitstream_manager, grouped_mem_inst_scoreboard, pb_configurable_block,
-    module_manager, circuit_lib, mux_lib, atom_ctx, device_annotation,
-    bitstream_annotation, physical_pb_graph_node, physical_pb, physical_mode,
-    verbose);
+    module_manager, module_name_map, circuit_lib, mux_lib, atom_ctx,
+    device_annotation, bitstream_annotation, physical_pb_graph_node,
+    physical_pb, physical_mode, verbose);
 }
 
 /********************************************************************
@@ -817,10 +828,10 @@ static void rec_build_physical_block_bitstream(
  *******************************************************************/
 static void build_physical_block_bitstream(
   BitstreamManager& bitstream_manager, const ConfigBlockId& top_block,
-  const ModuleManager& module_manager, const FabricTile& fabric_tile,
-  const FabricTileId& curr_tile, const CircuitLibrary& circuit_lib,
-  const MuxLibrary& mux_lib, const AtomContext& atom_ctx,
-  const VprDeviceAnnotation& device_annotation,
+  const ModuleManager& module_manager, const ModuleNameMap& module_name_map,
+  const FabricTile& fabric_tile, const FabricTileId& curr_tile,
+  const CircuitLibrary& circuit_lib, const MuxLibrary& mux_lib,
+  const AtomContext& atom_ctx, const VprDeviceAnnotation& device_annotation,
   const VprClusteringAnnotation& cluster_annotation,
   const VprPlacementAnnotation& place_annotation,
   const VprBitstreamAnnotation& bitstream_annotation, const DeviceGrid& grids,
@@ -835,6 +846,7 @@ static void build_physical_block_bitstream(
   std::string grid_module_name = generate_grid_block_module_name(
     grid_module_name_prefix, std::string(grid_type->name),
     is_io_type(grid_type), border_side);
+  grid_module_name = module_name_map.name(grid_module_name);
   ModuleId grid_module = module_manager.find_module(grid_module_name);
   VTR_ASSERT(true == module_manager.valid_module_id(grid_module));
 
@@ -916,10 +928,10 @@ static void build_physical_block_bitstream(
         /* Recursively traverse the pb_graph and generate bitstream */
         rec_build_physical_block_bitstream(
           bitstream_manager, grouped_mem_inst_scoreboard,
-          grid_configurable_block, module_manager, circuit_lib, mux_lib,
-          atom_ctx, device_annotation, bitstream_annotation, border_side,
-          PhysicalPb(), PhysicalPbId::INVALID(), lb_type->pb_graph_head, z,
-          verbose);
+          grid_configurable_block, module_manager, module_name_map, circuit_lib,
+          mux_lib, atom_ctx, device_annotation, bitstream_annotation,
+          border_side, PhysicalPb(), PhysicalPbId::INVALID(),
+          lb_type->pb_graph_head, z, verbose);
       } else {
         const PhysicalPb& phy_pb = cluster_annotation.physical_pb(
           place_annotation.grid_blocks(grid_coord)[z]);
@@ -932,9 +944,9 @@ static void build_physical_block_bitstream(
         /* Recursively traverse the pb_graph and generate bitstream */
         rec_build_physical_block_bitstream(
           bitstream_manager, grouped_mem_inst_scoreboard,
-          grid_configurable_block, module_manager, circuit_lib, mux_lib,
-          atom_ctx, device_annotation, bitstream_annotation, border_side,
-          phy_pb, top_pb_id, pb_graph_head, z, verbose);
+          grid_configurable_block, module_manager, module_name_map, circuit_lib,
+          mux_lib, atom_ctx, device_annotation, bitstream_annotation,
+          border_side, phy_pb, top_pb_id, pb_graph_head, z, verbose);
       }
     }
   }
@@ -948,10 +960,10 @@ static void build_physical_block_bitstream(
  *******************************************************************/
 void build_grid_bitstream(
   BitstreamManager& bitstream_manager, const ConfigBlockId& top_block,
-  const ModuleManager& module_manager, const FabricTile& fabric_tile,
-  const CircuitLibrary& circuit_lib, const MuxLibrary& mux_lib,
-  const DeviceGrid& grids, const size_t& layer, const AtomContext& atom_ctx,
-  const VprDeviceAnnotation& device_annotation,
+  const ModuleManager& module_manager, const ModuleNameMap& module_name_map,
+  const FabricTile& fabric_tile, const CircuitLibrary& circuit_lib,
+  const MuxLibrary& mux_lib, const DeviceGrid& grids, const size_t& layer,
+  const AtomContext& atom_ctx, const VprDeviceAnnotation& device_annotation,
   const VprClusteringAnnotation& cluster_annotation,
   const VprPlacementAnnotation& place_annotation,
   const VprBitstreamAnnotation& bitstream_annotation, const bool& verbose) {
@@ -992,10 +1004,10 @@ void build_grid_bitstream(
       }
 
       build_physical_block_bitstream(
-        bitstream_manager, parent_block, module_manager, fabric_tile, curr_tile,
-        circuit_lib, mux_lib, atom_ctx, device_annotation, cluster_annotation,
-        place_annotation, bitstream_annotation, grids, layer, grid_coord,
-        NUM_SIDES, verbose);
+        bitstream_manager, parent_block, module_manager, module_name_map,
+        fabric_tile, curr_tile, circuit_lib, mux_lib, atom_ctx,
+        device_annotation, cluster_annotation, place_annotation,
+        bitstream_annotation, grids, layer, grid_coord, NUM_SIDES, verbose);
     }
   }
   VTR_LOGV(verbose, "Done\n");
@@ -1040,10 +1052,10 @@ void build_grid_bitstream(
       }
 
       build_physical_block_bitstream(
-        bitstream_manager, parent_block, module_manager, fabric_tile, curr_tile,
-        circuit_lib, mux_lib, atom_ctx, device_annotation, cluster_annotation,
-        place_annotation, bitstream_annotation, grids, layer, io_coordinate,
-        io_side, verbose);
+        bitstream_manager, parent_block, module_manager, module_name_map,
+        fabric_tile, curr_tile, circuit_lib, mux_lib, atom_ctx,
+        device_annotation, cluster_annotation, place_annotation,
+        bitstream_annotation, grids, layer, io_coordinate, io_side, verbose);
     }
   }
   VTR_LOGV(verbose, "Done\n");

openfpga/src/fpga_bitstream/build_grid_bitstream.h

@@ -11,6 +11,7 @@
 #include "device_grid.h"
 #include "fabric_tile.h"
 #include "module_manager.h"
+#include "module_name_map.h"
 #include "mux_library.h"
 #include "vpr_bitstream_annotation.h"
 #include "vpr_clustering_annotation.h"
@@ -27,10 +28,10 @@ namespace openfpga {
 
 void build_grid_bitstream(
   BitstreamManager& bitstream_manager, const ConfigBlockId& top_block,
-  const ModuleManager& module_manager, const FabricTile& fabric_tile,
-  const CircuitLibrary& circuit_lib, const MuxLibrary& mux_lib,
-  const DeviceGrid& grids, const size_t& layer, const AtomContext& atom_ctx,
-  const VprDeviceAnnotation& device_annotation,
+  const ModuleManager& module_manager, const ModuleNameMap& module_name_map,
+  const FabricTile& fabric_tile, const CircuitLibrary& circuit_lib,
+  const MuxLibrary& mux_lib, const DeviceGrid& grids, const size_t& layer,
+  const AtomContext& atom_ctx, const VprDeviceAnnotation& device_annotation,
   const VprClusteringAnnotation& cluster_annotation,
   const VprPlacementAnnotation& place_annotation,
   const VprBitstreamAnnotation& bitstream_annotation, const bool& verbose);

openfpga/src/fpga_bitstream/build_routing_bitstream.cpp

@@ -33,10 +33,11 @@ namespace openfpga {
  *******************************************************************/
 static void build_switch_block_mux_bitstream(
   BitstreamManager& bitstream_manager, const ConfigBlockId& mux_mem_block,
-  const ModuleManager& module_manager, const CircuitLibrary& circuit_lib,
-  const MuxLibrary& mux_lib, const RRGraphView& rr_graph,
-  const RRNodeId& cur_rr_node, const std::vector<RRNodeId>& drive_rr_nodes,
-  const AtomContext& atom_ctx, const VprDeviceAnnotation& device_annotation,
+  const ModuleManager& module_manager, const ModuleNameMap& module_name_map,
+  const CircuitLibrary& circuit_lib, const MuxLibrary& mux_lib,
+  const RRGraphView& rr_graph, const RRNodeId& cur_rr_node,
+  const std::vector<RRNodeId>& drive_rr_nodes, const AtomContext& atom_ctx,
+  const VprDeviceAnnotation& device_annotation,
   const VprRoutingAnnotation& routing_annotation, const bool& verbose) {
   /* Check current rr_node is CHANX or CHANY*/
   VTR_ASSERT((CHANX == rr_graph.node_type(cur_rr_node)) ||
@@ -94,6 +95,7 @@ static void build_switch_block_mux_bitstream(
   std::string mem_module_name =
     generate_mux_subckt_name(circuit_lib, mux_model, datapath_mux_size,
                              std::string(MEMORY_MODULE_POSTFIX));
+  mem_module_name = module_name_map.name(mem_module_name);
   ModuleId mux_mem_module = module_manager.find_module(mem_module_name);
   VTR_ASSERT(true == module_manager.valid_module_id(mux_mem_module));
   ModulePortId mux_mem_out_port_id = module_manager.find_module_port(
@@ -152,9 +154,10 @@ static void build_switch_block_mux_bitstream(
 static void build_switch_block_interc_bitstream(
   BitstreamManager& bitstream_manager,
   const ConfigBlockId& sb_configurable_block,
-  const ModuleManager& module_manager, const CircuitLibrary& circuit_lib,
-  const MuxLibrary& mux_lib, const RRGraphView& rr_graph,
-  const AtomContext& atom_ctx, const VprDeviceAnnotation& device_annotation,
+  const ModuleManager& module_manager, const ModuleNameMap& module_name_map,
+  const CircuitLibrary& circuit_lib, const MuxLibrary& mux_lib,
+  const RRGraphView& rr_graph, const AtomContext& atom_ctx,
+  const VprDeviceAnnotation& device_annotation,
   const VprRoutingAnnotation& routing_annotation, const RRGSB& rr_gsb,
   const e_side& chan_side, const size_t& chan_node_id, const bool& verbose) {
   std::vector<RRNodeId> driver_rr_nodes;
@@ -190,9 +193,9 @@ static void build_switch_block_interc_bitstream(
              bitstream_manager.block_name(sb_configurable_block).c_str());
     /* This is a routing multiplexer! Generate bitstream */
     build_switch_block_mux_bitstream(
-      bitstream_manager, mux_mem_block, module_manager, circuit_lib, mux_lib,
-      rr_graph, cur_rr_node, driver_rr_nodes, atom_ctx, device_annotation,
-      routing_annotation, verbose);
+      bitstream_manager, mux_mem_block, module_manager, module_name_map,
+      circuit_lib, mux_lib, rr_graph, cur_rr_node, driver_rr_nodes, atom_ctx,
+      device_annotation, routing_annotation, verbose);
   } /*Nothing should be done else*/
 }
 
@@ -209,9 +212,9 @@ static void build_switch_block_interc_bitstream(
  *******************************************************************/
 static void build_switch_block_bitstream(
   BitstreamManager& bitstream_manager, const ConfigBlockId& sb_config_block,
-  const ModuleManager& module_manager, const CircuitLibrary& circuit_lib,
-  const MuxLibrary& mux_lib, const AtomContext& atom_ctx,
-  const VprDeviceAnnotation& device_annotation,
+  const ModuleManager& module_manager, const ModuleNameMap& module_name_map,
+  const CircuitLibrary& circuit_lib, const MuxLibrary& mux_lib,
+  const AtomContext& atom_ctx, const VprDeviceAnnotation& device_annotation,
   const VprRoutingAnnotation& routing_annotation, const RRGraphView& rr_graph,
   const RRGSB& rr_gsb, const bool& verbose) {
   /* Iterate over all the multiplexers */
@@ -229,9 +232,9 @@ static void build_switch_block_bitstream(
         continue;
       }
       build_switch_block_interc_bitstream(
-        bitstream_manager, sb_config_block, module_manager, circuit_lib,
-        mux_lib, rr_graph, atom_ctx, device_annotation, routing_annotation,
-        rr_gsb, side_manager.get_side(), itrack, verbose);
+        bitstream_manager, sb_config_block, module_manager, module_name_map,
+        circuit_lib, mux_lib, rr_graph, atom_ctx, device_annotation,
+        routing_annotation, rr_gsb, side_manager.get_side(), itrack, verbose);
     }
   }
 }
@@ -245,9 +248,9 @@ static void build_switch_block_bitstream(
  *******************************************************************/
 static void build_connection_block_mux_bitstream(
   BitstreamManager& bitstream_manager, const ConfigBlockId& mux_mem_block,
-  const ModuleManager& module_manager, const CircuitLibrary& circuit_lib,
-  const MuxLibrary& mux_lib, const AtomContext& atom_ctx,
-  const VprDeviceAnnotation& device_annotation,
+  const ModuleManager& module_manager, const ModuleNameMap& module_name_map,
+  const CircuitLibrary& circuit_lib, const MuxLibrary& mux_lib,
+  const AtomContext& atom_ctx, const VprDeviceAnnotation& device_annotation,
   const VprRoutingAnnotation& routing_annotation, const RRGraphView& rr_graph,
   const RRGSB& rr_gsb, const e_side& cb_ipin_side, const size_t& ipin_index,
   const bool& verbose) {
@@ -310,6 +313,7 @@ static void build_connection_block_mux_bitstream(
   std::string mem_module_name =
     generate_mux_subckt_name(circuit_lib, mux_model, datapath_mux_size,
                              std::string(MEMORY_MODULE_POSTFIX));
+  mem_module_name = module_name_map.name(mem_module_name);
   ModuleId mux_mem_module = module_manager.find_module(mem_module_name);
   VTR_ASSERT(true == module_manager.valid_module_id(mux_mem_module));
   ModulePortId mux_mem_out_port_id = module_manager.find_module_port(
@@ -368,9 +372,9 @@ static void build_connection_block_mux_bitstream(
 static void build_connection_block_interc_bitstream(
   BitstreamManager& bitstream_manager,
   const ConfigBlockId& cb_configurable_block,
-  const ModuleManager& module_manager, const CircuitLibrary& circuit_lib,
-  const MuxLibrary& mux_lib, const AtomContext& atom_ctx,
-  const VprDeviceAnnotation& device_annotation,
+  const ModuleManager& module_manager, const ModuleNameMap& module_name_map,
+  const CircuitLibrary& circuit_lib, const MuxLibrary& mux_lib,
+  const AtomContext& atom_ctx, const VprDeviceAnnotation& device_annotation,
   const VprRoutingAnnotation& routing_annotation, const RRGraphView& rr_graph,
   const RRGSB& rr_gsb, const e_side& cb_ipin_side, const size_t& ipin_index,
   const bool& verbose) {
@@ -402,9 +406,9 @@ static void build_connection_block_interc_bitstream(
              bitstream_manager.block_name(cb_configurable_block).c_str());
     /* This is a routing multiplexer! Generate bitstream */
     build_connection_block_mux_bitstream(
-      bitstream_manager, mux_mem_block, module_manager, circuit_lib, mux_lib,
-      atom_ctx, device_annotation, routing_annotation, rr_graph, rr_gsb,
-      cb_ipin_side, ipin_index, verbose);
+      bitstream_manager, mux_mem_block, module_manager, module_name_map,
+      circuit_lib, mux_lib, atom_ctx, device_annotation, routing_annotation,
+      rr_graph, rr_gsb, cb_ipin_side, ipin_index, verbose);
   } /*Nothing should be done else*/
 }
 
@@ -422,9 +426,9 @@ static void build_connection_block_interc_bitstream(
 static void build_connection_block_bitstream(
   BitstreamManager& bitstream_manager,
   const ConfigBlockId& cb_configurable_block,
-  const ModuleManager& module_manager, const CircuitLibrary& circuit_lib,
-  const MuxLibrary& mux_lib, const AtomContext& atom_ctx,
-  const VprDeviceAnnotation& device_annotation,
+  const ModuleManager& module_manager, const ModuleNameMap& module_name_map,
+  const CircuitLibrary& circuit_lib, const MuxLibrary& mux_lib,
+  const AtomContext& atom_ctx, const VprDeviceAnnotation& device_annotation,
   const VprRoutingAnnotation& routing_annotation, const RRGraphView& rr_graph,
   const RRGSB& rr_gsb, const t_rr_type& cb_type, const bool& verbose) {
   /* Find routing multiplexers on the sides of a Connection block where IPIN
@@ -439,9 +443,9 @@ static void build_connection_block_bitstream(
       VTR_LOGV(verbose, "\tGenerating bitstream for IPIN at '%s' side\n",
                side_manager.to_string().c_str());
       build_connection_block_interc_bitstream(
-        bitstream_manager, cb_configurable_block, module_manager, circuit_lib,
-        mux_lib, atom_ctx, device_annotation, routing_annotation, rr_graph,
-        rr_gsb, cb_ipin_side, inode, verbose);
+        bitstream_manager, cb_configurable_block, module_manager,
+        module_name_map, circuit_lib, mux_lib, atom_ctx, device_annotation,
+        routing_annotation, rr_graph, rr_gsb, cb_ipin_side, inode, verbose);
     }
   }
 }
@@ -452,9 +456,10 @@ static void build_connection_block_bitstream(
 static void build_connection_block_bitstreams(
   BitstreamManager& bitstream_manager,
   const ConfigBlockId& top_configurable_block,
-  const ModuleManager& module_manager, const FabricTile& fabric_tile,
-  const CircuitLibrary& circuit_lib, const MuxLibrary& mux_lib,
-  const AtomContext& atom_ctx, const VprDeviceAnnotation& device_annotation,
+  const ModuleManager& module_manager, const ModuleNameMap& module_name_map,
+  const FabricTile& fabric_tile, const CircuitLibrary& circuit_lib,
+  const MuxLibrary& mux_lib, const AtomContext& atom_ctx,
+  const VprDeviceAnnotation& device_annotation,
   const VprRoutingAnnotation& routing_annotation, const RRGraphView& rr_graph,
   const DeviceRRGSB& device_rr_gsb, const bool& compact_routing_hierarchy,
   const t_rr_type& cb_type, const bool& verbose) {
@@ -501,7 +506,8 @@ static void build_connection_block_bitstreams(
         cb_module_name =
           generate_connection_block_module_name(cb_type, unique_cb_coord);
       }
-      ModuleId cb_module = module_manager.find_module(cb_module_name);
+      ModuleId cb_module =
+        module_manager.find_module(module_name_map.name(cb_module_name));
       VTR_ASSERT(true == module_manager.valid_module_id(cb_module));
 
       /* Bypass empty blocks which have none configurable children */
@@ -578,9 +584,9 @@ static void build_connection_block_bitstreams(
       }
 
       build_connection_block_bitstream(
-        bitstream_manager, cb_configurable_block, module_manager, circuit_lib,
-        mux_lib, atom_ctx, device_annotation, routing_annotation, rr_graph,
-        rr_gsb, cb_type, verbose);
+        bitstream_manager, cb_configurable_block, module_manager,
+        module_name_map, circuit_lib, mux_lib, atom_ctx, device_annotation,
+        routing_annotation, rr_graph, rr_gsb, cb_type, verbose);
 
       VTR_LOGV(verbose, "\tDone\n");
     }
@@ -596,9 +602,10 @@ static void build_connection_block_bitstreams(
 void build_routing_bitstream(
   BitstreamManager& bitstream_manager,
   const ConfigBlockId& top_configurable_block,
-  const ModuleManager& module_manager, const FabricTile& fabric_tile,
-  const CircuitLibrary& circuit_lib, const MuxLibrary& mux_lib,
-  const AtomContext& atom_ctx, const VprDeviceAnnotation& device_annotation,
+  const ModuleManager& module_manager, const ModuleNameMap& module_name_map,
+  const FabricTile& fabric_tile, const CircuitLibrary& circuit_lib,
+  const MuxLibrary& mux_lib, const AtomContext& atom_ctx,
+  const VprDeviceAnnotation& device_annotation,
   const VprRoutingAnnotation& routing_annotation, const RRGraphView& rr_graph,
   const DeviceRRGSB& device_rr_gsb, const bool& compact_routing_hierarchy,
   const bool& verbose) {
@@ -636,7 +643,8 @@ void build_routing_bitstream(
         unique_sb_coord.set_y(unique_mirror.get_sb_y());
         sb_module_name = generate_switch_block_module_name(unique_sb_coord);
       }
-      ModuleId sb_module = module_manager.find_module(sb_module_name);
+      ModuleId sb_module =
+        module_manager.find_module(module_name_map.name(sb_module_name));
       VTR_ASSERT(true == module_manager.valid_module_id(sb_module));
 
       /* Bypass empty blocks which have none configurable children */
@@ -708,9 +716,9 @@ void build_routing_bitstream(
       }
 
       build_switch_block_bitstream(
-        bitstream_manager, sb_configurable_block, module_manager, circuit_lib,
-        mux_lib, atom_ctx, device_annotation, routing_annotation, rr_graph,
-        rr_gsb, verbose);
+        bitstream_manager, sb_configurable_block, module_manager,
+        module_name_map, circuit_lib, mux_lib, atom_ctx, device_annotation,
+        routing_annotation, rr_graph, rr_gsb, verbose);
 
       VTR_LOGV(verbose, "\tDone\n");
     }
@@ -725,17 +733,19 @@ void build_routing_bitstream(
   VTR_LOG("Generating bitstream for X-direction Connection blocks ...");
 
   build_connection_block_bitstreams(
-    bitstream_manager, top_configurable_block, module_manager, fabric_tile,
-    circuit_lib, mux_lib, atom_ctx, device_annotation, routing_annotation,
-    rr_graph, device_rr_gsb, compact_routing_hierarchy, CHANX, verbose);
+    bitstream_manager, top_configurable_block, module_manager, module_name_map,
+    fabric_tile, circuit_lib, mux_lib, atom_ctx, device_annotation,
+    routing_annotation, rr_graph, device_rr_gsb, compact_routing_hierarchy,
+    CHANX, verbose);
   VTR_LOG("Done\n");
 
   VTR_LOG("Generating bitstream for Y-direction Connection blocks ...");
 
   build_connection_block_bitstreams(
-    bitstream_manager, top_configurable_block, module_manager, fabric_tile,
-    circuit_lib, mux_lib, atom_ctx, device_annotation, routing_annotation,
-    rr_graph, device_rr_gsb, compact_routing_hierarchy, CHANY, verbose);
+    bitstream_manager, top_configurable_block, module_manager, module_name_map,
+    fabric_tile, circuit_lib, mux_lib, atom_ctx, device_annotation,
+    routing_annotation, rr_graph, device_rr_gsb, compact_routing_hierarchy,
+    CHANY, verbose);
   VTR_LOG("Done\n");
 }
 

openfpga/src/fpga_bitstream/build_routing_bitstream.h

@@ -14,6 +14,7 @@
 #include "device_rr_gsb.h"
 #include "fabric_tile.h"
 #include "module_manager.h"
+#include "module_name_map.h"
 #include "mux_library.h"
 #include "vpr_context.h"
 #include "vpr_device_annotation.h"
@@ -29,9 +30,10 @@ namespace openfpga {
 void build_routing_bitstream(
   BitstreamManager& bitstream_manager,
   const ConfigBlockId& top_configurable_block,
-  const ModuleManager& module_manager, const FabricTile& fabric_tile,
-  const CircuitLibrary& circuit_lib, const MuxLibrary& mux_lib,
-  const AtomContext& atom_ctx, const VprDeviceAnnotation& device_annotation,
+  const ModuleManager& module_manager, const ModuleNameMap& module_name_map,
+  const FabricTile& fabric_tile, const CircuitLibrary& circuit_lib,
+  const MuxLibrary& mux_lib, const AtomContext& atom_ctx,
+  const VprDeviceAnnotation& device_annotation,
   const VprRoutingAnnotation& routing_annotation, const RRGraphView& rr_graph,
   const DeviceRRGSB& device_rr_gsb, const bool& compact_routing_hierarchy,
   const bool& verbose);

openfpga/src/fpga_verilog/verilog_api.cpp

@@ -61,7 +61,7 @@ int fpga_fabric_verilog(
   const DecoderLibrary &decoder_lib, const DeviceContext &device_ctx,
   const VprDeviceAnnotation &device_annotation,
   const DeviceRRGSB &device_rr_gsb, const FabricTile &fabric_tile,
-  const FabricVerilogOption &options) {
+  const ModuleNameMap &module_name_map, const FabricVerilogOption &options) {
   vtr::ScopedStartFinishTimer timer("Write Verilog netlists for FPGA fabric\n");
 
   int status_code = CMD_EXEC_SUCCESS;
@@ -105,33 +105,36 @@ int fpga_fabric_verilog(
    * logic generation is not possible!!!
    */
   print_verilog_submodule(module_manager, netlist_manager, blwl_sr_banks,
-                          mux_lib, decoder_lib, circuit_lib, submodule_dir_path,
+                          mux_lib, decoder_lib, circuit_lib, module_name_map,
+                          submodule_dir_path,
                           std::string(DEFAULT_SUBMODULE_DIR_NAME), options);
 
   /* Generate routing blocks */
   if (true == options.compress_routing()) {
     print_verilog_unique_routing_modules(
       netlist_manager, const_cast<const ModuleManager &>(module_manager),
-      device_rr_gsb, rr_dir_path, std::string(DEFAULT_RR_DIR_NAME), options);
+      module_name_map, device_rr_gsb, rr_dir_path,
+      std::string(DEFAULT_RR_DIR_NAME), options);
   } else {
     VTR_ASSERT(false == options.compress_routing());
     print_verilog_flatten_routing_modules(
       netlist_manager, const_cast<const ModuleManager &>(module_manager),
-      device_rr_gsb, device_ctx.rr_graph, rr_dir_path,
+      module_name_map, device_rr_gsb, device_ctx.rr_graph, rr_dir_path,
       std::string(DEFAULT_RR_DIR_NAME), options);
   }
 
   /* Generate grids */
   print_verilog_grids(
     netlist_manager, const_cast<const ModuleManager &>(module_manager),
-    device_ctx, device_annotation, lb_dir_path,
+    module_name_map, device_ctx, device_annotation, lb_dir_path,
     std::string(DEFAULT_LB_DIR_NAME), options, options.verbose_output());
 
   /* Generate tiles */
   if (!fabric_tile.empty()) {
     status_code = print_verilog_tiles(
       netlist_manager, const_cast<const ModuleManager &>(module_manager),
-      tile_dir_path, fabric_tile, std::string(DEFAULT_TILE_DIR_NAME), options);
+      module_name_map, tile_dir_path, fabric_tile,
+      std::string(DEFAULT_TILE_DIR_NAME), options);
     if (status_code != CMD_EXEC_SUCCESS) {
       return CMD_EXEC_FATAL_ERROR;
     }
@@ -140,10 +143,10 @@ int fpga_fabric_verilog(
   /* Generate FPGA fabric */
   print_verilog_core_module(netlist_manager,
                             const_cast<const ModuleManager &>(module_manager),
-                            src_dir_path, options);
+                            module_name_map, src_dir_path, options);
   print_verilog_top_module(netlist_manager,
                            const_cast<const ModuleManager &>(module_manager),
-                           src_dir_path, options);
+                           module_name_map, src_dir_path, options);
 
   /* Generate an netlist including all the fabric-related netlists */
   print_verilog_fabric_include_netlist(
@@ -172,7 +175,7 @@ int fpga_verilog_full_testbench(
   const AtomContext &atom_ctx, const PlacementContext &place_ctx,
   const PinConstraints &pin_constraints, const BusGroup &bus_group,
   const std::string &bitstream_file, const IoLocationMap &io_location_map,
-  const IoNameMap &io_name_map,
+  const IoNameMap &io_name_map, const ModuleNameMap &module_name_map,
   const FabricGlobalPortInfo &fabric_global_port_info,
   const VprNetlistAnnotation &netlist_annotation,
   const CircuitLibrary &circuit_lib,
@@ -200,7 +203,7 @@ int fpga_verilog_full_testbench(
     module_manager, bitstream_manager, fabric_bitstream, blwl_sr_banks,
     circuit_lib, config_protocol, fabric_global_port_info, atom_ctx, place_ctx,
     pin_constraints, bus_group, bitstream_file, io_location_map, io_name_map,
-    netlist_annotation, netlist_name, top_testbench_file_path,
+    module_name_map, netlist_annotation, netlist_name, top_testbench_file_path,
     simulation_setting, options);
 
   /* Generate a Verilog file including all the netlists that have been generated
@@ -222,7 +225,7 @@ int fpga_verilog_preconfigured_fabric_wrapper(
   const BitstreamManager &bitstream_manager, const AtomContext &atom_ctx,
   const PlacementContext &place_ctx, const PinConstraints &pin_constraints,
   const BusGroup &bus_group, const IoLocationMap &io_location_map,
-  const IoNameMap &io_name_map,
+  const IoNameMap &io_name_map, const ModuleNameMap &module_name_map,
   const FabricGlobalPortInfo &fabric_global_port_info,
   const VprNetlistAnnotation &netlist_annotation,
   const CircuitLibrary &circuit_lib, const ConfigProtocol &config_protocol,
@@ -247,8 +250,8 @@ int fpga_verilog_preconfigured_fabric_wrapper(
   status = print_verilog_preconfig_top_module(
     module_manager, bitstream_manager, config_protocol, circuit_lib,
     fabric_global_port_info, atom_ctx, place_ctx, pin_constraints, bus_group,
-    io_location_map, io_name_map, netlist_annotation, netlist_name,
-    formal_verification_top_netlist_file_path, options);
+    io_location_map, io_name_map, module_name_map, netlist_annotation,
+    netlist_name, formal_verification_top_netlist_file_path, options);
 
   return status;
 }
@@ -261,7 +264,7 @@ int fpga_verilog_mock_fpga_wrapper(
   const ModuleManager &module_manager, const AtomContext &atom_ctx,
   const PlacementContext &place_ctx, const PinConstraints &pin_constraints,
   const BusGroup &bus_group, const IoLocationMap &io_location_map,
-  const IoNameMap &io_name_map,
+  const IoNameMap &io_name_map, const ModuleNameMap &module_name_map,
   const FabricGlobalPortInfo &fabric_global_port_info,
   const VprNetlistAnnotation &netlist_annotation,
   const VerilogTestbenchOption &options) {
@@ -286,7 +289,7 @@ int fpga_verilog_mock_fpga_wrapper(
   std::string netlist_file_path = src_dir_path + netlist_file_name;
   status = print_verilog_mock_fpga_wrapper(
     module_manager, fabric_global_port_info, atom_ctx, place_ctx,
-    pin_constraints, bus_group, io_location_map, io_name_map,
+    pin_constraints, bus_group, io_location_map, io_name_map, module_name_map,
     netlist_annotation, netlist_name, netlist_file_path, options);
 
   /* Add fname to the netlist name list */
@@ -316,8 +319,9 @@ int fpga_verilog_mock_fpga_wrapper(
  *verification and formal verification purpose.
  ********************************************************************/
 int fpga_verilog_preconfigured_testbench(
-  const ModuleManager &module_manager, const AtomContext &atom_ctx,
-  const PinConstraints &pin_constraints, const BusGroup &bus_group,
+  const ModuleManager &module_manager, const ModuleNameMap &module_name_map,
+  const AtomContext &atom_ctx, const PinConstraints &pin_constraints,
+  const BusGroup &bus_group,
   const FabricGlobalPortInfo &fabric_global_port_info,
   const VprNetlistAnnotation &netlist_annotation,
   const SimulationSetting &simulation_setting,
@@ -340,8 +344,8 @@ int fpga_verilog_preconfigured_testbench(
     std::string(RANDOM_TOP_TESTBENCH_VERILOG_FILE_POSTFIX);
   print_verilog_random_top_testbench(
     netlist_name, random_top_testbench_file_path, atom_ctx, netlist_annotation,
-    module_manager, fabric_global_port_info, pin_constraints, bus_group,
-    simulation_setting, options);
+    module_manager, module_name_map, fabric_global_port_info, pin_constraints,
+    bus_group, simulation_setting, options);
 
   /* Generate a Verilog file including all the netlists that have been generated
    */

openfpga/src/fpga_verilog/verilog_api.h

@@ -22,6 +22,7 @@
 #include "io_name_map.h"
 #include "memory_bank_shift_register_banks.h"
 #include "module_manager.h"
+#include "module_name_map.h"
 #include "mux_library.h"
 #include "netlist_manager.h"
 #include "pin_constraints.h"
@@ -45,7 +46,7 @@ int fpga_fabric_verilog(
   const DecoderLibrary& decoder_lib, const DeviceContext& device_ctx,
   const VprDeviceAnnotation& device_annotation,
   const DeviceRRGSB& device_rr_gsb, const FabricTile& fabric_tile,
-  const FabricVerilogOption& options);
+  const ModuleNameMap& module_name_map, const FabricVerilogOption& options);
 
 int fpga_verilog_full_testbench(
   const ModuleManager& module_manager,
@@ -55,7 +56,7 @@ int fpga_verilog_full_testbench(
   const AtomContext& atom_ctx, const PlacementContext& place_ctx,
   const PinConstraints& pin_constraints, const BusGroup& bus_group,
   const std::string& bitstream_file, const IoLocationMap& io_location_map,
-  const IoNameMap& io_name_map,
+  const IoNameMap& io_name_map, const ModuleNameMap& module_name_map,
   const FabricGlobalPortInfo& fabric_global_port_info,
   const VprNetlistAnnotation& netlist_annotation,
   const CircuitLibrary& circuit_lib,
@@ -67,7 +68,7 @@ int fpga_verilog_preconfigured_fabric_wrapper(
   const BitstreamManager& bitstream_manager, const AtomContext& atom_ctx,
   const PlacementContext& place_ctx, const PinConstraints& pin_constraints,
   const BusGroup& bus_group, const IoLocationMap& io_location_map,
-  const IoNameMap& io_name_map,
+  const IoNameMap& io_name_map, const ModuleNameMap& module_name_map,
   const FabricGlobalPortInfo& fabric_global_port_info,
   const VprNetlistAnnotation& netlist_annotation,
   const CircuitLibrary& circuit_lib, const ConfigProtocol& config_protocol,
@@ -77,14 +78,15 @@ int fpga_verilog_mock_fpga_wrapper(
   const ModuleManager& module_manager, const AtomContext& atom_ctx,
   const PlacementContext& place_ctx, const PinConstraints& pin_constraints,
   const BusGroup& bus_group, const IoLocationMap& io_location_map,
-  const IoNameMap& io_name_map,
+  const IoNameMap& io_name_map, const ModuleNameMap& module_name_map,
   const FabricGlobalPortInfo& fabric_global_port_info,
   const VprNetlistAnnotation& netlist_annotation,
   const VerilogTestbenchOption& options);
 
 int fpga_verilog_preconfigured_testbench(
-  const ModuleManager& module_manager, const AtomContext& atom_ctx,
-  const PinConstraints& pin_constraints, const BusGroup& bus_group,
+  const ModuleManager& module_manager, const ModuleNameMap& module_name_map,
+  const AtomContext& atom_ctx, const PinConstraints& pin_constraints,
+  const BusGroup& bus_group,
   const FabricGlobalPortInfo& fabric_global_port_info,
   const VprNetlistAnnotation& netlist_annotation,
   const SimulationSetting& simulation_setting,

openfpga/src/fpga_verilog/verilog_decoders.cpp

@@ -42,6 +42,7 @@ namespace openfpga {
 static void print_verilog_mux_local_decoder_module(
   std::fstream& fp, const ModuleManager& module_manager,
   const DecoderLibrary& decoder_lib, const DecoderId& decoder,
+  const ModuleNameMap& module_name_map,
   const e_verilog_default_net_type& default_net_type) {
   /* Get the number of inputs */
   size_t addr_size = decoder_lib.addr_size(decoder);
@@ -51,8 +52,8 @@ static void print_verilog_mux_local_decoder_module(
   VTR_ASSERT(true == valid_file_stream(fp));
 
   /* TODO: create a name for the local encoder */
-  std::string module_name =
-    generate_mux_local_decoder_subckt_name(addr_size, data_size);
+  std::string module_name = module_name_map.name(
+    generate_mux_local_decoder_subckt_name(addr_size, data_size));
 
   /* Create a Verilog Module based on the circuit model, and add to module
    * manager */
@@ -180,8 +181,8 @@ static void print_verilog_mux_local_decoder_module(
 void print_verilog_submodule_mux_local_decoders(
   const ModuleManager& module_manager, NetlistManager& netlist_manager,
   const MuxLibrary& mux_lib, const CircuitLibrary& circuit_lib,
-  const std::string& submodule_dir, const std::string& submodule_dir_name,
-  const FabricVerilogOption& options) {
+  const ModuleNameMap& module_name_map, const std::string& submodule_dir,
+  const std::string& submodule_dir_name, const FabricVerilogOption& options) {
   std::string verilog_fname(LOCAL_ENCODER_VERILOG_FILE_NAME);
   std::string verilog_fpath(submodule_dir + verilog_fname);
 
@@ -235,7 +236,8 @@ void print_verilog_submodule_mux_local_decoders(
   /* Generate Verilog modules for the found unique local encoders */
   for (const auto& decoder : decoder_lib.decoders()) {
     print_verilog_mux_local_decoder_module(fp, module_manager, decoder_lib,
-                                           decoder, options.default_net_type());
+                                           decoder, module_name_map,
+                                           options.default_net_type());
   }
 
   /* Close the file stream */
@@ -280,6 +282,7 @@ void print_verilog_submodule_mux_local_decoders(
 static void print_verilog_arch_decoder_module(
   std::fstream& fp, const ModuleManager& module_manager,
   const DecoderLibrary& decoder_lib, const DecoderId& decoder,
+  const ModuleNameMap& module_name_map,
   const e_verilog_default_net_type& default_net_type) {
   /* Get the number of inputs */
   size_t addr_size = decoder_lib.addr_size(decoder);
@@ -289,8 +292,8 @@ static void print_verilog_arch_decoder_module(
   VTR_ASSERT(true == valid_file_stream(fp));
 
   /* Create a name for the decoder */
-  std::string module_name =
-    generate_memory_decoder_subckt_name(addr_size, data_size);
+  std::string module_name = module_name_map.name(
+    generate_memory_decoder_subckt_name(addr_size, data_size));
 
   /* Create a Verilog Module based on the circuit model, and add to module
    * manager */
@@ -603,6 +606,7 @@ static void print_verilog_arch_decoder_module(
 static void print_verilog_arch_decoder_with_data_in_module(
   std::fstream& fp, const ModuleManager& module_manager,
   const DecoderLibrary& decoder_lib, const DecoderId& decoder,
+  const ModuleNameMap& module_name_map,
   const e_verilog_default_net_type& default_net_type) {
   /* Get the number of inputs */
   size_t addr_size = decoder_lib.addr_size(decoder);
@@ -613,8 +617,8 @@ static void print_verilog_arch_decoder_with_data_in_module(
   VTR_ASSERT(true == valid_file_stream(fp));
 
   /* Create a name for the decoder */
-  std::string module_name =
-    generate_memory_decoder_with_data_in_subckt_name(addr_size, data_size);
+  std::string module_name = module_name_map.name(
+    generate_memory_decoder_with_data_in_subckt_name(addr_size, data_size));
 
   /* Create a Verilog Module based on the circuit model, and add to module
    * manager */
@@ -778,8 +782,9 @@ static void print_verilog_arch_decoder_with_data_in_module(
  ***************************************************************************************/
 void print_verilog_submodule_arch_decoders(
   const ModuleManager& module_manager, NetlistManager& netlist_manager,
-  const DecoderLibrary& decoder_lib, const std::string& submodule_dir,
-  const std::string& submodule_dir_name, const FabricVerilogOption& options) {
+  const DecoderLibrary& decoder_lib, const ModuleNameMap& module_name_map,
+  const std::string& submodule_dir, const std::string& submodule_dir_name,
+  const FabricVerilogOption& options) {
   std::string verilog_fname(ARCH_ENCODER_VERILOG_FILE_NAME);
   std::string verilog_fpath(submodule_dir + verilog_fname);
 
@@ -801,10 +806,12 @@ void print_verilog_submodule_arch_decoders(
   for (const auto& decoder : decoder_lib.decoders()) {
     if (true == decoder_lib.use_data_in(decoder)) {
       print_verilog_arch_decoder_with_data_in_module(
-        fp, module_manager, decoder_lib, decoder, options.default_net_type());
+        fp, module_manager, decoder_lib, decoder, module_name_map,
+        options.default_net_type());
     } else {
       print_verilog_arch_decoder_module(fp, module_manager, decoder_lib,
-                                        decoder, options.default_net_type());
+                                        decoder, module_name_map,
+                                        options.default_net_type());
     }
   }
 

openfpga/src/fpga_verilog/verilog_decoders.h

@@ -12,6 +12,7 @@
 #include "decoder_library.h"
 #include "fabric_verilog_options.h"
 #include "module_manager.h"
+#include "module_name_map.h"
 #include "mux_graph.h"
 #include "mux_library.h"
 #include "netlist_manager.h"
@@ -27,13 +28,14 @@ namespace openfpga {
 void print_verilog_submodule_mux_local_decoders(
   const ModuleManager& module_manager, NetlistManager& netlist_manager,
   const MuxLibrary& mux_lib, const CircuitLibrary& circuit_lib,
-  const std::string& submodule_dir, const std::string& submodule_dir_name,
-  const FabricVerilogOption& options);
+  const ModuleNameMap& module_name_map, const std::string& submodule_dir,
+  const std::string& submodule_dir_name, const FabricVerilogOption& options);
 
 void print_verilog_submodule_arch_decoders(
   const ModuleManager& module_manager, NetlistManager& netlist_manager,
-  const DecoderLibrary& decoder_lib, const std::string& submodule_dir,
-  const std::string& submodule_dir_name, const FabricVerilogOption& options);
+  const DecoderLibrary& decoder_lib, const ModuleNameMap& module_name_map,
+  const std::string& submodule_dir, const std::string& submodule_dir_name,
+  const FabricVerilogOption& options);
 
 } /* end namespace openfpga */
 

openfpga/src/fpga_verilog/verilog_essential_gates.cpp

@@ -151,6 +151,7 @@ static void print_verilog_invbuf_body(std::fstream& fp,
 static void print_verilog_invbuf_module(
   const ModuleManager& module_manager, std::fstream& fp,
   const CircuitLibrary& circuit_lib, const CircuitModelId& circuit_model,
+  const ModuleNameMap& module_name_map,
   const e_verilog_default_net_type& default_net_type) {
   /* Ensure a valid file handler*/
   VTR_ASSERT(true == valid_file_stream(fp));
@@ -175,8 +176,8 @@ static void print_verilog_invbuf_module(
 
   /* Create a Verilog Module based on the circuit model, and add to module
    * manager */
-  ModuleId module_id =
-    module_manager.find_module(circuit_lib.model_name(circuit_model));
+  ModuleId module_id = module_manager.find_module(
+    module_name_map.name(circuit_lib.model_name(circuit_model)));
   VTR_ASSERT(true == module_manager.valid_module_id(module_id));
 
   /* dump module definition + ports */
@@ -220,6 +221,7 @@ static void print_verilog_invbuf_module(
 static void print_verilog_passgate_module(
   const ModuleManager& module_manager, std::fstream& fp,
   const CircuitLibrary& circuit_lib, const CircuitModelId& circuit_model,
+  const ModuleNameMap& module_name_map,
   const e_verilog_default_net_type& default_net_type) {
   /* Ensure a valid file handler*/
   VTR_ASSERT(true == valid_file_stream(fp));
@@ -270,8 +272,8 @@ static void print_verilog_passgate_module(
 
   /* Create a Verilog Module based on the circuit model, and add to module
    * manager */
-  ModuleId module_id =
-    module_manager.find_module(circuit_lib.model_name(circuit_model));
+  ModuleId module_id = module_manager.find_module(
+    module_name_map.name(circuit_lib.model_name(circuit_model)));
   VTR_ASSERT(true == module_manager.valid_module_id(module_id));
 
   /* dump module definition + ports */
@@ -443,6 +445,7 @@ static void print_verilog_mux2_gate_body(
 static void print_verilog_gate_module(
   const ModuleManager& module_manager, std::fstream& fp,
   const CircuitLibrary& circuit_lib, const CircuitModelId& circuit_model,
+  const ModuleNameMap& module_name_map,
   const e_verilog_default_net_type& default_net_type) {
   /* Ensure a valid file handler*/
   VTR_ASSERT(true == valid_file_stream(fp));
@@ -465,8 +468,8 @@ static void print_verilog_gate_module(
 
   /* Create a Verilog Module based on the circuit model, and add to module
    * manager */
-  ModuleId module_id =
-    module_manager.find_module(circuit_lib.model_name(circuit_model));
+  ModuleId module_id = module_manager.find_module(
+    module_name_map.name(circuit_lib.model_name(circuit_model)));
   VTR_ASSERT(true == module_manager.valid_module_id(module_id));
 
   /* dump module definition + ports */
@@ -506,11 +509,12 @@ static void print_verilog_gate_module(
  ***********************************************/
 static void print_verilog_constant_generator_module(
   const ModuleManager& module_manager, std::fstream& fp,
-  const size_t& const_value,
+  const size_t& const_value, const ModuleNameMap& module_name_map,
   const e_verilog_default_net_type& default_net_type) {
   /* Find the module in module manager */
   std::string module_name = generate_const_value_module_name(const_value);
-  ModuleId const_val_module = module_manager.find_module(module_name);
+  ModuleId const_val_module =
+    module_manager.find_module(module_name_map.name(module_name));
   VTR_ASSERT(true == module_manager.valid_module_id(const_val_module));
 
   /* Ensure a valid file handler*/
@@ -544,6 +548,7 @@ void print_verilog_submodule_essentials(const ModuleManager& module_manager,
                                         const std::string& submodule_dir,
                                         const std::string& submodule_dir_name,
                                         const CircuitLibrary& circuit_lib,
+                                        const ModuleNameMap& module_name_map,
                                         const FabricVerilogOption& options) {
   std::string verilog_fname(ESSENTIALS_VERILOG_FILE_NAME);
   std::string verilog_fpath = submodule_dir + verilog_fname;
@@ -563,11 +568,11 @@ void print_verilog_submodule_essentials(const ModuleManager& module_manager,
 
   /* Print constant generators */
   /* VDD */
-  print_verilog_constant_generator_module(module_manager, fp, 0,
-                                          options.default_net_type());
+  print_verilog_constant_generator_module(
+    module_manager, fp, 0, module_name_map, options.default_net_type());
   /* GND */
-  print_verilog_constant_generator_module(module_manager, fp, 1,
-                                          options.default_net_type());
+  print_verilog_constant_generator_module(
+    module_manager, fp, 1, module_name_map, options.default_net_type());
 
   for (const auto& circuit_model : circuit_lib.models()) {
     /* By pass user-defined modules */
@@ -576,17 +581,19 @@ void print_verilog_submodule_essentials(const ModuleManager& module_manager,
     }
     if (CIRCUIT_MODEL_INVBUF == circuit_lib.model_type(circuit_model)) {
       print_verilog_invbuf_module(module_manager, fp, circuit_lib,
-                                  circuit_model, options.default_net_type());
+                                  circuit_model, module_name_map,
+                                  options.default_net_type());
       continue;
     }
     if (CIRCUIT_MODEL_PASSGATE == circuit_lib.model_type(circuit_model)) {
       print_verilog_passgate_module(module_manager, fp, circuit_lib,
-                                    circuit_model, options.default_net_type());
+                                    circuit_model, module_name_map,
+                                    options.default_net_type());
       continue;
     }
     if (CIRCUIT_MODEL_GATE == circuit_lib.model_type(circuit_model)) {
       print_verilog_gate_module(module_manager, fp, circuit_lib, circuit_model,
-                                options.default_net_type());
+                                module_name_map, options.default_net_type());
       continue;
     }
   }

openfpga/src/fpga_verilog/verilog_essential_gates.h

@@ -9,6 +9,7 @@
 #include "circuit_library.h"
 #include "fabric_verilog_options.h"
 #include "module_manager.h"
+#include "module_name_map.h"
 #include "netlist_manager.h"
 #include "verilog_port_types.h"
 
@@ -24,6 +25,7 @@ void print_verilog_submodule_essentials(const ModuleManager& module_manager,
                                         const std::string& submodule_dir,
                                         const std::string& submodule_dir_name,
                                         const CircuitLibrary& circuit_lib,
+                                        const ModuleNameMap& module_name_map,
                                         const FabricVerilogOption& options);
 
 } /* end namespace openfpga */

openfpga/src/fpga_verilog/verilog_formal_random_top_testbench.cpp

@@ -52,7 +52,7 @@ constexpr const char* FORMAL_TB_SIM_START_PORT_NAME = "sim_start";
  *******************************************************************/
 static void print_verilog_top_random_testbench_ports(
   std::fstream& fp, const ModuleManager& module_manager,
-  const std::string& circuit_name,
+  const ModuleNameMap& module_name_map, const std::string& circuit_name,
   const std::vector<std::string>& clock_port_names, const AtomContext& atom_ctx,
   const VprNetlistAnnotation& netlist_annotation,
   const VerilogTestbenchOption& options) {
@@ -82,10 +82,11 @@ static void print_verilog_top_random_testbench_ports(
   fp << std::endl;
 
   print_verilog_testbench_shared_ports(
-    fp, module_manager, FabricGlobalPortInfo(), PinConstraints(), atom_ctx,
-    netlist_annotation, clock_port_names, std::string(),
-    std::string(BENCHMARK_PORT_POSTFIX), std::string(FPGA_PORT_POSTFIX),
-    std::string(CHECKFLAG_PORT_POSTFIX), options.no_self_checking());
+    fp, module_manager, module_name_map, FabricGlobalPortInfo(),
+    PinConstraints(), atom_ctx, netlist_annotation, clock_port_names,
+    std::string(), std::string(BENCHMARK_PORT_POSTFIX),
+    std::string(FPGA_PORT_POSTFIX), std::string(CHECKFLAG_PORT_POSTFIX),
+    options.no_self_checking());
 
   /* Instantiate an integer to count the number of error
    * and determine if the simulation succeed or failed
@@ -168,7 +169,8 @@ static void print_verilog_random_testbench_fpga_instance(
 static void print_verilog_random_testbench_reset_stimuli(
   std::fstream& fp, const AtomContext& atom_ctx,
   const VprNetlistAnnotation& netlist_annotation,
-  const ModuleManager& module_manager, const FabricGlobalPortInfo& global_ports,
+  const ModuleManager& module_manager, const ModuleNameMap& module_name_map,
+  const FabricGlobalPortInfo& global_ports,
   const PinConstraints& pin_constraints,
   const std::vector<std::string>& clock_port_names,
   const BasicPort& clock_port) {
@@ -199,18 +201,18 @@ static void print_verilog_random_testbench_reset_stimuli(
     /* Bypass any constained net that are mapped to a global port of the FPGA
      * fabric because their stimulus cannot be random
      */
-    if (false ==
-        port_is_fabric_global_reset_port(global_ports, module_manager,
-                                         pin_constraints.net_pin(block_name))) {
+    if (false == port_is_fabric_global_reset_port(
+                   global_ports, module_manager, module_name_map,
+                   pin_constraints.net_pin(block_name))) {
       continue;
     }
 
     /* Generete stimuli for this net which is how reset signal works */
     BasicPort reset_port(block_name, 1);
     size_t initial_value = 1;
-    if (1 ==
-        global_ports.global_port_default_value(find_fabric_global_port(
-          global_ports, module_manager, pin_constraints.net_pin(block_name)))) {
+    if (1 == global_ports.global_port_default_value(find_fabric_global_port(
+               global_ports, module_manager, module_name_map,
+               pin_constraints.net_pin(block_name)))) {
       initial_value = 0;
     }
 
@@ -270,7 +272,8 @@ static void print_verilog_random_testbench_reset_stimuli(
 void print_verilog_random_top_testbench(
   const std::string& circuit_name, const std::string& verilog_fname,
   const AtomContext& atom_ctx, const VprNetlistAnnotation& netlist_annotation,
-  const ModuleManager& module_manager, const FabricGlobalPortInfo& global_ports,
+  const ModuleManager& module_manager, const ModuleNameMap& module_name_map,
+  const FabricGlobalPortInfo& global_ports,
   const PinConstraints& pin_constraints, const BusGroup& bus_group,
   const SimulationSetting& simulation_parameters,
   const VerilogTestbenchOption& options) {
@@ -301,9 +304,9 @@ void print_verilog_random_top_testbench(
     find_atom_netlist_clock_port_names(atom_ctx.nlist, netlist_annotation);
 
   /* Start of testbench */
-  print_verilog_top_random_testbench_ports(fp, module_manager, circuit_name,
-                                           clock_port_names, atom_ctx,
-                                           netlist_annotation, options);
+  print_verilog_top_random_testbench_ports(
+    fp, module_manager, module_name_map, circuit_name, clock_port_names,
+    atom_ctx, netlist_annotation, options);
 
   /* Call defined top-level module */
   print_verilog_random_testbench_fpga_instance(
@@ -329,12 +332,12 @@ void print_verilog_random_top_testbench(
    * limitation should be removed!
    */
   print_verilog_random_testbench_reset_stimuli(
-    fp, atom_ctx, netlist_annotation, module_manager, global_ports,
-    pin_constraints, clock_port_names, clock_ports[0]);
+    fp, atom_ctx, netlist_annotation, module_manager, module_name_map,
+    global_ports, pin_constraints, clock_port_names, clock_ports[0]);
 
   print_verilog_testbench_random_stimuli(
-    fp, atom_ctx, netlist_annotation, module_manager, global_ports,
-    pin_constraints, clock_port_names, std::string(),
+    fp, atom_ctx, netlist_annotation, module_manager, module_name_map,
+    global_ports, pin_constraints, clock_port_names, std::string(),
     std::string(CHECKFLAG_PORT_POSTFIX), clock_ports,
     options.no_self_checking());
 

openfpga/src/fpga_verilog/verilog_formal_random_top_testbench.h

@@ -9,6 +9,7 @@
 #include "bus_group.h"
 #include "fabric_global_port_info.h"
 #include "module_manager.h"
+#include "module_name_map.h"
 #include "pin_constraints.h"
 #include "simulation_setting.h"
 #include "verilog_testbench_options.h"
@@ -25,7 +26,8 @@ namespace openfpga {
 void print_verilog_random_top_testbench(
   const std::string& circuit_name, const std::string& verilog_fname,
   const AtomContext& atom_ctx, const VprNetlistAnnotation& netlist_annotation,
-  const ModuleManager& module_manager, const FabricGlobalPortInfo& global_ports,
+  const ModuleManager& module_manager, const ModuleNameMap& module_name_map,
+  const FabricGlobalPortInfo& global_ports,
   const PinConstraints& pin_constraints, const BusGroup& bus_group,
   const SimulationSetting& simulation_parameters,
   const VerilogTestbenchOption& options);

openfpga/src/fpga_verilog/verilog_grid.cpp

@@ -66,9 +66,9 @@ namespace openfpga {
  *******************************************************************/
 static void print_verilog_primitive_block(
   NetlistManager& netlist_manager, const ModuleManager& module_manager,
-  const std::string& subckt_dir, const std::string& subckt_dir_name,
-  t_pb_graph_node* primitive_pb_graph_node, const FabricVerilogOption& options,
-  const bool& verbose) {
+  const ModuleNameMap& module_name_map, const std::string& subckt_dir,
+  const std::string& subckt_dir_name, t_pb_graph_node* primitive_pb_graph_node,
+  const FabricVerilogOption& options, const bool& verbose) {
   /* Ensure a valid pb_graph_node */
   if (nullptr == primitive_pb_graph_node) {
     VTR_LOGF_ERROR(__FILE__, __LINE__, "Invalid primitive_pb_graph_node!\n");
@@ -101,6 +101,7 @@ static void print_verilog_primitive_block(
   /* Generate the module name for this primitive pb_graph_node*/
   std::string primitive_module_name =
     generate_physical_block_module_name(primitive_pb_graph_node->pb_type);
+  primitive_module_name = module_name_map.name(primitive_module_name);
 
   /* Create a module of the primitive LUT and register it to module manager */
   ModuleId primitive_module = module_manager.find_module(primitive_module_name);
@@ -150,6 +151,7 @@ static void print_verilog_primitive_block(
  *******************************************************************/
 static void rec_print_verilog_logical_tile(
   NetlistManager& netlist_manager, const ModuleManager& module_manager,
+  const ModuleNameMap& module_name_map,
   const VprDeviceAnnotation& device_annotation, const std::string& subckt_dir,
   const std::string& subckt_dir_name, t_pb_graph_node* physical_pb_graph_node,
   const FabricVerilogOption& options, const bool& verbose) {
@@ -172,8 +174,8 @@ static void rec_print_verilog_logical_tile(
     for (int ipb = 0; ipb < physical_mode->num_pb_type_children; ++ipb) {
       /* Go recursive to visit the children */
       rec_print_verilog_logical_tile(
-        netlist_manager, module_manager, device_annotation, subckt_dir,
-        subckt_dir_name,
+        netlist_manager, module_manager, module_name_map, device_annotation,
+        subckt_dir, subckt_dir_name,
         &(physical_pb_graph_node
             ->child_pb_graph_nodes[physical_mode->index][ipb][0]),
         options, verbose);
@@ -182,9 +184,9 @@ static void rec_print_verilog_logical_tile(
 
   /* For leaf node, a primitive Verilog module will be generated. */
   if (true == is_primitive_pb_type(physical_pb_type)) {
-    print_verilog_primitive_block(netlist_manager, module_manager, subckt_dir,
-                                  subckt_dir_name, physical_pb_graph_node,
-                                  options, verbose);
+    print_verilog_primitive_block(netlist_manager, module_manager,
+                                  module_name_map, subckt_dir, subckt_dir_name,
+                                  physical_pb_graph_node, options, verbose);
     /* Finish for primitive node, return */
     return;
   }
@@ -214,6 +216,7 @@ static void rec_print_verilog_logical_tile(
   /* Generate the name of the Verilog module for this pb_type */
   std::string pb_module_name =
     generate_physical_block_module_name(physical_pb_type);
+  pb_module_name = module_name_map.name(pb_module_name);
 
   /* Register the Verilog module in module manager */
   ModuleId pb_module = module_manager.find_module(pb_module_name);
@@ -261,6 +264,7 @@ static void rec_print_verilog_logical_tile(
  *****************************************************************************/
 static void print_verilog_logical_tile_netlist(
   NetlistManager& netlist_manager, const ModuleManager& module_manager,
+  const ModuleNameMap& module_name_map,
   const VprDeviceAnnotation& device_annotation, const std::string& subckt_dir,
   const std::string& subckt_dir_name, t_pb_graph_node* pb_graph_head,
   const FabricVerilogOption& options, const bool& verbose) {
@@ -276,9 +280,9 @@ static void print_verilog_logical_tile_netlist(
    */
   /* Print Verilog modules starting from the top-level pb_type/pb_graph_node,
    * and traverse the graph in a recursive way */
-  rec_print_verilog_logical_tile(netlist_manager, module_manager,
-                                 device_annotation, subckt_dir, subckt_dir_name,
-                                 pb_graph_head, options, verbose);
+  rec_print_verilog_logical_tile(
+    netlist_manager, module_manager, module_name_map, device_annotation,
+    subckt_dir, subckt_dir_name, pb_graph_head, options, verbose);
 
   VTR_LOG("Done\n");
   VTR_LOG("\n");
@@ -294,9 +298,9 @@ static void print_verilog_logical_tile_netlist(
  *****************************************************************************/
 static void print_verilog_physical_tile_netlist(
   NetlistManager& netlist_manager, const ModuleManager& module_manager,
-  const std::string& subckt_dir, const std::string& subckt_dir_name,
-  t_physical_tile_type_ptr phy_block_type, const e_side& border_side,
-  const FabricVerilogOption& options) {
+  const ModuleNameMap& module_name_map, const std::string& subckt_dir,
+  const std::string& subckt_dir_name, t_physical_tile_type_ptr phy_block_type,
+  const e_side& border_side, const FabricVerilogOption& options) {
   /* Give a name to the Verilog netlist */
   std::string verilog_fname(generate_grid_block_netlist_name(
     std::string(GRID_MODULE_NAME_PREFIX) + std::string(phy_block_type->name),
@@ -334,6 +338,7 @@ static void print_verilog_physical_tile_netlist(
   std::string grid_module_name = generate_grid_block_module_name(
     std::string(GRID_VERILOG_FILE_NAME_PREFIX),
     std::string(phy_block_type->name), is_io_type(phy_block_type), border_side);
+  grid_module_name = module_name_map.name(grid_module_name);
   ModuleId grid_module = module_manager.find_module(grid_module_name);
   VTR_ASSERT(true == module_manager.valid_module_id(grid_module));
 
@@ -377,9 +382,10 @@ static void print_verilog_physical_tile_netlist(
  ****************************************************************************/
 void print_verilog_grids(
   NetlistManager& netlist_manager, const ModuleManager& module_manager,
-  const DeviceContext& device_ctx, const VprDeviceAnnotation& device_annotation,
-  const std::string& subckt_dir, const std::string& subckt_dir_name,
-  const FabricVerilogOption& options, const bool& verbose) {
+  const ModuleNameMap& module_name_map, const DeviceContext& device_ctx,
+  const VprDeviceAnnotation& device_annotation, const std::string& subckt_dir,
+  const std::string& subckt_dir_name, const FabricVerilogOption& options,
+  const bool& verbose) {
   /* Create a vector to contain all the Verilog netlist names that have been
    * generated in this function */
   std::vector<std::string> netlist_names;
@@ -400,8 +406,9 @@ void print_verilog_grids(
       continue;
     }
     print_verilog_logical_tile_netlist(
-      netlist_manager, module_manager, device_annotation, subckt_dir,
-      subckt_dir_name, logical_tile.pb_graph_head, options, verbose);
+      netlist_manager, module_manager, module_name_map, device_annotation,
+      subckt_dir, subckt_dir_name, logical_tile.pb_graph_head, options,
+      verbose);
   }
   VTR_LOG("Writing logical tiles...");
   VTR_LOG("Done\n");
@@ -432,15 +439,15 @@ void print_verilog_grids(
         find_physical_io_tile_located_sides(device_ctx.grid, &physical_tile);
       for (const e_side& io_type_side : io_type_sides) {
         print_verilog_physical_tile_netlist(
-          netlist_manager, module_manager, subckt_dir, subckt_dir_name,
-          &physical_tile, io_type_side, options);
+          netlist_manager, module_manager, module_name_map, subckt_dir,
+          subckt_dir_name, &physical_tile, io_type_side, options);
       }
       continue;
     } else {
       /* For CLB and heterogenenous blocks */
-      print_verilog_physical_tile_netlist(netlist_manager, module_manager,
-                                          subckt_dir, subckt_dir_name,
-                                          &physical_tile, NUM_SIDES, options);
+      print_verilog_physical_tile_netlist(
+        netlist_manager, module_manager, module_name_map, subckt_dir,
+        subckt_dir_name, &physical_tile, NUM_SIDES, options);
     }
   }
   VTR_LOG("Building physical tiles...");

openfpga/src/fpga_verilog/verilog_grid.h

@@ -8,6 +8,7 @@
 
 #include "fabric_verilog_options.h"
 #include "module_manager.h"
+#include "module_name_map.h"
 #include "netlist_manager.h"
 #include "vpr_context.h"
 #include "vpr_device_annotation.h"
@@ -21,9 +22,10 @@ namespace openfpga {
 
 void print_verilog_grids(
   NetlistManager& netlist_manager, const ModuleManager& module_manager,
-  const DeviceContext& device_ctx, const VprDeviceAnnotation& device_annotation,
-  const std::string& subckt_dir, const std::string& subckt_dir_name,
-  const FabricVerilogOption& options, const bool& verbose);
+  const ModuleNameMap& module_name_map, const DeviceContext& device_ctx,
+  const VprDeviceAnnotation& device_annotation, const std::string& subckt_dir,
+  const std::string& subckt_dir_name, const FabricVerilogOption& options,
+  const bool& verbose);
 
 } /* end namespace openfpga */
 

openfpga/src/fpga_verilog/verilog_lut.cpp

@@ -29,6 +29,7 @@ namespace openfpga {
 void print_verilog_submodule_luts(const ModuleManager& module_manager,
                                   NetlistManager& netlist_manager,
                                   const CircuitLibrary& circuit_lib,
+                                  const ModuleNameMap& module_name_map,
                                   const std::string& submodule_dir,
                                   const std::string& submodule_dir_name,
                                   const FabricVerilogOption& options) {
@@ -55,8 +56,8 @@ void print_verilog_submodule_luts(const ModuleManager& module_manager,
       continue;
     }
     /* Find the module id */
-    ModuleId lut_module =
-      module_manager.find_module(circuit_lib.model_name(lut_model));
+    ModuleId lut_module = module_manager.find_module(
+      module_name_map.name(circuit_lib.model_name(lut_model)));
     VTR_ASSERT(true == module_manager.valid_module_id(lut_module));
     write_verilog_module_to_file(
       fp, module_manager, lut_module,

openfpga/src/fpga_verilog/verilog_lut.h

@@ -10,6 +10,7 @@
 #include "circuit_library.h"
 #include "fabric_verilog_options.h"
 #include "module_manager.h"
+#include "module_name_map.h"
 #include "netlist_manager.h"
 
 /********************************************************************
@@ -22,6 +23,7 @@ namespace openfpga {
 void print_verilog_submodule_luts(const ModuleManager& module_manager,
                                   NetlistManager& netlist_manager,
                                   const CircuitLibrary& circuit_lib,
+                                  const ModuleNameMap& module_name_map,
                                   const std::string& submodule_dir,
                                   const std::string& submodule_dir_name,
                                   const FabricVerilogOption& options);

openfpga/src/fpga_verilog/verilog_memory.cpp

@@ -42,7 +42,7 @@ namespace openfpga {
 static void print_verilog_mux_memory_module(
   const ModuleManager& module_manager, const CircuitLibrary& circuit_lib,
   std::fstream& fp, const CircuitModelId& mux_model, const MuxGraph& mux_graph,
-  const FabricVerilogOption& options) {
+  const ModuleNameMap& module_name_map, const FabricVerilogOption& options) {
   /* Multiplexers built with different technology is in different organization
    */
   switch (circuit_lib.design_tech_type(mux_model)) {
@@ -53,6 +53,7 @@ static void print_verilog_mux_memory_module(
         find_mux_num_datapath_inputs(circuit_lib, mux_model,
                                      mux_graph.num_inputs()),
         std::string(MEMORY_MODULE_POSTFIX));
+      module_name = module_name_map.name(module_name);
       ModuleId mem_module = module_manager.find_module(module_name);
       VTR_ASSERT(true == module_manager.valid_module_id(mem_module));
       /* Write the module content in Verilog format */
@@ -71,6 +72,9 @@ static void print_verilog_mux_memory_module(
         find_mux_num_datapath_inputs(circuit_lib, mux_model,
                                      mux_graph.num_inputs()),
         std::string(MEMORY_FEEDTHROUGH_MODULE_POSTFIX));
+      if (module_name_map.name_exist(feedthru_module_name)) {
+        feedthru_module_name = module_name_map.name(feedthru_module_name);
+      }
       ModuleId feedthru_mem_module =
         module_manager.find_module(feedthru_module_name);
       if (module_manager.valid_module_id(feedthru_mem_module)) {
@@ -118,13 +122,11 @@ static void print_verilog_mux_memory_module(
  * Take another example, the memory circuit can implement the scan-chain or
  * memory-bank organization for the memories.
  ********************************************************************/
-void print_verilog_submodule_memories(const ModuleManager& module_manager,
-                                      NetlistManager& netlist_manager,
-                                      const MuxLibrary& mux_lib,
-                                      const CircuitLibrary& circuit_lib,
-                                      const std::string& submodule_dir,
-                                      const std::string& submodule_dir_name,
-                                      const FabricVerilogOption& options) {
+void print_verilog_submodule_memories(
+  const ModuleManager& module_manager, NetlistManager& netlist_manager,
+  const MuxLibrary& mux_lib, const CircuitLibrary& circuit_lib,
+  const ModuleNameMap& module_name_map, const std::string& submodule_dir,
+  const std::string& submodule_dir_name, const FabricVerilogOption& options) {
   /* Plug in with the mux subckt */
   std::string verilog_fname(MEMORIES_VERILOG_FILE_NAME);
   std::string verilog_fpath(submodule_dir + verilog_fname);
@@ -155,7 +157,7 @@ void print_verilog_submodule_memories(const ModuleManager& module_manager,
     }
     /* Create a Verilog module for the memories used by the multiplexer */
     print_verilog_mux_memory_module(module_manager, circuit_lib, fp, mux_model,
-                                    mux_graph, options);
+                                    mux_graph, module_name_map, options);
   }
 
   /* Create the memory circuits for non-MUX circuit models.
@@ -198,6 +200,7 @@ void print_verilog_submodule_memories(const ModuleManager& module_manager,
     /* Create the module name for the memory block */
     std::string module_name = generate_memory_module_name(
       circuit_lib, model, sram_models[0], std::string(MEMORY_MODULE_POSTFIX));
+    module_name = module_name_map.name(module_name);
 
     ModuleId mem_module = module_manager.find_module(module_name);
     VTR_ASSERT(true == module_manager.valid_module_id(mem_module));
@@ -214,6 +217,9 @@ void print_verilog_submodule_memories(const ModuleManager& module_manager,
     std::string feedthru_module_name =
       generate_memory_module_name(circuit_lib, model, sram_models[0],
                                   std::string(MEMORY_MODULE_POSTFIX), true);
+    if (module_name_map.name_exist(feedthru_module_name)) {
+      feedthru_module_name = module_name_map.name(feedthru_module_name);
+    }
 
     ModuleId feedthru_mem_module =
       module_manager.find_module(feedthru_module_name);

openfpga/src/fpga_verilog/verilog_memory.h

@@ -9,6 +9,7 @@
 #include "circuit_library.h"
 #include "fabric_verilog_options.h"
 #include "module_manager.h"
+#include "module_name_map.h"
 #include "mux_graph.h"
 #include "mux_library.h"
 #include "netlist_manager.h"
@@ -20,13 +21,11 @@
 /* begin namespace openfpga */
 namespace openfpga {
 
-void print_verilog_submodule_memories(const ModuleManager& module_manager,
-                                      NetlistManager& netlist_manager,
-                                      const MuxLibrary& mux_lib,
-                                      const CircuitLibrary& circuit_lib,
-                                      const std::string& submodule_dir,
-                                      const std::string& submodule_dir_name,
-                                      const FabricVerilogOption& options);
+void print_verilog_submodule_memories(
+  const ModuleManager& module_manager, NetlistManager& netlist_manager,
+  const MuxLibrary& mux_lib, const CircuitLibrary& circuit_lib,
+  const ModuleNameMap& module_name_map, const std::string& submodule_dir,
+  const std::string& submodule_dir_name, const FabricVerilogOption& options);
 
 } /* end namespace openfpga */
 

openfpga/src/fpga_verilog/verilog_mock_fpga_wrapper.cpp

@@ -44,7 +44,8 @@ static void print_verilog_mock_fpga_wrapper_connect_ios(
   std::fstream& fp, const ModuleManager& module_manager,
   const ModuleId& top_module, const AtomContext& atom_ctx,
   const PlacementContext& place_ctx, const IoLocationMap& io_location_map,
-  const IoNameMap& io_name_map, const PinConstraints& pin_constraints,
+  const IoNameMap& io_name_map, const ModuleNameMap& module_name_map,
+  const PinConstraints& pin_constraints,
   const FabricGlobalPortInfo& global_ports,
   const VprNetlistAnnotation& netlist_annotation,
   const std::string& net_name_postfix,
@@ -189,7 +190,7 @@ static void print_verilog_mock_fpga_wrapper_connect_ios(
       }
       /* For global ports, use wires; otherwise, use registers*/
       if (true == port_is_fabric_global_reset_port(
-                    global_ports, module_manager,
+                    global_ports, module_manager, module_name_map,
                     pin_constraints.net_pin(block_name))) {
         continue;
       }
@@ -446,6 +447,7 @@ int print_verilog_mock_fpga_wrapper(
   const AtomContext& atom_ctx, const PlacementContext& place_ctx,
   const PinConstraints& pin_constraints, const BusGroup& bus_group,
   const IoLocationMap& io_location_map, const IoNameMap& io_name_map,
+  const ModuleNameMap& module_name_map,
   const VprNetlistAnnotation& netlist_annotation,
   const std::string& circuit_name, const std::string& verilog_fname,
   const VerilogTestbenchOption& options) {
@@ -472,7 +474,8 @@ int print_verilog_mock_fpga_wrapper(
   print_verilog_file_header(fp, title, options.time_stamp());
 
   /* Find the top_module */
-  ModuleId top_module = module_manager.find_module(options.dut_module());
+  ModuleId top_module =
+    module_manager.find_module(module_name_map.name(options.dut_module()));
   if (!module_manager.valid_module_id(top_module)) {
     VTR_LOG_ERROR(
       "Unable to find the DUT module '%s'. Please check if you create "
@@ -483,8 +486,11 @@ int print_verilog_mock_fpga_wrapper(
   /* Note that we always need the core module as it contains the original port
    * names before possible renaming at top-level module. If there is no core
    * module, it means that the current top module is the core module */
-  ModuleId core_module =
-    module_manager.find_module(generate_fpga_core_module_name());
+  std::string core_module_name = generate_fpga_core_module_name();
+  if (module_name_map.name_exist(core_module_name)) {
+    core_module_name = module_name_map.name(core_module_name);
+  }
+  ModuleId core_module = module_manager.find_module(core_module_name);
   if (!module_manager.valid_module_id(core_module)) {
     core_module = top_module;
   }
@@ -514,8 +520,8 @@ int print_verilog_mock_fpga_wrapper(
 
   /* Print local wires */
   print_verilog_testbench_shared_input_ports(
-    fp, module_manager, global_ports, pin_constraints, atom_ctx,
-    netlist_annotation, benchmark_clock_port_names, true,
+    fp, module_manager, module_name_map, global_ports, pin_constraints,
+    atom_ctx, netlist_annotation, benchmark_clock_port_names, true,
     std::string(APPINST_PORT_POSTFIX), false);
 
   print_verilog_testbench_shared_benchmark_output_ports(
@@ -541,8 +547,8 @@ int print_verilog_mock_fpga_wrapper(
   /* Connect I/Os to benchmark I/Os or constant driver */
   print_verilog_mock_fpga_wrapper_connect_ios(
     fp, module_manager, core_module, atom_ctx, place_ctx, io_location_map,
-    require_io_naming ? io_name_map : IoNameMap(), pin_constraints,
-    global_ports, netlist_annotation, std::string(),
+    require_io_naming ? io_name_map : IoNameMap(), module_name_map,
+    pin_constraints, global_ports, netlist_annotation, std::string(),
     std::string(APPINST_PORT_POSTFIX), std::string(APPINST_PORT_POSTFIX),
     benchmark_clock_port_names, (size_t)VERILOG_DEFAULT_SIGNAL_INIT_VALUE);
 

openfpga/src/fpga_verilog/verilog_mock_fpga_wrapper.h

@@ -15,6 +15,7 @@
 #include "io_location_map.h"
 #include "io_name_map.h"
 #include "module_manager.h"
+#include "module_name_map.h"
 #include "pin_constraints.h"
 #include "verilog_testbench_options.h"
 #include "vpr_context.h"
@@ -32,6 +33,7 @@ int print_verilog_mock_fpga_wrapper(
   const AtomContext& atom_ctx, const PlacementContext& place_ctx,
   const PinConstraints& pin_constraints, const BusGroup& bus_group,
   const IoLocationMap& io_location_map, const IoNameMap& io_name_map,
+  const ModuleNameMap& module_name_map,
   const VprNetlistAnnotation& netlist_annotation,
   const std::string& circuit_name, const std::string& verilog_fname,
   const VerilogTestbenchOption& options);

openfpga/src/fpga_verilog/verilog_mux.cpp

@@ -643,12 +643,13 @@ static void generate_verilog_rram_mux_branch_module(
 static void generate_verilog_mux_branch_module(
   ModuleManager& module_manager, const CircuitLibrary& circuit_lib,
   std::fstream& fp, const CircuitModelId& mux_model, const MuxGraph& mux_graph,
-  const bool& use_explicit_port_map,
+  const ModuleNameMap& module_name_map, const bool& use_explicit_port_map,
   const e_verilog_default_net_type& default_net_type,
   std::map<std::string, bool>& branch_mux_module_is_outputted) {
   std::string module_name = generate_mux_branch_subckt_name(
     circuit_lib, mux_model, mux_graph.num_inputs(), mux_graph.num_memory_bits(),
     VERILOG_MUX_BASIS_POSTFIX);
+  module_name = module_name_map.name(module_name);
 
   /* Skip outputting if the module has already been outputted */
   auto result = branch_mux_module_is_outputted.find(module_name);
@@ -1400,13 +1401,14 @@ static void generate_verilog_rram_mux_module(
 static void generate_verilog_mux_module(
   ModuleManager& module_manager, const CircuitLibrary& circuit_lib,
   std::fstream& fp, const CircuitModelId& mux_model, const MuxGraph& mux_graph,
-  const bool& use_explicit_port_map,
+  const ModuleNameMap& module_name_map, const bool& use_explicit_port_map,
   const e_verilog_default_net_type& default_net_type) {
   std::string module_name =
     generate_mux_subckt_name(circuit_lib, mux_model,
                              find_mux_num_datapath_inputs(
                                circuit_lib, mux_model, mux_graph.num_inputs()),
                              std::string(""));
+  module_name = module_name_map.name(module_name);
 
   /* Multiplexers built with different technology is in different organization
    */
@@ -1447,8 +1449,8 @@ static void generate_verilog_mux_module(
 static void print_verilog_submodule_mux_primitives(
   ModuleManager& module_manager, NetlistManager& netlist_manager,
   const MuxLibrary& mux_lib, const CircuitLibrary& circuit_lib,
-  const std::string& submodule_dir, const std::string& submodule_dir_name,
-  const FabricVerilogOption& options) {
+  const ModuleNameMap& module_name_map, const std::string& submodule_dir,
+  const std::string& submodule_dir_name, const FabricVerilogOption& options) {
   /* Output primitive cells for MUX modules */
   std::string verilog_fname(MUX_PRIMITIVES_VERILOG_FILE_NAME);
   std::string verilog_fpath(submodule_dir + verilog_fname);
@@ -1484,8 +1486,8 @@ static void print_verilog_submodule_mux_primitives(
     for (auto branch_mux_graph : branch_mux_graphs) {
       generate_verilog_mux_branch_module(
         module_manager, circuit_lib, fp, mux_circuit_model, branch_mux_graph,
-        options.explicit_port_mapping(), options.default_net_type(),
-        branch_mux_module_is_outputted);
+        module_name_map, options.explicit_port_mapping(),
+        options.default_net_type(), branch_mux_module_is_outputted);
     }
   }
 
@@ -1512,8 +1514,8 @@ static void print_verilog_submodule_mux_primitives(
 static void print_verilog_submodule_mux_top_modules(
   ModuleManager& module_manager, NetlistManager& netlist_manager,
   const MuxLibrary& mux_lib, const CircuitLibrary& circuit_lib,
-  const std::string& submodule_dir, const std::string& submodule_dir_name,
-  const FabricVerilogOption& options) {
+  const ModuleNameMap& module_name_map, const std::string& submodule_dir,
+  const std::string& submodule_dir_name, const FabricVerilogOption& options) {
   /* Output top-level MUX modules */
   std::string verilog_fname(MUXES_VERILOG_FILE_NAME);
   std::string verilog_fpath(submodule_dir + verilog_fname);
@@ -1536,9 +1538,10 @@ static void print_verilog_submodule_mux_top_modules(
     const MuxGraph& mux_graph = mux_lib.mux_graph(mux);
     CircuitModelId mux_circuit_model = mux_lib.mux_circuit_model(mux);
     /* Create MUX circuits */
-    generate_verilog_mux_module(
-      module_manager, circuit_lib, fp, mux_circuit_model, mux_graph,
-      options.explicit_port_mapping(), options.default_net_type());
+    generate_verilog_mux_module(module_manager, circuit_lib, fp,
+                                mux_circuit_model, mux_graph, module_name_map,
+                                options.explicit_port_mapping(),
+                                options.default_net_type());
   }
 
   /* Close the file stream */
@@ -1566,20 +1569,18 @@ static void print_verilog_submodule_mux_top_modules(
  * - A Verilog netlist contains all the top-level
  *   module for routing multiplexers
  **********************************************/
-void print_verilog_submodule_muxes(ModuleManager& module_manager,
-                                   NetlistManager& netlist_manager,
-                                   const MuxLibrary& mux_lib,
-                                   const CircuitLibrary& circuit_lib,
-                                   const std::string& submodule_dir,
-                                   const std::string& submodule_dir_name,
-                                   const FabricVerilogOption& options) {
-  print_verilog_submodule_mux_primitives(module_manager, netlist_manager,
-                                         mux_lib, circuit_lib, submodule_dir,
-                                         submodule_dir_name, options);
+void print_verilog_submodule_muxes(
+  ModuleManager& module_manager, NetlistManager& netlist_manager,
+  const MuxLibrary& mux_lib, const CircuitLibrary& circuit_lib,
+  const ModuleNameMap& module_name_map, const std::string& submodule_dir,
+  const std::string& submodule_dir_name, const FabricVerilogOption& options) {
+  print_verilog_submodule_mux_primitives(
+    module_manager, netlist_manager, mux_lib, circuit_lib, module_name_map,
+    submodule_dir, submodule_dir_name, options);
 
-  print_verilog_submodule_mux_top_modules(module_manager, netlist_manager,
-                                          mux_lib, circuit_lib, submodule_dir,
-                                          submodule_dir_name, options);
+  print_verilog_submodule_mux_top_modules(
+    module_manager, netlist_manager, mux_lib, circuit_lib, module_name_map,
+    submodule_dir, submodule_dir_name, options);
 }
 
 } /* end namespace openfpga */

openfpga/src/fpga_verilog/verilog_mux.h

@@ -10,6 +10,7 @@
 #include "circuit_library.h"
 #include "fabric_verilog_options.h"
 #include "module_manager.h"
+#include "module_name_map.h"
 #include "mux_graph.h"
 #include "mux_library.h"
 #include "netlist_manager.h"
@@ -21,13 +22,11 @@
 /* begin namespace openfpga */
 namespace openfpga {
 
-void print_verilog_submodule_muxes(ModuleManager& module_manager,
-                                   NetlistManager& netlist_manager,
-                                   const MuxLibrary& mux_lib,
-                                   const CircuitLibrary& circuit_lib,
-                                   const std::string& submodule_dir,
-                                   const std::string& submodule_dir_name,
-                                   const FabricVerilogOption& options);
+void print_verilog_submodule_muxes(
+  ModuleManager& module_manager, NetlistManager& netlist_manager,
+  const MuxLibrary& mux_lib, const CircuitLibrary& circuit_lib,
+  const ModuleNameMap& module_name_map, const std::string& submodule_dir,
+  const std::string& submodule_dir_name, const FabricVerilogOption& options);
 
 } /* end namespace openfpga */
 

openfpga/src/fpga_verilog/verilog_preconfig_top_module.cpp

@@ -540,7 +540,8 @@ int print_verilog_preconfig_top_module(
   const FabricGlobalPortInfo &global_ports, const AtomContext &atom_ctx,
   const PlacementContext &place_ctx, const PinConstraints &pin_constraints,
   const BusGroup &bus_group, const IoLocationMap &io_location_map,
-  const IoNameMap &io_name_map, const VprNetlistAnnotation &netlist_annotation,
+  const IoNameMap &io_name_map, const ModuleNameMap &module_name_map,
+  const VprNetlistAnnotation &netlist_annotation,
   const std::string &circuit_name, const std::string &verilog_fname,
   const VerilogTestbenchOption &options) {
   std::string timer_message =
@@ -573,7 +574,8 @@ int print_verilog_preconfig_top_module(
                                            netlist_annotation, bus_group);
 
   /* Spot the dut module */
-  ModuleId top_module = module_manager.find_module(options.dut_module());
+  ModuleId top_module =
+    module_manager.find_module(module_name_map.name(options.dut_module()));
   if (!module_manager.valid_module_id(top_module)) {
     VTR_LOG_ERROR(
       "Unable to find the DUT module '%s'. Please check if you create "
@@ -584,8 +586,11 @@ int print_verilog_preconfig_top_module(
   /* Note that we always need the core module as it contains the original port
    * names before possible renaming at top-level module. If there is no core
    * module, it means that the current top module is the core module */
-  ModuleId core_module =
-    module_manager.find_module(generate_fpga_core_module_name());
+  std::string core_module_name = generate_fpga_core_module_name();
+  if (module_name_map.name_exist(core_module_name)) {
+    core_module_name = module_name_map.name(core_module_name);
+  }
+  ModuleId core_module = module_manager.find_module(core_module_name);
   if (!module_manager.valid_module_id(core_module)) {
     core_module = top_module;
   }
@@ -629,10 +634,10 @@ int print_verilog_preconfig_top_module(
   /* If we do have the core module, and the dut is specified as core module, the
    * hierarchy path when adding should be the instance name of the core module
    */
-  std::string inst_name = generate_fpga_top_module_name();
+  std::string inst_name = module_name_map.name(generate_fpga_top_module_name());
   if (options.dut_module() == generate_fpga_core_module_name()) {
-    ModuleId parent_module =
-      module_manager.find_module(generate_fpga_top_module_name());
+    ModuleId parent_module = module_manager.find_module(
+      module_name_map.name(generate_fpga_top_module_name()));
     inst_name = module_manager.instance_name(parent_module, core_module, 0);
   }
 

openfpga/src/fpga_verilog/verilog_preconfig_top_module.h

@@ -15,6 +15,7 @@
 #include "io_location_map.h"
 #include "io_name_map.h"
 #include "module_manager.h"
+#include "module_name_map.h"
 #include "pin_constraints.h"
 #include "verilog_testbench_options.h"
 #include "vpr_context.h"
@@ -34,7 +35,8 @@ int print_verilog_preconfig_top_module(
   const FabricGlobalPortInfo& global_ports, const AtomContext& atom_ctx,
   const PlacementContext& place_ctx, const PinConstraints& pin_constraints,
   const BusGroup& bus_group, const IoLocationMap& io_location_map,
-  const IoNameMap& io_name_map, const VprNetlistAnnotation& netlist_annotation,
+  const IoNameMap& io_name_map, const ModuleNameMap& module_name_map,
+  const VprNetlistAnnotation& netlist_annotation,
   const std::string& circuit_name, const std::string& verilog_fname,
   const VerilogTestbenchOption& options);
 

openfpga/src/fpga_verilog/verilog_routing.cpp

@@ -77,9 +77,9 @@ namespace openfpga {
  ********************************************************************/
 static void print_verilog_routing_connection_box_unique_module(
   NetlistManager& netlist_manager, const ModuleManager& module_manager,
-  const std::string& subckt_dir, const std::string& subckt_dir_name,
-  const RRGSB& rr_gsb, const t_rr_type& cb_type,
-  const FabricVerilogOption& options) {
+  const ModuleNameMap& module_name_map, const std::string& subckt_dir,
+  const std::string& subckt_dir_name, const RRGSB& rr_gsb,
+  const t_rr_type& cb_type, const FabricVerilogOption& options) {
   /* Create the netlist */
   vtr::Point<size_t> gsb_coordinate(rr_gsb.get_cb_x(cb_type),
                                     rr_gsb.get_cb_y(cb_type));
@@ -102,8 +102,9 @@ static void print_verilog_routing_connection_box_unique_module(
 
   /* Create a Verilog Module based on the circuit model, and add to module
    * manager */
-  ModuleId cb_module = module_manager.find_module(
+  std::string cb_module_name = module_name_map.name(
     generate_connection_block_module_name(cb_type, gsb_coordinate));
+  ModuleId cb_module = module_manager.find_module(cb_module_name);
   VTR_ASSERT(true == module_manager.valid_module_id(cb_module));
 
   /* Write the verilog module */
@@ -191,8 +192,9 @@ static void print_verilog_routing_connection_box_unique_module(
  ********************************************************************/
 static void print_verilog_routing_switch_box_unique_module(
   NetlistManager& netlist_manager, const ModuleManager& module_manager,
-  const std::string& subckt_dir, const std::string& subckt_dir_name,
-  const RRGSB& rr_gsb, const FabricVerilogOption& options) {
+  const ModuleNameMap& module_name_map, const std::string& subckt_dir,
+  const std::string& subckt_dir_name, const RRGSB& rr_gsb,
+  const FabricVerilogOption& options) {
   /* Create the netlist */
   vtr::Point<size_t> gsb_coordinate(rr_gsb.get_sb_x(), rr_gsb.get_sb_y());
   std::string verilog_fname(generate_routing_block_netlist_name(
@@ -215,8 +217,9 @@ static void print_verilog_routing_switch_box_unique_module(
 
   /* Create a Verilog Module based on the circuit model, and add to module
    * manager */
-  ModuleId sb_module = module_manager.find_module(
-    generate_switch_block_module_name(gsb_coordinate));
+  std::string sb_module_name =
+    module_name_map.name(generate_switch_block_module_name(gsb_coordinate));
+  ModuleId sb_module = module_manager.find_module(sb_module_name);
   VTR_ASSERT(true == module_manager.valid_module_id(sb_module));
 
   /* Write the verilog module */
@@ -245,9 +248,9 @@ static void print_verilog_routing_switch_box_unique_module(
  *******************************************************************/
 static void print_verilog_flatten_connection_block_modules(
   NetlistManager& netlist_manager, const ModuleManager& module_manager,
-  const DeviceRRGSB& device_rr_gsb, const std::string& subckt_dir,
-  const std::string& subckt_dir_name, const t_rr_type& cb_type,
-  const FabricVerilogOption& options) {
+  const ModuleNameMap& module_name_map, const DeviceRRGSB& device_rr_gsb,
+  const std::string& subckt_dir, const std::string& subckt_dir_name,
+  const t_rr_type& cb_type, const FabricVerilogOption& options) {
   /* Build unique X-direction connection block modules */
   vtr::Point<size_t> cb_range = device_rr_gsb.get_gsb_range();
 
@@ -262,8 +265,8 @@ static void print_verilog_flatten_connection_block_modules(
         continue;
       }
       print_verilog_routing_connection_box_unique_module(
-        netlist_manager, module_manager, subckt_dir, subckt_dir_name, rr_gsb,
-        cb_type, options);
+        netlist_manager, module_manager, module_name_map, subckt_dir,
+        subckt_dir_name, rr_gsb, cb_type, options);
     }
   }
 }
@@ -277,13 +280,11 @@ static void print_verilog_flatten_connection_block_modules(
  * 1. Connection blocks
  * 2. Switch blocks
  *******************************************************************/
-void print_verilog_flatten_routing_modules(NetlistManager& netlist_manager,
-                                           const ModuleManager& module_manager,
-                                           const DeviceRRGSB& device_rr_gsb,
-                                           const RRGraphView& rr_graph,
-                                           const std::string& subckt_dir,
-                                           const std::string& subckt_dir_name,
-                                           const FabricVerilogOption& options) {
+void print_verilog_flatten_routing_modules(
+  NetlistManager& netlist_manager, const ModuleManager& module_manager,
+  const ModuleNameMap& module_name_map, const DeviceRRGSB& device_rr_gsb,
+  const RRGraphView& rr_graph, const std::string& subckt_dir,
+  const std::string& subckt_dir_name, const FabricVerilogOption& options) {
   /* Create a vector to contain all the Verilog netlist names that have been
    * generated in this function */
   std::vector<std::string> netlist_names;
@@ -298,18 +299,18 @@ void print_verilog_flatten_routing_modules(NetlistManager& netlist_manager,
         continue;
       }
       print_verilog_routing_switch_box_unique_module(
-        netlist_manager, module_manager, subckt_dir, subckt_dir_name, rr_gsb,
-        options);
+        netlist_manager, module_manager, module_name_map, subckt_dir,
+        subckt_dir_name, rr_gsb, options);
     }
   }
 
   print_verilog_flatten_connection_block_modules(
-    netlist_manager, module_manager, device_rr_gsb, subckt_dir, subckt_dir_name,
-    CHANX, options);
+    netlist_manager, module_manager, module_name_map, device_rr_gsb, subckt_dir,
+    subckt_dir_name, CHANX, options);
 
   print_verilog_flatten_connection_block_modules(
-    netlist_manager, module_manager, device_rr_gsb, subckt_dir, subckt_dir_name,
-    CHANY, options);
+    netlist_manager, module_manager, module_name_map, device_rr_gsb, subckt_dir,
+    subckt_dir_name, CHANY, options);
 }
 
 /********************************************************************
@@ -324,6 +325,7 @@ void print_verilog_flatten_routing_modules(NetlistManager& netlist_manager,
  *******************************************************************/
 void print_verilog_unique_routing_modules(NetlistManager& netlist_manager,
                                           const ModuleManager& module_manager,
+                                          const ModuleNameMap& module_name_map,
                                           const DeviceRRGSB& device_rr_gsb,
                                           const std::string& subckt_dir,
                                           const std::string& subckt_dir_name,
@@ -336,8 +338,8 @@ void print_verilog_unique_routing_modules(NetlistManager& netlist_manager,
   for (size_t isb = 0; isb < device_rr_gsb.get_num_sb_unique_module(); ++isb) {
     const RRGSB& unique_mirror = device_rr_gsb.get_sb_unique_module(isb);
     print_verilog_routing_switch_box_unique_module(
-      netlist_manager, module_manager, subckt_dir, subckt_dir_name,
-      unique_mirror, options);
+      netlist_manager, module_manager, module_name_map, subckt_dir,
+      subckt_dir_name, unique_mirror, options);
   }
 
   /* Build unique X-direction connection block modules */
@@ -346,8 +348,8 @@ void print_verilog_unique_routing_modules(NetlistManager& netlist_manager,
     const RRGSB& unique_mirror = device_rr_gsb.get_cb_unique_module(CHANX, icb);
 
     print_verilog_routing_connection_box_unique_module(
-      netlist_manager, module_manager, subckt_dir, subckt_dir_name,
-      unique_mirror, CHANX, options);
+      netlist_manager, module_manager, module_name_map, subckt_dir,
+      subckt_dir_name, unique_mirror, CHANX, options);
   }
 
   /* Build unique X-direction connection block modules */
@@ -356,8 +358,8 @@ void print_verilog_unique_routing_modules(NetlistManager& netlist_manager,
     const RRGSB& unique_mirror = device_rr_gsb.get_cb_unique_module(CHANY, icb);
 
     print_verilog_routing_connection_box_unique_module(
-      netlist_manager, module_manager, subckt_dir, subckt_dir_name,
-      unique_mirror, CHANY, options);
+      netlist_manager, module_manager, module_name_map, subckt_dir,
+      subckt_dir_name, unique_mirror, CHANY, options);
   }
 
   VTR_LOG("\n");

openfpga/src/fpga_verilog/verilog_routing.h

@@ -8,6 +8,7 @@
 #include "device_rr_gsb.h"
 #include "fabric_verilog_options.h"
 #include "module_manager.h"
+#include "module_name_map.h"
 #include "mux_library.h"
 #include "netlist_manager.h"
 #include "rr_graph_view.h"
@@ -19,16 +20,15 @@
 /* begin namespace openfpga */
 namespace openfpga {
 
-void print_verilog_flatten_routing_modules(NetlistManager& netlist_manager,
-                                           const ModuleManager& module_manager,
-                                           const DeviceRRGSB& device_rr_gsb,
-                                           const RRGraphView& rr_graph,
-                                           const std::string& subckt_dir,
-                                           const std::string& subckt_dir_name,
-                                           const FabricVerilogOption& options);
+void print_verilog_flatten_routing_modules(
+  NetlistManager& netlist_manager, const ModuleManager& module_manager,
+  const ModuleNameMap& module_name_map, const DeviceRRGSB& device_rr_gsb,
+  const RRGraphView& rr_graph, const std::string& subckt_dir,
+  const std::string& subckt_dir_name, const FabricVerilogOption& options);
 
 void print_verilog_unique_routing_modules(NetlistManager& netlist_manager,
                                           const ModuleManager& module_manager,
+                                          const ModuleNameMap& module_name_map,
                                           const DeviceRRGSB& device_rr_gsb,
                                           const std::string& subckt_dir,
                                           const std::string& subckt_dir_name,

openfpga/src/fpga_verilog/verilog_submodule.cpp

@@ -36,16 +36,19 @@ void print_verilog_submodule(
   ModuleManager& module_manager, NetlistManager& netlist_manager,
   const MemoryBankShiftRegisterBanks& blwl_sr_banks, const MuxLibrary& mux_lib,
   const DecoderLibrary& decoder_lib, const CircuitLibrary& circuit_lib,
-  const std::string& submodule_dir, const std::string& submodule_dir_name,
+  const ModuleNameMap& module_name_map, const std::string& submodule_dir,
+  const std::string& submodule_dir_name,
   const FabricVerilogOption& fpga_verilog_opts) {
   print_verilog_submodule_essentials(
     const_cast<const ModuleManager&>(module_manager), netlist_manager,
-    submodule_dir, submodule_dir_name, circuit_lib, fpga_verilog_opts);
+    submodule_dir, submodule_dir_name, circuit_lib, module_name_map,
+    fpga_verilog_opts);
 
   /* Decoders for architecture */
   print_verilog_submodule_arch_decoders(
     const_cast<const ModuleManager&>(module_manager), netlist_manager,
-    decoder_lib, submodule_dir, submodule_dir_name, fpga_verilog_opts);
+    decoder_lib, module_name_map, submodule_dir, submodule_dir_name,
+    fpga_verilog_opts);
 
   /* Routing multiplexers */
   /* NOTE: local decoders generation must go before the MUX generation!!!
@@ -54,25 +57,29 @@ void print_verilog_submodule(
    */
   print_verilog_submodule_mux_local_decoders(
     const_cast<const ModuleManager&>(module_manager), netlist_manager, mux_lib,
-    circuit_lib, submodule_dir, submodule_dir_name, fpga_verilog_opts);
+    circuit_lib, module_name_map, submodule_dir, submodule_dir_name,
+    fpga_verilog_opts);
   print_verilog_submodule_muxes(module_manager, netlist_manager, mux_lib,
-                                circuit_lib, submodule_dir, submodule_dir_name,
-                                fpga_verilog_opts);
+                                circuit_lib, module_name_map, submodule_dir,
+                                submodule_dir_name, fpga_verilog_opts);
 
   /* LUTes */
   print_verilog_submodule_luts(const_cast<const ModuleManager&>(module_manager),
-                               netlist_manager, circuit_lib, submodule_dir,
-                               submodule_dir_name, fpga_verilog_opts);
+                               netlist_manager, circuit_lib, module_name_map,
+                               submodule_dir, submodule_dir_name,
+                               fpga_verilog_opts);
 
   /* Hard wires */
   print_verilog_submodule_wires(
     const_cast<const ModuleManager&>(module_manager), netlist_manager,
-    circuit_lib, submodule_dir, submodule_dir_name, fpga_verilog_opts);
+    circuit_lib, module_name_map, submodule_dir, submodule_dir_name,
+    fpga_verilog_opts);
 
   /* Memories */
   print_verilog_submodule_memories(
     const_cast<const ModuleManager&>(module_manager), netlist_manager, mux_lib,
-    circuit_lib, submodule_dir, submodule_dir_name, fpga_verilog_opts);
+    circuit_lib, module_name_map, submodule_dir, submodule_dir_name,
+    fpga_verilog_opts);
 
   /* Shift register banks */
   print_verilog_submodule_shift_register_banks(

openfpga/src/fpga_verilog/verilog_submodule.h

@@ -8,6 +8,7 @@
 #include "fabric_verilog_options.h"
 #include "memory_bank_shift_register_banks.h"
 #include "module_manager.h"
+#include "module_name_map.h"
 #include "mux_library.h"
 #include "netlist_manager.h"
 
@@ -22,7 +23,8 @@ void print_verilog_submodule(
   ModuleManager& module_manager, NetlistManager& netlist_manager,
   const MemoryBankShiftRegisterBanks& blwl_sr_banks, const MuxLibrary& mux_lib,
   const DecoderLibrary& decoder_lib, const CircuitLibrary& circuit_lib,
-  const std::string& submodule_dir, const std::string& submodule_dir_name,
+  const ModuleNameMap& module_name_map, const std::string& submodule_dir,
+  const std::string& submodule_dir_name,
   const FabricVerilogOption& fpga_verilog_opts);
 
 } /* end namespace openfpga */

openfpga/src/fpga_verilog/verilog_testbench_utils.cpp

@@ -818,7 +818,8 @@ void print_verilog_testbench_clock_stimuli(
 void print_verilog_testbench_random_stimuli(
   std::fstream& fp, const AtomContext& atom_ctx,
   const VprNetlistAnnotation& netlist_annotation,
-  const ModuleManager& module_manager, const FabricGlobalPortInfo& global_ports,
+  const ModuleManager& module_manager, const ModuleNameMap& module_name_map,
+  const FabricGlobalPortInfo& global_ports,
   const PinConstraints& pin_constraints,
   const std::vector<std::string>& clock_port_names,
   const std::string& input_port_postfix,
@@ -858,9 +859,9 @@ void print_verilog_testbench_random_stimuli(
     /* Bypass any constained net that are mapped to a global port of the FPGA
      * fabric because their stimulus cannot be random
      */
-    if (true ==
-        port_is_fabric_global_reset_port(global_ports, module_manager,
-                                         pin_constraints.net_pin(block_name))) {
+    if (true == port_is_fabric_global_reset_port(
+                  global_ports, module_manager, module_name_map,
+                  pin_constraints.net_pin(block_name))) {
       continue;
     }
 
@@ -942,9 +943,9 @@ void print_verilog_testbench_random_stimuli(
     /* Bypass any constained net that are mapped to a global port of the FPGA
      * fabric because their stimulus cannot be random
      */
-    if (true ==
-        port_is_fabric_global_reset_port(global_ports, module_manager,
-                                         pin_constraints.net_pin(block_name))) {
+    if (true == port_is_fabric_global_reset_port(
+                  global_ports, module_manager, module_name_map,
+                  pin_constraints.net_pin(block_name))) {
       continue;
     }
 
@@ -970,6 +971,7 @@ void print_verilog_testbench_random_stimuli(
  *******************************************************************/
 void print_verilog_testbench_shared_input_ports(
   std::fstream& fp, const ModuleManager& module_manager,
+  const ModuleNameMap& module_name_map,
   const FabricGlobalPortInfo& global_ports,
   const PinConstraints& pin_constraints, const AtomContext& atom_ctx,
   const VprNetlistAnnotation& netlist_annotation,
@@ -1006,9 +1008,9 @@ void print_verilog_testbench_shared_input_ports(
     /* Each logical block assumes a single-width port */
     BasicPort input_port(block_name + shared_input_port_postfix, 1);
     /* For global ports, use wires; otherwise, use registers*/
-    if (false ==
-        port_is_fabric_global_reset_port(global_ports, module_manager,
-                                         pin_constraints.net_pin(block_name))) {
+    if (false == port_is_fabric_global_reset_port(
+                   global_ports, module_manager, module_name_map,
+                   pin_constraints.net_pin(block_name))) {
       if (use_reg_port) {
         fp << "\t" << generate_verilog_port(VERILOG_PORT_REG, input_port) << ";"
            << std::endl;
@@ -1159,6 +1161,7 @@ void print_verilog_testbench_shared_check_flags(
  *******************************************************************/
 void print_verilog_testbench_shared_ports(
   std::fstream& fp, const ModuleManager& module_manager,
+  const ModuleNameMap& module_name_map,
   const FabricGlobalPortInfo& global_ports,
   const PinConstraints& pin_constraints, const AtomContext& atom_ctx,
   const VprNetlistAnnotation& netlist_annotation,
@@ -1168,9 +1171,9 @@ void print_verilog_testbench_shared_ports(
   const std::string& fpga_output_port_postfix,
   const std::string& check_flag_port_postfix, const bool& no_self_checking) {
   print_verilog_testbench_shared_input_ports(
-    fp, module_manager, global_ports, pin_constraints, atom_ctx,
-    netlist_annotation, clock_port_names, false, shared_input_port_postfix,
-    true);
+    fp, module_manager, module_name_map, global_ports, pin_constraints,
+    atom_ctx, netlist_annotation, clock_port_names, false,
+    shared_input_port_postfix, true);
 
   print_verilog_testbench_shared_fpga_output_ports(
     fp, atom_ctx, netlist_annotation, fpga_output_port_postfix);

openfpga/src/fpga_verilog/verilog_testbench_utils.h

@@ -14,6 +14,7 @@
 #include "io_location_map.h"
 #include "io_name_map.h"
 #include "module_manager.h"
+#include "module_name_map.h"
 #include "pin_constraints.h"
 #include "simulation_setting.h"
 #include "vpr_context.h"
@@ -84,7 +85,8 @@ void print_verilog_testbench_clock_stimuli(
 void print_verilog_testbench_random_stimuli(
   std::fstream& fp, const AtomContext& atom_ctx,
   const VprNetlistAnnotation& netlist_annotation,
-  const ModuleManager& module_manager, const FabricGlobalPortInfo& global_ports,
+  const ModuleManager& module_manager, const ModuleNameMap& module_name_map,
+  const FabricGlobalPortInfo& global_ports,
   const PinConstraints& pin_constraints,
   const std::vector<std::string>& clock_port_names,
   const std::string& input_port_postfix,
@@ -93,6 +95,7 @@ void print_verilog_testbench_random_stimuli(
 
 void print_verilog_testbench_shared_input_ports(
   std::fstream& fp, const ModuleManager& module_manager,
+  const ModuleNameMap& module_name_map,
   const FabricGlobalPortInfo& global_ports,
   const PinConstraints& pin_constraints, const AtomContext& atom_ctx,
   const VprNetlistAnnotation& netlist_annotation,
@@ -117,6 +120,7 @@ void print_verilog_testbench_shared_check_flags(
 
 void print_verilog_testbench_shared_ports(
   std::fstream& fp, const ModuleManager& module_manager,
+  const ModuleNameMap& module_name_map,
   const FabricGlobalPortInfo& global_ports,
   const PinConstraints& pin_constraints, const AtomContext& atom_ctx,
   const VprNetlistAnnotation& netlist_annotation,

openfpga/src/fpga_verilog/verilog_tile.cpp

@@ -26,13 +26,14 @@ namespace openfpga {
  *******************************************************************/
 static int print_verilog_tile_module_netlist(
   NetlistManager& netlist_manager, const ModuleManager& module_manager,
-  const std::string& verilog_dir, const FabricTile& fabric_tile,
-  const FabricTileId& fabric_tile_id, const std::string& subckt_dir_name,
-  const FabricVerilogOption& options) {
+  const ModuleNameMap& module_name_map, const std::string& verilog_dir,
+  const FabricTile& fabric_tile, const FabricTileId& fabric_tile_id,
+  const std::string& subckt_dir_name, const FabricVerilogOption& options) {
   /* Create a module as the top-level fabric, and add it to the module manager
    */
   vtr::Point<size_t> tile_coord = fabric_tile.tile_coordinate(fabric_tile_id);
-  std::string tile_module_name = generate_tile_module_name(tile_coord);
+  std::string tile_module_name =
+    module_name_map.name(generate_tile_module_name(tile_coord));
   ModuleId tile_module = module_manager.find_module(tile_module_name);
   if (!module_manager.valid_module_id(tile_module)) {
     return CMD_EXEC_FATAL_ERROR;
@@ -89,6 +90,7 @@ static int print_verilog_tile_module_netlist(
  *******************************************************************/
 int print_verilog_tiles(NetlistManager& netlist_manager,
                         const ModuleManager& module_manager,
+                        const ModuleNameMap& module_name_map,
                         const std::string& verilog_dir,
                         const FabricTile& fabric_tile,
                         const std::string& subckt_dir_name,
@@ -100,8 +102,8 @@ int print_verilog_tiles(NetlistManager& netlist_manager,
   /* Build a module for each unique tile  */
   for (FabricTileId fabric_tile_id : fabric_tile.unique_tiles()) {
     status_code = print_verilog_tile_module_netlist(
-      netlist_manager, module_manager, verilog_dir, fabric_tile, fabric_tile_id,
-      subckt_dir_name, options);
+      netlist_manager, module_manager, module_name_map, verilog_dir,
+      fabric_tile, fabric_tile_id, subckt_dir_name, options);
     if (status_code != CMD_EXEC_SUCCESS) {
       return CMD_EXEC_FATAL_ERROR;
     }

openfpga/src/fpga_verilog/verilog_tile.h

@@ -9,6 +9,7 @@
 #include "fabric_tile.h"
 #include "fabric_verilog_options.h"
 #include "module_manager.h"
+#include "module_name_map.h"
 #include "netlist_manager.h"
 
 /********************************************************************
@@ -20,6 +21,7 @@ namespace openfpga {
 
 int print_verilog_tiles(NetlistManager& netlist_manager,
                         const ModuleManager& module_manager,
+                        const ModuleNameMap& module_name_map,
                         const std::string& verilog_dir,
                         const FabricTile& fabric_tile,
                         const std::string& subckt_dir_name,

openfpga/src/fpga_verilog/verilog_top_module.cpp

@@ -26,11 +26,15 @@ namespace openfpga {
  *******************************************************************/
 void print_verilog_core_module(NetlistManager& netlist_manager,
                                const ModuleManager& module_manager,
+                               const ModuleNameMap& module_name_map,
                                const std::string& verilog_dir,
                                const FabricVerilogOption& options) {
   /* Create a module as the top-level fabric, and add it to the module manager
    */
   std::string core_module_name = generate_fpga_core_module_name();
+  if (module_name_map.name_exist(core_module_name)) {
+    core_module_name = module_name_map.name(core_module_name);
+  }
   ModuleId core_module = module_manager.find_module(core_module_name);
   /* It could happen that the module does not exist, just return with no errors
    */
@@ -94,11 +98,13 @@ void print_verilog_core_module(NetlistManager& netlist_manager,
  *******************************************************************/
 void print_verilog_top_module(NetlistManager& netlist_manager,
                               const ModuleManager& module_manager,
+                              const ModuleNameMap& module_name_map,
                               const std::string& verilog_dir,
                               const FabricVerilogOption& options) {
   /* Create a module as the top-level fabric, and add it to the module manager
    */
   std::string top_module_name = generate_fpga_top_module_name();
+  top_module_name = module_name_map.name(top_module_name);
   ModuleId top_module = module_manager.find_module(top_module_name);
   VTR_ASSERT(true == module_manager.valid_module_id(top_module));
 

openfpga/src/fpga_verilog/verilog_top_module.h

@@ -8,6 +8,7 @@
 
 #include "fabric_verilog_options.h"
 #include "module_manager.h"
+#include "module_name_map.h"
 #include "netlist_manager.h"
 
 /********************************************************************
@@ -19,11 +20,13 @@ namespace openfpga {
 
 void print_verilog_core_module(NetlistManager& netlist_manager,
                                const ModuleManager& module_manager,
+                               const ModuleNameMap& module_name_map,
                                const std::string& verilog_dir,
                                const FabricVerilogOption& options);
 
 void print_verilog_top_module(NetlistManager& netlist_manager,
                               const ModuleManager& module_manager,
+                              const ModuleNameMap& module_name_map,
                               const std::string& verilog_dir,
                               const FabricVerilogOption& options);
 

openfpga/src/fpga_verilog/verilog_top_testbench.cpp

@@ -801,8 +801,8 @@ static void print_verilog_top_testbench_benchmark_clock_ports(
  *******************************************************************/
 static void print_verilog_top_testbench_ports(
   std::fstream& fp, const ModuleManager& module_manager,
-  const ModuleId& top_module, const AtomContext& atom_ctx,
-  const VprNetlistAnnotation& netlist_annotation,
+  const ModuleNameMap& module_name_map, const ModuleId& top_module,
+  const AtomContext& atom_ctx, const VprNetlistAnnotation& netlist_annotation,
   const std::vector<std::string>& clock_port_names,
   const FabricGlobalPortInfo& global_ports,
   const PinConstraints& pin_constraints,
@@ -950,8 +950,8 @@ static void print_verilog_top_testbench_ports(
 
   std::vector<std::string> global_port_names;
   print_verilog_testbench_shared_ports(
-    fp, module_manager, global_ports, pin_constraints, atom_ctx,
-    netlist_annotation, clock_port_names,
+    fp, module_manager, module_name_map, global_ports, pin_constraints,
+    atom_ctx, netlist_annotation, clock_port_names,
     std::string(TOP_TESTBENCH_SHARED_INPUT_POSTFIX),
     std::string(TOP_TESTBENCH_REFERENCE_OUTPUT_POSTFIX),
     std::string(TOP_TESTBENCH_FPGA_OUTPUT_POSTFIX),
@@ -2336,7 +2336,8 @@ static void print_verilog_full_testbench_bitstream(
 static void print_verilog_top_testbench_reset_stimuli(
   std::fstream& fp, const AtomContext& atom_ctx,
   const VprNetlistAnnotation& netlist_annotation,
-  const ModuleManager& module_manager, const FabricGlobalPortInfo& global_ports,
+  const ModuleManager& module_manager, const ModuleNameMap& module_name_map,
+  const FabricGlobalPortInfo& global_ports,
   const PinConstraints& pin_constraints, const std::string& port_name_postfix,
   const std::vector<std::string>& clock_port_names) {
   valid_file_stream(fp);
@@ -2366,15 +2367,15 @@ static void print_verilog_top_testbench_reset_stimuli(
     /* Bypass any constained net that are mapped to a global port of the FPGA
      * fabric because their stimulus cannot be random
      */
-    if (false ==
-        port_is_fabric_global_reset_port(global_ports, module_manager,
-                                         pin_constraints.net_pin(block_name))) {
+    if (false == port_is_fabric_global_reset_port(
+                   global_ports, module_manager, module_name_map,
+                   pin_constraints.net_pin(block_name))) {
       continue;
     }
 
-    size_t initial_value =
-      global_ports.global_port_default_value(find_fabric_global_port(
-        global_ports, module_manager, pin_constraints.net_pin(block_name)));
+    size_t initial_value = global_ports.global_port_default_value(
+      find_fabric_global_port(global_ports, module_manager, module_name_map,
+                              pin_constraints.net_pin(block_name)));
 
     /* Connect stimuli to greset with an optional inversion, depending on the
      * default value */
@@ -2447,6 +2448,7 @@ int print_verilog_full_testbench(
   const PlacementContext& place_ctx, const PinConstraints& pin_constraints,
   const BusGroup& bus_group, const std::string& bitstream_file,
   const IoLocationMap& io_location_map, const IoNameMap& io_name_map,
+  const ModuleNameMap& module_name_map,
   const VprNetlistAnnotation& netlist_annotation,
   const std::string& circuit_name, const std::string& verilog_fname,
   const SimulationSetting& simulation_parameters,
@@ -2477,7 +2479,8 @@ int print_verilog_full_testbench(
   print_verilog_file_header(fp, title, options.time_stamp());
 
   /* Spot the dut module */
-  ModuleId top_module = module_manager.find_module(options.dut_module());
+  ModuleId top_module =
+    module_manager.find_module(module_name_map.name(options.dut_module()));
   if (!module_manager.valid_module_id(top_module)) {
     VTR_LOG_ERROR(
       "Unable to find the DUT module '%s'. Please check if you create "
@@ -2488,8 +2491,11 @@ int print_verilog_full_testbench(
   /* Note that we always need the core module as it contains the original port
    * names before possible renaming at top-level module. If there is no core
    * module, it means that the current top module is the core module */
-  ModuleId core_module =
-    module_manager.find_module(generate_fpga_core_module_name());
+  std::string core_module_name = generate_fpga_core_module_name();
+  if (module_name_map.name_exist(core_module_name)) {
+    core_module_name = module_name_map.name(core_module_name);
+  }
+  ModuleId core_module = module_manager.find_module(core_module_name);
   if (!module_manager.valid_module_id(core_module)) {
     core_module = top_module;
   }
@@ -2516,9 +2522,9 @@ int print_verilog_full_testbench(
 
   /* Start of testbench */
   print_verilog_top_testbench_ports(
-    fp, module_manager, core_module, atom_ctx, netlist_annotation,
-    clock_port_names, global_ports, pin_constraints, simulation_parameters,
-    config_protocol, circuit_name, options);
+    fp, module_manager, module_name_map, core_module, atom_ctx,
+    netlist_annotation, clock_port_names, global_ports, pin_constraints,
+    simulation_parameters, config_protocol, circuit_name, options);
 
   /* Find the clock period */
   float prog_clock_period =
@@ -2624,12 +2630,12 @@ int print_verilog_full_testbench(
 
   /* Add stimuli for reset, set, clock and iopad signals */
   print_verilog_top_testbench_reset_stimuli(
-    fp, atom_ctx, netlist_annotation, module_manager, global_ports,
-    pin_constraints, std::string(TOP_TESTBENCH_SHARED_INPUT_POSTFIX),
-    clock_port_names);
+    fp, atom_ctx, netlist_annotation, module_manager, module_name_map,
+    global_ports, pin_constraints,
+    std::string(TOP_TESTBENCH_SHARED_INPUT_POSTFIX), clock_port_names);
   print_verilog_testbench_random_stimuli(
-    fp, atom_ctx, netlist_annotation, module_manager, global_ports,
-    pin_constraints, clock_port_names,
+    fp, atom_ctx, netlist_annotation, module_manager, module_name_map,
+    global_ports, pin_constraints, clock_port_names,
     std::string(TOP_TESTBENCH_SHARED_INPUT_POSTFIX),
     std::string(TOP_TESTBENCH_CHECKFLAG_PORT_POSTFIX),
     std::vector<BasicPort>(

openfpga/src/fpga_verilog/verilog_top_testbench.h

@@ -17,6 +17,7 @@
 #include "io_name_map.h"
 #include "memory_bank_shift_register_banks.h"
 #include "module_manager.h"
+#include "module_name_map.h"
 #include "pin_constraints.h"
 #include "simulation_setting.h"
 #include "verilog_testbench_options.h"
@@ -40,6 +41,7 @@ int print_verilog_full_testbench(
   const PlacementContext& place_ctx, const PinConstraints& pin_constraints,
   const BusGroup& bus_group, const std::string& bitstream_file,
   const IoLocationMap& io_location_map, const IoNameMap& io_name_map,
+  const ModuleNameMap& module_name_map,
   const VprNetlistAnnotation& netlist_annotation,
   const std::string& circuit_name, const std::string& verilog_fname,
   const SimulationSetting& simulation_parameters,

openfpga/src/fpga_verilog/verilog_wire.cpp

@@ -34,6 +34,7 @@ namespace openfpga {
 static void print_verilog_wire_module(
   const ModuleManager& module_manager, const CircuitLibrary& circuit_lib,
   std::fstream& fp, const CircuitModelId& wire_model,
+  const ModuleNameMap& module_name_map,
   const e_verilog_default_net_type& default_net_type) {
   /* Ensure a valid file handler*/
   VTR_ASSERT(true == valid_file_stream(fp));
@@ -55,8 +56,8 @@ static void print_verilog_wire_module(
 
   /* Create a Verilog Module based on the circuit model, and add to module
    * manager */
-  ModuleId wire_module =
-    module_manager.find_module(circuit_lib.model_name(wire_model));
+  ModuleId wire_module = module_manager.find_module(
+    module_name_map.name(circuit_lib.model_name(wire_model)));
   VTR_ASSERT(true == module_manager.valid_module_id(wire_module));
 
   /* dump module definition + ports */
@@ -106,6 +107,7 @@ static void print_verilog_wire_module(
 void print_verilog_submodule_wires(const ModuleManager& module_manager,
                                    NetlistManager& netlist_manager,
                                    const CircuitLibrary& circuit_lib,
+                                   const ModuleNameMap& module_name_map,
                                    const std::string& submodule_dir,
                                    const std::string& submodule_dir_name,
                                    const FabricVerilogOption& options) {
@@ -133,7 +135,7 @@ void print_verilog_submodule_wires(const ModuleManager& module_manager,
       continue;
     }
     print_verilog_wire_module(module_manager, circuit_lib, fp, model,
-                              options.default_net_type());
+                              module_name_map, options.default_net_type());
   }
   print_verilog_comment(
     fp, std::string("----- END Verilog modules for regular wires -----"));

openfpga/src/fpga_verilog/verilog_wire.h

@@ -10,6 +10,7 @@
 #include "circuit_library.h"
 #include "fabric_verilog_options.h"
 #include "module_manager.h"
+#include "module_name_map.h"
 #include "netlist_manager.h"
 #include "verilog_port_types.h"
 
@@ -23,6 +24,7 @@ namespace openfpga {
 void print_verilog_submodule_wires(const ModuleManager& module_manager,
                                    NetlistManager& netlist_manager,
                                    const CircuitLibrary& circuit_lib,
+                                   const ModuleNameMap& module_name_map,
                                    const std::string& submodule_dir,
                                    const std::string& submodule_dir_name,
                                    const FabricVerilogOption& options);

openfpga/src/utils/fabric_global_port_info_utils.cpp

@@ -72,15 +72,19 @@ std::vector<FabricGlobalPortId> find_fabric_global_programming_set_ports(
  *******************************************************************/
 bool port_is_fabric_global_reset_port(
   const FabricGlobalPortInfo& fabric_global_port_info,
-  const ModuleManager& module_manager, const BasicPort& port) {
+  const ModuleManager& module_manager, const ModuleNameMap& module_name_map,
+  const BasicPort& port) {
   /* Find the top_module: the fabric global ports are always part of the ports
    * of the top/core module. If there is a core module, we should consider core
    * only */
-  ModuleId top_module =
-    module_manager.find_module(generate_fpga_top_module_name());
+  ModuleId top_module = module_manager.find_module(
+    module_name_map.name(generate_fpga_top_module_name()));
   VTR_ASSERT(true == module_manager.valid_module_id(top_module));
-  ModuleId core_module =
-    module_manager.find_module(generate_fpga_core_module_name());
+  std::string core_module_name = generate_fpga_core_module_name();
+  if (module_name_map.name_exist(core_module_name)) {
+    core_module_name = module_name_map.name(core_module_name);
+  }
+  ModuleId core_module = module_manager.find_module(core_module_name);
   if (module_manager.valid_module_id(core_module)) {
     top_module = core_module;
   }
@@ -111,15 +115,19 @@ bool port_is_fabric_global_reset_port(
  *******************************************************************/
 FabricGlobalPortId find_fabric_global_port(
   const FabricGlobalPortInfo& fabric_global_port_info,
-  const ModuleManager& module_manager, const BasicPort& port) {
+  const ModuleManager& module_manager, const ModuleNameMap& module_name_map,
+  const BasicPort& port) {
   /* Find the top_module: the fabric global ports are always part of the ports
    * of the top/core module. If there is a core module, we should consider core
    * only */
-  ModuleId top_module =
-    module_manager.find_module(generate_fpga_top_module_name());
+  ModuleId top_module = module_manager.find_module(
+    module_name_map.name(generate_fpga_top_module_name()));
   VTR_ASSERT(true == module_manager.valid_module_id(top_module));
-  ModuleId core_module =
-    module_manager.find_module(generate_fpga_core_module_name());
+  std::string core_module_name = generate_fpga_core_module_name();
+  if (module_name_map.name_exist(core_module_name)) {
+    core_module_name = module_name_map.name(core_module_name);
+  }
+  ModuleId core_module = module_manager.find_module(core_module_name);
   if (module_manager.valid_module_id(core_module)) {
     top_module = core_module;
   }

openfpga/src/utils/fabric_global_port_info_utils.h

@@ -8,6 +8,7 @@
 
 #include "fabric_global_port_info.h"
 #include "module_manager.h"
+#include "module_name_map.h"
 
 /********************************************************************
  * Function declaration
@@ -24,11 +25,13 @@ std::vector<FabricGlobalPortId> find_fabric_global_programming_set_ports(
 
 bool port_is_fabric_global_reset_port(
   const FabricGlobalPortInfo& fabric_global_port_info,
-  const ModuleManager& module_manager, const BasicPort& port);
+  const ModuleManager& module_manager, const ModuleNameMap& module_name_map,
+  const BasicPort& port);
 
 FabricGlobalPortId find_fabric_global_port(
   const FabricGlobalPortInfo& fabric_global_port_info,
-  const ModuleManager& module_manager, const BasicPort& port);
+  const ModuleManager& module_manager, const ModuleNameMap& module_name_map,
+  const BasicPort& port);
 
 } /* end namespace openfpga */
 

openfpga_flow/openfpga_shell_scripts/module_rename_full_testbench_example_script.openfpga

@@ -0,0 +1,74 @@
+# Run VPR for the 'and' design
+#--write_rr_graph example_rr_graph.xml
+vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --device ${OPENFPGA_VPR_DEVICE} --route_chan_width ${OPENFPGA_VPR_ROUTE_CHAN_WIDTH} --clock_modeling ideal
+
+# Read OpenFPGA architecture definition
+read_openfpga_arch -f ${OPENFPGA_ARCH_FILE}
+
+# Read OpenFPGA simulation settings
+read_openfpga_simulation_setting -f ${OPENFPGA_SIM_SETTING_FILE}
+
+# Annotate the OpenFPGA architecture to VPR data base
+# to debug use --verbose options
+link_openfpga_arch --sort_gsb_chan_node_in_edges
+
+# Check and correct any naming conflicts in the BLIF netlist
+check_netlist_naming_conflict --fix --report ./netlist_renaming.xml
+
+# Apply fix-up to Look-Up Table truth tables based on packing results
+lut_truth_table_fixup
+
+# Build the module graph
+#  - Enabled compression on routing architecture modules
+#  - Enable pin duplication on grid modules
+build_fabric --compress_routing --group_config_block ${OPENFPGA_GROUP_TILE_CONFIG_OPTION} ${OPENFPGA_FABRIC_MODULE_NAME_OPTIONS} #--verbose
+# Add a fpga core between fpga top and the underlying modules
+${OPENFPGA_ADD_FPGA_CORE_MODULE}
+
+# Write the fabric hierarchy of module graph to a file
+# This is used by hierarchical PnR flows
+write_fabric_hierarchy --file ./fabric_hierarchy.txt
+
+# Repack the netlist to physical pbs
+# This must be done before bitstream generator and testbench generation
+# Strongly recommend it is done after all the fix-up have been applied
+repack #--verbose
+
+# Build the bitstream
+#  - Output the fabric-independent bitstream to a file
+build_architecture_bitstream --verbose --write_file fabric_independent_bitstream.xml
+
+# Build fabric-dependent bitstream
+build_fabric_bitstream --verbose
+
+# Write fabric-dependent bitstream
+write_fabric_bitstream --file fabric_bitstream.bit --format plain_text
+
+# Write the Verilog netlist for FPGA fabric
+#  - Enable the use of explicit port mapping in Verilog netlist
+write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --print_user_defined_template --verbose
+
+# Write the Verilog testbench for FPGA fabric
+#  - We suggest the use of same output directory as fabric Verilog netlists
+#  - Must specify the reference benchmark file if you want to output any testbenches
+#  - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA
+#  - Enable pre-configured top-level testbench which is a fast verification skipping programming phase
+#  - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts
+write_full_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --explicit_port_mapping --include_signal_init --bitstream fabric_bitstream.bit
+
+# Write the SDC files for PnR backend
+#  - Turn on every options here
+# FIXME: Not supported yet. 
+#write_pnr_sdc --file ./SDC
+
+# Write SDC to disable timing for configure ports
+#write_sdc_disable_timing_configure_ports --file ./SDC/disable_configure_ports.sdc
+
+# Write the SDC to run timing analysis for a mapped FPGA fabric
+#write_analysis_sdc --file ./SDC_analysis
+
+# Finish and exit OpenFPGA
+exit
+
+# Note :
+# To run verification at the end of the flow maintain source in ./SRC directory

openfpga_flow/openfpga_shell_scripts/module_rename_preconfig_testbench_example_script.openfpga

@@ -0,0 +1,84 @@
+# Run VPR for the 'and' design
+#--write_rr_graph example_rr_graph.xml
+vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --device ${OPENFPGA_VPR_DEVICE} --route_chan_width ${OPENFPGA_VPR_ROUTE_CHAN_WIDTH} --clock_modeling ideal ${OPENFPGA_VPR_EXTRA_OPTIONS}
+
+# Read OpenFPGA architecture definition
+read_openfpga_arch -f ${OPENFPGA_ARCH_FILE}
+
+# Read OpenFPGA simulation settings
+read_openfpga_simulation_setting -f ${OPENFPGA_SIM_SETTING_FILE}
+
+# Annotate the OpenFPGA architecture to VPR data base
+# to debug use --verbose options
+link_openfpga_arch --sort_gsb_chan_node_in_edges
+
+# Check and correct any naming conflicts in the BLIF netlist
+check_netlist_naming_conflict --fix --report ./netlist_renaming.xml
+
+# Apply fix-up to Look-Up Table truth tables based on packing results
+lut_truth_table_fixup
+
+# Optionally pb pin fixup
+${OPENFPGA_PB_PIN_FIXUP_COMMAND}
+
+# Build the module graph
+#  - Enabled compression on routing architecture modules
+#  - Enable pin duplication on grid modules
+build_fabric --compress_routing ${OPENFPGA_FABRIC_MODULE_NAME_OPTIONS} ${OPENFPGA_GROUP_TILE_CONFIG_OPTION} #--verbose
+# Add a fpga core between fpga top and the underlying modules
+${OPENFPGA_ADD_FPGA_CORE_MODULE}
+# Output module naming for debugging. Comment it if not required
+write_module_naming_rules --file module_names_before_renaming.xml
+# Rename modules with a given rule
+rename_modules --file ${OPENFPGA_RENAME_MODULE_FILE}
+# Output module naming for debugging. Comment it if not required
+write_module_naming_rules --file module_names_after_renaming.xml
+
+# Write the fabric hierarchy of module graph to a file
+# This is used by hierarchical PnR flows
+write_fabric_hierarchy --file ./fabric_hierarchy.txt
+
+# Repack the netlist to physical pbs
+# This must be done before bitstream generator and testbench generation
+# Strongly recommend it is done after all the fix-up have been applied
+repack #--verbose
+
+# Build the bitstream
+#  - Output the fabric-independent bitstream to a file
+build_architecture_bitstream --verbose --write_file fabric_independent_bitstream.xml
+
+# Build fabric-dependent bitstream
+build_fabric_bitstream --verbose
+
+# Write fabric-dependent bitstream
+write_fabric_bitstream --file fabric_bitstream.bit --format plain_text
+
+# Write the Verilog netlist for FPGA fabric
+#  - Enable the use of explicit port mapping in Verilog netlist
+write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --print_user_defined_template --verbose
+
+# Write the Verilog testbench for FPGA fabric
+#  - We suggest the use of same output directory as fabric Verilog netlists
+#  - Must specify the reference benchmark file if you want to output any testbenches
+#  - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA
+#  - Enable pre-configured top-level testbench which is a fast verification skipping programming phase
+#  - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts
+write_preconfigured_fabric_wrapper --embed_bitstream iverilog --file ./SRC  ${OPENFPGA_VERILOG_TESTBENCH_OPTIONS}
+write_preconfigured_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} ${OPENFPGA_VERILOG_TESTBENCH_OPTIONS} 
+
+# Write the SDC files for PnR backend
+#  - Turn on every options here
+# FIXME: Not supported yet. 
+#write_pnr_sdc --file ./SDC
+
+# Write SDC to disable timing for configure ports
+#write_sdc_disable_timing_configure_ports --file ./SDC/disable_configure_ports.sdc
+
+# Write the SDC to run timing analysis for a mapped FPGA fabric
+#write_analysis_sdc --file ./SDC_analysis
+
+# Finish and exit OpenFPGA
+exit
+
+# Note :
+# To run verification at the end of the flow maintain source in ./SRC directory

openfpga_flow/regression_test_scripts/basic_reg_test.sh

@@ -202,6 +202,11 @@ run-task basic_tests/group_config_block/group_config_block_hetero_fabric_tile $@
 run-task basic_tests/group_config_block/group_config_block_hetero_fabric_tile_Lshape $@
 run-task basic_tests/group_config_block/group_config_block_homo_fabric_tile_global_tile_clock_io_subtile $@
 
+echo -e "Module naming";
+run-task basic_tests/module_naming/using_index $@
+run-task basic_tests/module_naming/renaming_rules $@
+run-task basic_tests/module_naming/renaming_rules_strong $@
+
 echo -e "Testing global port definition from tiles";
 run-task basic_tests/global_tile_ports/global_tile_clock $@
 run-task basic_tests/global_tile_ports/global_tile_clock_subtile $@

openfpga_flow/tasks/basic_tests/module_naming/renaming_rules/config/module_names.xml

@@ -0,0 +1,4 @@
+<module_names>
+  <module_name default="tile_1__1_" given="tile_clb"/>
+  <module_name default="tile_2__1_" given="tile_dsp"/>
+</module_names>

openfpga_flow/tasks/basic_tests/module_naming/renaming_rules/config/task.conf

@@ -0,0 +1,51 @@
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+# Configuration file for running experiments
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs
+# Each job execute fpga_flow script on combination of architecture & benchmark
+# timeout_each_job is timeout for each job
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+
+[GENERAL]
+run_engine=openfpga_shell
+power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml
+power_analysis = false
+spice_output=false
+verilog_output=true
+timeout_each_job = 20*60
+fpga_flow=yosys_vpr
+
+[OpenFPGA_SHELL]
+openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/module_rename_preconfig_testbench_example_script.openfpga
+openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_frac_N8_reset_softadder_register_scan_chain_dsp8_caravel_io_skywater130nm_fdhd_cc_openfpga.xml
+openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_sim_openfpga.xml
+openfpga_vpr_extra_options=--constant_net_method route --skip_sync_clustering_and_routing_results on
+openfpga_pb_pin_fixup_command = pb_pin_fixup --verbose
+openfpga_vpr_device=3x2
+openfpga_vpr_route_chan_width=60
+openfpga_group_tile_config_option=--group_tile ${PATH:TASK_DIR}/config/tile_config.xml
+openfpga_verilog_testbench_options=
+openfpga_add_fpga_core_module=
+openfpga_fabric_module_name_options=
+openfpga_rename_module_file = ${PATH:TASK_DIR}/config/module_names.xml
+
+[ARCHITECTURES]
+arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_frac_N8_tileable_reset_softadder_register_scan_chain_dsp8_nonLR_caravel_io_skywater130nm.xml
+
+[BENCHMARKS]
+bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/mac/mac_8/mac_8.v
+
+[SYNTHESIS_PARAM]
+# Yosys script parameters
+bench_yosys_cell_sim_verilog_common=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/k4_frac_N8_tileable_reset_softadder_register_scan_chain_dsp8_nonLR_caravel_io_skywater130nm_cell_sim.v
+bench_yosys_dsp_map_verilog_common=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/k4_frac_N8_tileable_reset_softadder_register_scan_chain_dsp8_nonLR_caravel_io_skywater130nm_dsp_map.v
+bench_yosys_dsp_map_parameters_common=-D DSP_A_MAXWIDTH=8 -D DSP_B_MAXWIDTH=8 -D DSP_A_MINWIDTH=2 -D DSP_B_MINWIDTH=2 -D DSP_NAME=mult_8x8
+bench_read_verilog_options_common = -nolatches
+bench_yosys_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_dsp_flow.ys
+bench_yosys_rewrite_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_flow_with_rewrite.ys;${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_rewrite_flow.ys
+
+bench0_top = mac_8
+
+[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
+end_flow_with_test=
+vpr_fpga_verilog_formal_verification_top_netlist=

openfpga_flow/tasks/basic_tests/module_naming/renaming_rules/config/tile_config.xml

@@ -0,0 +1 @@
+<tiles style="top_left"/>

openfpga_flow/tasks/basic_tests/module_naming/renaming_rules_strong/config/module_names.xml

@@ -0,0 +1,12 @@
+<module_names>
+  <module_name default="mux_tree_tapbuf_size10_mem" given="mux_tree_mem_max"/>
+  <module_name default="mux_tree_size_2" given="mux_tree_mini"/>
+  <module_name default="logical_tile_clb_mode_clb_" given="logical_tile_clb_mode_clb_unique"/>
+  <module_name default="sb_1__1_" given="sb_max"/>
+  <module_name default="cby_1__1_" given="cby_max"/>
+  <module_name default="cbx_1__1_" given="cbx_max"/>
+  <module_name default="tile_1__1_" given="tile_clb"/>
+  <module_name default="tile_2__1_" given="tile_dsp"/>
+  <module_name default="fpga_core" given="pfabric_core"/>
+  <module_name default="fpga_top" given="pfabric_top"/>
+</module_names>

openfpga_flow/tasks/basic_tests/module_naming/renaming_rules_strong/config/task.conf

@@ -0,0 +1,51 @@
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+# Configuration file for running experiments
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs
+# Each job execute fpga_flow script on combination of architecture & benchmark
+# timeout_each_job is timeout for each job
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+
+[GENERAL]
+run_engine=openfpga_shell
+power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml
+power_analysis = false
+spice_output=false
+verilog_output=true
+timeout_each_job = 20*60
+fpga_flow=yosys_vpr
+
+[OpenFPGA_SHELL]
+openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/module_rename_preconfig_testbench_example_script.openfpga
+openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_frac_N8_reset_softadder_register_scan_chain_dsp8_caravel_io_skywater130nm_fdhd_cc_openfpga.xml
+openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_sim_openfpga.xml
+openfpga_vpr_extra_options=--constant_net_method route --skip_sync_clustering_and_routing_results on
+openfpga_pb_pin_fixup_command = pb_pin_fixup --verbose
+openfpga_vpr_device=3x2
+openfpga_vpr_route_chan_width=60
+openfpga_group_tile_config_option=--group_tile ${PATH:TASK_DIR}/config/tile_config.xml
+openfpga_verilog_testbench_options=
+openfpga_add_fpga_core_module=add_fpga_core_to_fabric --instance_name fpga_core_inst
+openfpga_fabric_module_name_options=
+openfpga_rename_module_file = ${PATH:TASK_DIR}/config/module_names.xml
+
+[ARCHITECTURES]
+arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_frac_N8_tileable_reset_softadder_register_scan_chain_dsp8_nonLR_caravel_io_skywater130nm.xml
+
+[BENCHMARKS]
+bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/mac/mac_8/mac_8.v
+
+[SYNTHESIS_PARAM]
+# Yosys script parameters
+bench_yosys_cell_sim_verilog_common=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/k4_frac_N8_tileable_reset_softadder_register_scan_chain_dsp8_nonLR_caravel_io_skywater130nm_cell_sim.v
+bench_yosys_dsp_map_verilog_common=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/k4_frac_N8_tileable_reset_softadder_register_scan_chain_dsp8_nonLR_caravel_io_skywater130nm_dsp_map.v
+bench_yosys_dsp_map_parameters_common=-D DSP_A_MAXWIDTH=8 -D DSP_B_MAXWIDTH=8 -D DSP_A_MINWIDTH=2 -D DSP_B_MINWIDTH=2 -D DSP_NAME=mult_8x8
+bench_read_verilog_options_common = -nolatches
+bench_yosys_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_dsp_flow.ys
+bench_yosys_rewrite_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_flow_with_rewrite.ys;${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_rewrite_flow.ys
+
+bench0_top = mac_8
+
+[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
+end_flow_with_test=
+vpr_fpga_verilog_formal_verification_top_netlist=

openfpga_flow/tasks/basic_tests/module_naming/renaming_rules_strong/config/tile_config.xml

@@ -0,0 +1 @@
+<tiles style="top_left"/>

openfpga_flow/tasks/basic_tests/module_naming/using_index/config/task.conf

@@ -0,0 +1,39 @@
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+# Configuration file for running experiments
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs
+# Each job execute fpga_flow script on combination of architecture & benchmark
+# timeout_each_job is timeout for each job
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+
+[GENERAL]
+run_engine=openfpga_shell
+power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml
+power_analysis = false
+spice_output=false
+verilog_output=true
+timeout_each_job = 20*60
+fpga_flow=yosys_vpr
+
+[OpenFPGA_SHELL]
+openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/module_rename_full_testbench_example_script.openfpga
+openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_openfpga.xml
+openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_sim_openfpga.xml
+openfpga_group_tile_config_option=--group_tile ${PATH:TASK_DIR}/config/tile_config.xml
+openfpga_add_fpga_core_module=
+openfpga_vpr_device=auto
+openfpga_vpr_route_chan_width=20
+openfpga_fabric_module_name_options=--name_module_using_index
+
+[ARCHITECTURES]
+arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_TileOrgzTl_40nm.xml
+
+[BENCHMARKS]
+bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/or2/or2.v
+
+[SYNTHESIS_PARAM]
+bench_read_verilog_options_common = -nolatches
+bench0_top = or2
+
+[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
+end_flow_with_test=