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[doc] typo

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tangxifan 2023-09-17 13:46:54 -07:00
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docs/source/manual/file_formats/module_naming_file.rst
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@ -8,7 +8,7 @@ The XML-based description language is used to describe module names for an FPGA
- the built-in name or default name for each module when building an FPGA fabric
- the customized name which is given by users for each module, in place of the built-in names
Using the description language, users can customize the name for each module in an FPGA fabric, including testbenches.
Using the description language, users can customize the name for each module in an FPGA fabric, excluding testbenches.
Under the root node ``<module_names>``, naming rules can be defined line-by-line through syntax ``<module_name>``.