From 7e71f655dfc2c5c6a23d2fd8a631ef3704c6ffab Mon Sep 17 00:00:00 2001 From: tangxifan Date: Sun, 17 Sep 2023 13:46:54 -0700 Subject: [PATCH] [doc] typo --- docs/source/manual/file_formats/module_naming_file.rst | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/docs/source/manual/file_formats/module_naming_file.rst b/docs/source/manual/file_formats/module_naming_file.rst index 17d2646cd..6f4853bae 100644 --- a/docs/source/manual/file_formats/module_naming_file.rst +++ b/docs/source/manual/file_formats/module_naming_file.rst @@ -8,7 +8,7 @@ The XML-based description language is used to describe module names for an FPGA - the built-in name or default name for each module when building an FPGA fabric - the customized name which is given by users for each module, in place of the built-in names -Using the description language, users can customize the name for each module in an FPGA fabric, including testbenches. +Using the description language, users can customize the name for each module in an FPGA fabric, excluding testbenches. Under the root node ````, naming rules can be defined line-by-line through syntax ````.