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5389 Commits

Author SHA1 Message Date
tangxifan ac9046b7d2 [Doc] Remove ``define_simulation.v`` since it is no longer needed. 2021-06-29 15:38:35 -06:00
tangxifan 7ac7de789e [Tool] Add a new option ``--no_self_checking`` so that users can output a simple testbench without self checking codes 2021-06-29 15:26:40 -06:00
tangxifan 77dddaeb39 [Tool] Remove the preprocessing flags ``FORMAL_SIMULATION`` and ``FORMAL_VERIFICAITON`` because now ``write_testbench`` command can be called many times to generate different versions 2021-06-29 14:26:33 -06:00
tangxifan d0670e64d4
Merge pull request #347 from lnis-uofu/testbench_force 
Use ``force`` in preconfigured testbenches to avoid instrusive code modification on flip-flop HDL
 2021-06-29 13:43:29 -06:00
tangxifan a3208b332b [Tool] Use 'force' in preconfigured testbenches to avoid instrusive code modification on flip-flop HDL 2021-06-29 11:50:53 -06:00
tangxifan 75a12e55de [HDL] Remove the instrusive signal initialization in the configuration flip-flop HDL codes 2021-06-29 11:40:22 -06:00
tangxifan 36764b8180
Merge pull request #345 from lnis-uofu/testbench_cleanup 
Remove the hardcoded factor when computing simulation timing
 2021-06-29 10:55:13 -06:00
tangxifan dfe1db996a [Tool] Remove the hardcoded factor when computing simulation timing; There should be no hidden parameters impacting simulation time 2021-06-29 09:56:04 -06:00
tangxifan 74148ec491
Merge pull request #343 from lnis-uofu/preconfig_wrapper 
Bug fix in Preconfigured Fabric Wrapper Generator
 2021-06-27 21:44:56 -06:00
tangxifan 403190a051
Merge branch 'master' into preconfig_wrapper 2021-06-27 20:05:36 -06:00
tangxifan b4c587f10b [Test] Added the new test cases to regression tests 2021-06-27 19:58:15 -06:00
tangxifan 6f0600e17f [Test] Added two test cases for generating preconfigured fabric wrapper in different styles 2021-06-27 19:56:01 -06:00
tangxifan 4a623bec79 [Script] Add example openfpga shell script to generate preconfigured fabric wrapper 2021-06-27 19:55:40 -06:00
tangxifan 87446a14c3 [Tool] Bug fix for the option ``--embed_bitstream none`` 2021-06-27 19:45:06 -06:00
tangxifan 873b6c4d36
Merge pull request #342 from lnis-uofu/preconfig_wrapper 
New option ``--embed_bitstream`` for Preconfigured fabric wrapper in place of ``--support_icarus_simulator``
 2021-06-25 17:39:56 -06:00
tangxifan 30027b8c15 [Doc] Update doc to deprecate anything related to '--support_icarus_simulator' and '--include_signal_init' 2021-06-25 15:27:15 -06:00
tangxifan 991062e9bf [Tool] Bug fix 2021-06-25 15:22:42 -06:00
tangxifan fae5e1dfdf [Script] Upgrade openfpga shell script with the new option '--embed_bitstream' 2021-06-25 15:16:37 -06:00
tangxifan 11d0283771 [Doc] Remove option '--support_icarus_simulator'. Add option '--embed_bitstream' 2021-06-25 15:11:12 -06:00
tangxifan 90163fab6c [Tool] Replace option '--support_icarus_simulator' with a new one '--preload_bitstream <string>' 2021-06-25 15:06:07 -06:00
tangxifan 1b6e1e5516
Merge pull request #341 from lnis-uofu/sim_info 
Update Simulation Exchangeable Information Writer
 2021-06-25 11:42:44 -06:00
tangxifan 507f5ee54c [Doc] Update documentation about time unit support in writing simulation file 2021-06-25 10:34:43 -06:00
tangxifan 2bb514c51a [Tool] Support time unit in writing simulation information file 2021-06-25 10:33:29 -06:00
tangxifan 8e2ba718d0 [Doc] update documentation on the new option '--testbench_type' 2021-06-25 10:16:48 -06:00
tangxifan bcc16d732c [Tool] Add new option 'testbench_type' so that simulation task can write different information for different testbenches 2021-06-25 10:10:16 -06:00
tangxifan 91a2dc4fd7
Merge pull request #340 from lnis-uofu/opt_signal_init 
Signal initialization HDL codes will not be outputted unless specified in the command-line option
 2021-06-24 19:28:57 -06:00
tangxifan 67dec810eb [Tool] Remove icarus simulator flag; Reduce the file size of preconfigured fabric wrapper by only output the necessary force/deposit HDL codes 2021-06-24 17:27:32 -06:00
tangxifan 549657e1fb [Tool] Remove out-of-date flag: INITIAL_SIMULATION from code base 2021-06-24 17:13:36 -06:00
tangxifan 5364d8104f [Tool] Add signal_init option to preconfigured fabric wrapper writer 2021-06-24 17:07:41 -06:00
tangxifan 779437cd37 [Doc] Update documentation to remove out-of-date options related to signal_init 2021-06-24 17:07:15 -06:00
tangxifan 21d1519658 [Tool] Remove signal initialization flag; Now the HDL codes will not be outputted unless specified in the option 2021-06-24 16:56:28 -06:00
tangxifan c1dab21686
Merge pull request #269 from lnis-uofu/dev 
Patch wrong paths in FPGA-SDC
 2021-06-23 10:39:33 -06:00
tangxifan 477cba1c7e
Merge branch 'master' into verilog_testbench 2021-06-23 09:18:18 -06:00
tangxifan ce3c80f499
Merge branch 'master' into dev 2021-06-23 09:15:03 -06:00
tangxifan 4ca805b5d5
Merge pull request #337 from lnis-uofu/write_io_mapping 
Write io mapping
 2021-06-22 18:55:51 -06:00
tangxifan 4fa745caa8
Merge branch 'master' into write_io_mapping 2021-06-22 17:42:15 -06:00
tangxifan 931dc21687
Merge pull request #339 from lnis-uofu/micro_benchmark 
Micro benchmark
 2021-06-22 17:42:03 -06:00
tangxifan b2c30e3103 [Test] Bug fix in mcnc openfpga shell script 2021-06-22 16:40:24 -06:00
tangxifan e34fbf8ecf [Test] Deploy MCNC big20 to the micro benchmark regression test 2021-06-22 16:36:04 -06:00
tangxifan f06017581c [Test] Bug fix in counter micro benchmark tests 2021-06-22 16:33:50 -06:00
tangxifan 0a0d10b36d [HDL] Bug fix in Verilog syntax 2021-06-22 16:18:46 -06:00
tangxifan 4421dfcbbd
Merge branch 'master' into micro_benchmark 2021-06-22 14:29:29 -06:00
ganeshgore cbcf41062f
Merge pull request #338 from lnis-uofu/openfpga_flow_dir_name 
Support benchmarks with same top module names in openfpga flow script
 2021-06-22 11:28:15 -07:00
tangxifan fd580bb36f [Script] Update script to keep back compatibility: local run directory is different only for those benchmarks sharing the same top module name 2021-06-22 11:45:23 -06:00
tangxifan 260b14c3d4 [CI] Add the micro benchmark regression test to CI 2021-06-21 18:37:42 -06:00
tangxifan 0b2d6eb147 [Test] Add micro benchmark to a dedicated regression test 2021-06-21 18:35:41 -06:00
tangxifan 760570d883 [Test] Update counter test case for cover most counter HDL design 2021-06-21 18:13:18 -06:00
tangxifan 9c24a739be [Test] Added a MAC benchmark sweeping test 2021-06-21 17:40:53 -06:00
tangxifan 07dcf3ad27 [HDL] Add more micro benchmarks for counter, and-gate and mac unit 2021-06-21 16:48:35 -06:00
tangxifan f9e66e1bae [Script] Support benchmarks with same top module names in openfpga flow script; Now each benchmark local run directory has a unique name; 2021-06-21 15:27:12 -06:00