tangxifan
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68f5a9dc44
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Merge pull request #324 from lnis-uofu/testbench_external_bitstream
Support memory bank configuration protocol in bitstream writer and full testbench that reads external bitstream file
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2021-06-07 21:18:43 -06:00 |
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tangxifan
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9808b61b36
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[Tool] Bug fix on the unfit vector size of bit index register in Verilog testbench in some cases
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2021-06-07 20:06:39 -06:00 |
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tangxifan
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789be124a0
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Merge branch 'testbench_external_bitstream' of https://github.com/LNIS-Projects/OpenFPGA into testbench_external_bitstream
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2021-06-07 19:20:39 -06:00 |
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tangxifan
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5ecd975ec7
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[Test] Bug fix
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2021-06-07 19:20:10 -06:00 |
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tangxifan
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73fd9e2205
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Merge branch 'master' into testbench_external_bitstream
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2021-06-07 18:01:39 -06:00 |
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tangxifan
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54a53bc988
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[Doc] Update documentation on the minor changes on bitstream file for memory bank protocol
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2021-06-07 17:58:00 -06:00 |
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tangxifan
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9556f994b4
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[Test] Use 'write_full_testbench' in all the memory bank -related test cases
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2021-06-07 17:49:40 -06:00 |
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tangxifan
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ba75c18378
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[Tool] Now 'write_full_testbench' supports memory bank configuration protocol
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2021-06-07 17:40:07 -06:00 |
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tangxifan
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c680dd51ed
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Merge pull request #323 from lnis-uofu/testbench_external_bitstream
Support frame-based configuration protocol in bitstream writer and full testbench that reads external bitstream file
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2021-06-07 16:00:11 -06:00 |
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tangxifan
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1a5902ca74
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[Tool] Bug fix in finding pruned bitstream for frame-based protocol when fast configuration is enabled
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2021-06-07 14:32:56 -06:00 |
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tangxifan
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0fee741008
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[Doc] Update documentation on the minor changes on fabric bitstream file format
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2021-06-07 14:22:35 -06:00 |
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tangxifan
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732a1feaa4
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Merge branch 'master' into testbench_external_bitstream
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2021-06-07 14:04:47 -06:00 |
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tangxifan
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a67196178e
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[Test] Now use 'write_full_testbench' in configuration frame test cases
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2021-06-07 13:58:15 -06:00 |
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tangxifan
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af298de121
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[Tool] Patch bugs in the full testbench writing using external bitstream file for frame-based configuration protocol
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2021-06-07 13:53:32 -06:00 |
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tangxifan
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d644b8f22d
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[Tool] Support external bitstream file when generating full testbench for frame-based decoder
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2021-06-07 11:55:11 -06:00 |
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tangxifan
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7fb5c16b56
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Merge pull request #321 from lnis-uofu/testbench_external_bitstream
Support fast configuration in bitstream writer and full testbench that reads external bitstream file
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2021-06-04 21:34:51 -06:00 |
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tangxifan
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618b04568f
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[Tool] Remove unnecessary new line in bitstream file
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2021-06-04 20:07:42 -06:00 |
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tangxifan
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c30be6e95e
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[Doc] Update documentation about the fast configuration for write bitstream command
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2021-06-04 20:00:28 -06:00 |
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tangxifan
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cf7addb1a6
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[Tool] Add heads to bitstream plain text file
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2021-06-04 19:48:48 -06:00 |
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tangxifan
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27fa15603a
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[Tool] Patch test case due to changes in the template script
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2021-06-04 18:17:47 -06:00 |
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tangxifan
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70fb3a85dc
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[Tool] Patch fast configuration in bitstream writing
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2021-06-04 17:23:10 -06:00 |
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tangxifan
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49b971620e
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Merge branch 'master' into testbench_external_bitstream
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2021-06-04 16:49:41 -06:00 |
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tangxifan
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d98be9f87b
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[Tool] Remove icarus requirement on vcd writing in Verilog testbenches; Since vcd writing commands are standard Verilog
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2021-06-04 16:45:00 -06:00 |
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tangxifan
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6e69c2d70a
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[Tool] Patch fast configuration in full Verilog testbench generator
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2021-06-04 16:34:55 -06:00 |
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tangxifan
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e9fa44cc25
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[Tool] Add fast configuration to the write bitstream command in example shell script
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2021-06-04 16:24:56 -06:00 |
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tangxifan
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061f832429
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[Tool] Enable fast configuration when writing fabric bitstream
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2021-06-04 16:23:40 -06:00 |
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tangxifan
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059e74b4ef
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[Doc] Add --fast configuration option to documentation for 'write_full_testbench'
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2021-06-04 15:17:00 -06:00 |
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tangxifan
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5f96d440ec
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[Test] Deploy 'write_full_testbench' openfpga shell script to multi-headed configuration chain with auto-tuned fast configuration
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2021-06-04 11:48:05 -06:00 |
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tangxifan
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ec203d3a5c
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[Test] Deploy 'write_full_testbench' openfpga shell script to all the fast configuration chain test cases
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2021-06-04 11:35:23 -06:00 |
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tangxifan
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2068291de0
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[Test] Now deploy the 'write_full_testbench' openfpga shell script to all the configuration chain test cases
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2021-06-04 11:32:49 -06:00 |
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tangxifan
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aa4e1f5f9a
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[Test] Update test case which uses write_full_testbench openfpga shell script
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2021-06-04 11:29:43 -06:00 |
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tangxifan
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f5e90c9467
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[Script] Update openfpga shell script with fast configuration option
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2021-06-04 11:28:10 -06:00 |
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tangxifan
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81048d3698
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[Tool] Add option '--fast_configuration' to 'write_full_testbench' command
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2021-06-04 11:26:39 -06:00 |
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tangxifan
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98308133c1
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[Tool] Add configuration skip capability to top testbench which loads external bitstream file
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2021-06-04 11:24:05 -06:00 |
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tangxifan
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adb18d28b8
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[Tool] Remove unused arguments
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2021-06-04 10:37:28 -06:00 |
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tangxifan
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f36425e5d0
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Merge pull request #320 from lnis-uofu/testbench_external_bitstream
Preliminary support on full testbench generator using external bitstream file
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2021-06-03 18:43:45 -06:00 |
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tangxifan
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ebe30fc070
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[Test] Deploy write full testbench to multi-head configuration chain test case
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2021-06-03 17:08:33 -06:00 |
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tangxifan
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8fc90637e0
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[Script] Update write_full_testbench example script to support custom device layout in VPR
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2021-06-03 17:08:08 -06:00 |
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tangxifan
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b83d8826fb
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[Doc] Update documentation on the testbench organization/waveforms
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2021-06-03 16:54:13 -06:00 |
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tangxifan
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9bcaa820ae
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[Doc] Update documentation for the new command 'write_full_testbench'
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2021-06-03 16:18:07 -06:00 |
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tangxifan
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1e9f6eb439
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[Test] update configuration chain test to use new testbench
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2021-06-03 15:53:27 -06:00 |
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tangxifan
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51ca62a464
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[Script] Add example script for write_full_testbench command
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2021-06-03 15:48:59 -06:00 |
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tangxifan
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67485269d3
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Merge branch 'master' into testbench_external_bitstream
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2021-06-03 15:46:25 -06:00 |
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tangxifan
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ae6a46cd60
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[Tool] Add a new command write_full_testbench which outputs self-testable full testbench which loads external bitstream file; Currently only support configuration chain without fast configuration technique
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2021-06-03 15:41:11 -06:00 |
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tangxifan
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ef3cbe708c
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Merge pull request #317 from lnis-uofu/doc_patch
Patch FPGA-SDC to consider time unit in global port timing constraints
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2021-06-03 13:20:56 -06:00 |
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tangxifan
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72bf5c2564
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Merge branch 'master' into doc_patch
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2021-05-27 10:28:43 -06:00 |
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tangxifan
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1fd399736d
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[Tool] Patch FPGA-SDC to consider time unit in global port timing constraints
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2021-05-27 10:26:20 -06:00 |
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tangxifan
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537b73ba6e
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Merge pull request #314 from lnis-uofu/doc_patch
Documentation update on example circuit models for data memories
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2021-05-24 19:17:17 -06:00 |
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tangxifan
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16ae23f33e
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[Doc] Update notes about compilation guidelines
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2021-05-24 16:26:59 -06:00 |
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tangxifan
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9b40e74e25
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[Doc] Add example circuit models for multipliers and update technical highlight with links to the examples
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2021-05-24 15:24:50 -06:00 |