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Merge pull request #314 from lnis-uofu/doc_patch 

Documentation update on example circuit models for data memories
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docs/source/manual/arch_lang/circuit_model_examples.rst
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@ -284,6 +284,8 @@ This example shows:
SRAMs
~~~~~
.. note:: OpenFPGA does not auto-generate any netlist for SRAM cells. Users should define the HDL modeling in external netlists and ensure consistency to physical designs.
Template
````````
@ -963,16 +965,17 @@ This example shows:
.. note:: If the embedded harden logic are driven partially by LUT outputs, users may use the :ref:`file_formats_bitstream_setting` to gaurantee correct bitstream generation for the LUTs.
Datapath Flip-Flops
~~~~~~~~~~~~~~~~~~~
Flip-Flops
~~~~~~~~~~
.. note:: OpenFPGA does not auto-generate any netlist for datapath flip-flops. Users should define the HDL modeling in external netlists and ensure consistency to physical designs.
Template
````````
.. code-block:: xml
<circuit_model type="ccff|ff" name="<string>" prefix="<string>" spice_netlist="<string>" verilog_netlist="<string>"/>
<circuit_model type="ff" name="<string>" prefix="<string>" spice_netlist="<string>" verilog_netlist="<string>"/>
<design_technology type="cmos"/>
<input_buffer exist="<string>" circuit_model_name="<string>"/>
<output_buffer exist="<string>" circuit_model_name="<string>"/>
@ -987,16 +990,14 @@ Template
.. note:: FPGA-Verilog/SPICE currently support only one clock domain in the FPGA. Therefore there should be only one clock port to be defined and the size of the clock port should be 1.
.. option:: <circuit_model type="ccff|ff" name="<string>" prefix="<string>" spice_netlist="<string>" verilog_netlist="<string>"/>
.. option:: type="ff"
- ``type="ccff|ff"`` Specify the type of a flip-flop. ``ff`` is a regular flip-flop while ``ccff`` denotes a configuration-chain flip-flop
``ff`` is a regular flip-flop to be used in datapath logic, e.g., a configurable logic block.
.. note:: A flip-flop should at least have three types of ports, ``input``, ``output`` and ``clock``.
.. note:: If the user provides a customized Verilog/SPICE netlist, the bandwidth of ports should be defined to the same as the Verilog/SPICE netlist.
.. note:: In a valid FPGA architecture, users should provide at least either a ``ccff`` or ``sram`` circuit model, so that the configurations can loaded to core logic.
.. _circuit_model_dff_example:
D-type Flip-Flop
@ -1029,6 +1030,70 @@ This example shows:
- The flip-flop has ``set`` and ``reset`` functionalities
- The flip-flop port names defined differently in standard cell library and VPR architecture. The ``lib_name`` capture the port name defined in standard cells, while ``prefix`` capture the port name defined in ``pb_type`` of VPR architecture file
.. _circuit_model_multi_mode_ff_example:
Multi-mode Flip-Flop
````````````````````
:numref:`fig_multi_mode_ff_circuit_model` illustrates an example of a flip-flop which can be operate in different modes.
.. _fig_multi_mode_ff_circuit_model:
.. figure:: ./figures/multi_mode_ff_circuit_model.svg
:scale: 150%
:alt: Multi-mode flip-flop example
An example of a flip-flop which can be operate in different modes
The code describing this FF is:
.. code-block:: xml
<circuit_model type="ff" name="frac_ff" prefix="frac_ff" verilog_netlist="frac_ff.v" spice_netlist="frac_ff.sp">
<port type="input" prefix="D" lib_name="D" size="1"/>
<port type="input" prefix="Reset" lib_name="RST_OP" size="1" is_global="true"/>
<port type="output" prefix="Q" lib_name="Q" size="1"/>
<port type="clock" prefix="clock" lib_name="CLK" size="1" is_global="true"/>
<port type="sram" prefix="MODE" lib_name="MODE" size="1" mode_select="true" circuit_model_name="CCFF" default_value="0"/>
</circuit_model>
This example shows:
- A multi-mode flip-flop which is defined in a Verilog netlist ``frac_ff.v`` and a SPICE netlist ``frac_ff.sp``
- The flip-flop has a ``reset`` pin which can be either active-low or active-high, depending on the mode selection pin ``MODE``.
- The mode-selection bit will be generated by a configurable memory outside the flip-flop, which will be implemented by a circuit model ``CCFF`` defined by users (see an example in :ref:`circuit_model_ccff_example`).
- The flip-flop port names defined differently in standard cell library and VPR architecture. The ``lib_name`` capture the port name defined in standard cells, while ``prefix`` capture the port name defined in ``pb_type`` of VPR architecture file
Configuration Chain Flip-Flop
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
.. note:: OpenFPGA does not auto-generate any netlist for configuration chain flip-flops. Users should define the HDL modeling in external netlists and ensure consistency to physical designs.
Template
````````
.. code-block:: xml
<circuit_model type="ccff" name="<string>" prefix="<string>" spice_netlist="<string>" verilog_netlist="<string>"/>
<design_technology type="cmos"/>
<input_buffer exist="<string>" circuit_model_name="<string>"/>
<output_buffer exist="<string>" circuit_model_name="<string>"/>
<port type="input" prefix="<string>" size="<int>"/>
<port type="output" prefix="<string>" size="<int>"/>
<port type="clock" prefix="<string>" size="<int>"/>
</circuit_model>
.. note:: The circuit designs of configurable memory elements are highly dependent on the technology node and well optimized by engineers. Therefore, FPGA-Verilog/SPICE requires users to provide their customized FF Verilog/SPICE/Verilog netlists. A sample Verilog/SPICE netlist of FF can be found in the directory SpiceNetlists in the released package.
The information of input and output buffer should be clearly specified according to the customized SPICE netlist! The existence of input/output buffers will influence the decision in creating SPICE testbenches, which may leads to larger errors in power analysis.
.. note:: FPGA-Verilog/SPICE currently support only one clock domain for any configuration protocols in the FPGA. Therefore there should be only one clock port to be defined and the size of the clock port should be 1.
.. note:: A flip-flop should at least have three types of ports, ``input``, ``output`` and ``clock``.
.. note:: If the user provides a customized Verilog/SPICE netlist, the bandwidth of ports should be defined to the same as the Verilog/SPICE netlist.
.. note:: In a valid FPGA architecture, users should provide at least either a ``ccff`` or ``sram`` circuit model, so that the configurations can loaded to core logic.
.. _circuit_model_ccff_example:
Regular Configuration-chain Flip-flop
@ -1147,6 +1212,8 @@ The code describing this FF is:
Hard Logics
~~~~~~~~~~~
.. note:: OpenFPGA does not auto-generate any netlist for the hard logics. Users should define the HDL modeling in external netlists and ensure consistency to physical designs.
Template
````````
@ -1175,6 +1242,13 @@ Template
Full Adder
``````````
.. figure:: ./figures/full_adder_1bit_circuit_model.svg
:scale: 200%
:alt: An example of a 1-bit full adder
An example of a 1-bit full adder.
The code describing the 1-bit full adder is:
.. code-block:: xml
@ -1189,6 +1263,134 @@ Full Adder
<port type="output" prefix="sumout" size="1"/>
</circuit_model>
This example shows:
- A 1-bit full adder which is defined in a Verilog netlist ``adder.v`` and a SPICE netlist ``adder.sp``
- The adder has three 1-bit inputs, i.e., ``a``, ``b`` and ``cin``, and two 2-bit outputs, i.e., ``cout``, ``sumout``.
.. _circuit_model_single_mode_mult8x8_example:
Multiplier
``````````
.. figure:: ./figures/single_mode_mult8x8_circuit_model.svg
:scale: 200%
:alt: An example of a 8-bit multiplier.
An example of a 8-bit multiplier.
The code describing the multiplier is:
.. code-block:: xml
<circuit_model type="hard_logic" name="mult8x8" prefix="mult8x8" spice_netlist="dsp.sp" verilog_netlist="dsp.v">
<design_technology type="cmos"/>
<input_buffer exist="true" circuit_model_name="inv1x"/>
<output_buffer exist="true" circuit_model_name="inv1x"/>
<port type="input" prefix="a" size="8"/>
<port type="input" prefix="b" size="8"/>
<port type="output" prefix="out" size="16"/>
</circuit_model>
This example shows:
- A 8-bit multiplier which is defined in a Verilog netlist ``dsp.v`` and a SPICE netlist ``dsp.sp``
.. _circuit_model_multi_mode_mult8x8_example:
Multi-mode Multiplier
`````````````````````
.. figure:: ./figures/multi_mode_mult8x8_circuit_model.svg
:scale: 200%
:alt: An example of a 8-bit multiplier which can operating in two modes: (1) dual 4-bit multipliers; and (2) 8-bit multiplier
An example of a 8-bit multiplier which can operating in two modes: (1) dual 4-bit multipliers; and (2) 8-bit multiplier
The code describing the multiplier is:
.. code-block:: xml
<circuit_model type="hard_logic" name="frac_mult8x8" prefix="frac_mult8x8" spice_netlist="dsp.sp" verilog_netlist="dsp.v">
<design_technology type="cmos"/>
<input_buffer exist="true" circuit_model_name="inv1x"/>
<output_buffer exist="true" circuit_model_name="inv1x"/>
<port type="input" prefix="a" size="8"/>
<port type="input" prefix="b" size="8"/>
<port type="output" prefix="out" size="16"/>
<port type="sram" prefix="mode" size="1" mode_select="true" circuit_model_name="CCFF" default_value="0"/>
</circuit_model>
This example shows:
- A multi-mode 8-bit multiplier which is defined in a Verilog netlist ``dsp.v`` and a SPICE netlist ``dsp.sp``
- The multi-mode multiplier can operating in two modes: (1) dual 4-bit multipliers; and (2) 8-bit multiplier
- The mode-selection bit will be generated by a configurable memory outside the flip-flop, which will be implemented by a circuit model ``CCFF`` defined by users (see an example in :ref:`circuit_model_ccff_example`).
.. _circuit_model_single_mode_dpram_example:
Dual Port Block RAM
```````````````````
.. figure:: ./figures/single_mode_dpram128x8_memory_circuit_model.svg
:scale: 150%
:alt: An example of a dual port block RAM with 128 addresses and 8-bit data width.
An example of a dual port block RAM with 128 addresses and 8-bit data width.
The code describing this block RAM is:
.. code-block:: xml
<circuit_model type="hard_logic" name="dpram_128x8" prefix="dpram_128x8" spice_netlist="dpram.sp" verilog_netlist="dpram.v">
<design_technology type="cmos"/>
<input_buffer exist="true" circuit_model_name="inv1x"/>
<output_buffer exist="true" circuit_model_name="inv1x"/>
<port type="input" prefix="waddr" size="7"/>
<port type="input" prefix="raddr" size="7"/>
<port type="input" prefix="data_in" size="8"/>
<port type="input" prefix="wen" size="1"/>
<port type="input" prefix="ren" size="1"/>
<port type="output" prefix="data_out" size="8"/>
<port type="clock" prefix="clock" size="1" is_global="true" default_val="0"/>
</circuit_model>
This example shows:
- A 128x8 dual port RAM which is defined in a Verilog netlist ``dpram.v`` and a SPICE netlist ``dpram.sp``
- The clock port of the RAM is controlled by a global signal (see details about global signal definition in :ref:`annotate_vpr_arch_physical_tile_annotation`).
.. _circuit_model_multi_mode_dpram_example:
Multi-mode Dual Port Block RAM
``````````````````````````````
.. figure:: ./figures/multi_mode_dpram128x8_memory_circuit_model.svg
:scale: 150%
:alt: An example of a multi-mode dual port block RAM with 128 addresses and 8-bit data width.
An example of a dual port block RAM which can operate in two modes: 128x8 and 256x4.
The code describing this block RAM is:
.. code-block:: xml
<circuit_model type="hard_logic" name="frac_dpram_128x8" prefix="frac_dpram_128x8" spice_netlist="frac_dpram.sp" verilog_netlist="frac_dpram.v">
<design_technology type="cmos"/>
<input_buffer exist="true" circuit_model_name="inv1x"/>
<output_buffer exist="true" circuit_model_name="inv1x"/>
<port type="input" prefix="waddr" size="8"/>
<port type="input" prefix="raddr" size="8"/>
<port type="input" prefix="data_in" size="8"/>
<port type="input" prefix="wen" size="1"/>
<port type="input" prefix="ren" size="1"/>
<port type="output" prefix="data_out" size="8"/>
<port type="clock" prefix="clock" size="1" is_global="true" default_val="0"/>
<port type="sram" prefix="mode" size="1" mode_select="true" circuit_model_name="CCFF" default_value="0"/>
</circuit_model>
This example shows:
- A fracturable dual port RAM which is defined in a Verilog netlist ``frac_dpram.v`` and a SPICE netlist ``frac_dpram.sp``
- The dual port RAM can operate in two modes: (1) 128 addresses with 8-bit data width; (2) 256 addresses with 4-bit data width
- The clock port of the RAM is controlled by a global signal (see details about global signal definition in :ref:`annotate_vpr_arch_physical_tile_annotation`).
- The mode-selection bit will be generated by a configurable memory outside the flip-flop, which will be implemented by a circuit model ``CCFF`` defined by users (see an example in :ref:`circuit_model_ccff_example`).
Routing Wire Segments
~~~~~~~~~~~~~~~~~~~~~
@ -1255,6 +1457,8 @@ This example shows
I/O pads
~~~~~~~~
.. note:: OpenFPGA does not auto-generate any netlist for I/O cells. Users should define the HDL modeling in external netlists and ensure consistency to physical designs.
Template
````````

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docs/source/overview/tech_highlights.rst
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@ -42,19 +42,21 @@ Supported Circuit Designs
+-----------------+--------------+-----------+-----------------------------------------------------+
| | Configurable | No | Yes | - :ref:`circuit_model_config_latch_example` |
| | Memory | | | - :ref:`circuit_model_sram_blwl_example` |
| | | | - :ref:`circuit_model_dff_example` |
| | | | - :ref:`circuit_model_ccff_example` |
| | | | - :ref:`circuit_model_ccff_enable_example` |
| | | | - :ref:`circuit_model_ccff_scanable_example` |
+-----------------+--------------+-----------+-----------------------------------------------------+
| Block RAM | No | Yes | - **Any size** |
| | | | - Single-port |
| | | | - Dual-port |
| | | | - Fracturable |
| Data Memory | No | Yes | - **Any size** |
| | | | - :ref:`circuit_model_dff_example` |
| | | | - :ref:`circuit_model_multi_mode_ff_example` |
| | | | - Single-port Block RAM |
| | | | - :ref:`circuit_model_single_mode_dpram_example` |
| | | | - :ref:`circuit_model_multi_mode_dpram_example` |
+-----------------+--------------+-----------+-----------------------------------------------------+
| | Arithmetic | No | Yes | - **Any size** |
| | Units | | | - Multiplier |
| | | | - :ref:`circuit_model_full_adder_example` |
| | Units | | | - :ref:`circuit_model_full_adder_example` |
| | | | - :ref:`circuit_model_single_mode_mult8x8_example` |
| | | | - :ref:`circuit_model_multi_mode_mult8x8_example` |
+-----------------+--------------+-----------+-----------------------------------------------------+
| I/O | No | Yes | - :ref:`circuit_model_gpio_example` |
| | | | - Bi-directional buffer |

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@ -24,7 +24,7 @@ In general, please follow the steps to compile
.. note:: cmake3.12+ is recommended to compile OpenFPGA with GUI
.. note:: Recommand to use ``make -j`` to accelerate the compilation
.. note:: Recommand to use ``make -j<int>`` to accelerate the compilation, where ``<int>`` denotes the number of cores to be used in compilation.
.. note:: VPR's GUI requires gtk-3, and can be enabled with ``cmake .. -DVPR_USE_EZGL=on``