Commit Graph

345 Commits

Author SHA1 Message Date
tangxifan 3d4f1505b6 [core] code format 2023-10-20 22:02:56 -07:00
tangxifan 66c3226fad [core] now follow module unique index when naming grouped configuration memories 2023-10-20 22:01:19 -07:00
tangxifan e4b204f2e4 [core] code format 2023-10-20 21:14:07 -07:00
tangxifan 76a4b8a82b [core] remove the prefix of grouped memory blocks 2023-10-20 21:13:37 -07:00
tangxifan c4bce834e4 [core] code format 2023-09-25 22:34:39 -07:00
tangxifan 5aa206e616 [core] fixed some bugs 2023-09-25 22:27:24 -07:00
tangxifan 1624dc9764 [core] code format 2023-09-25 21:13:50 -07:00
tangxifan 76f446caec [core] fixed a bug 2023-09-25 21:13:11 -07:00
tangxifan dbd466cdec [core] now support tile port merge 2023-09-25 18:16:24 -07:00
tangxifan 3adf81046a [core] code format 2023-09-25 17:22:26 -07:00
tangxifan 5e269e8bc4 [core] support port merging at grid modules 2023-09-25 17:21:58 -07:00
tangxifan edb0e687f1 [core] code format 2023-09-23 12:15:53 -07:00
tangxifan 11de8965a8 [core] fixed some bugs 2023-09-23 12:15:31 -07:00
tangxifan 860cfd53c6 [core] fixed critical bugs in renaming modules 2023-09-23 11:51:31 -07:00
tangxifan ca3617a029 [core] code format 2023-09-20 20:37:27 -07:00
tangxifan 1ef38b6a64 [core] now name the port of tiles using the relative index of the subblocks in each tile, rather than the unique index of subblocks across a complete fabric. This avoids all the conflicts in naming 2023-09-20 20:34:21 -07:00
tangxifan c105b56bf0 [core] code format 2023-09-18 23:31:27 -07:00
tangxifan 43fd08a3fe [core] fixed a bug 2023-09-18 23:31:09 -07:00
tangxifan 1daabb990e [core] code format 2023-09-18 15:35:13 -07:00
tangxifan 110301a2e4 [core] now tile port naming can follow index 2023-09-18 15:34:40 -07:00
tangxifan ef97127c63 [core] fixed some bugs in testbenches when renaming top modules 2023-09-17 22:34:00 -07:00
tangxifan d5152dc16d [core] fixed a bug on the hierarchy writer 2023-09-17 17:42:25 -07:00
tangxifan 37573abc22 [core] code format 2023-09-15 23:32:40 -07:00
tangxifan c85c64eb5a [core] syntax 2023-09-15 23:30:34 -07:00
tangxifan bc407e5d69 [core] code complete for rename modules 2023-09-15 23:22:31 -07:00
tangxifan 2a45b49890 [core] developing renaming commands. options and functions 2023-09-15 19:15:18 -07:00
tangxifan 717906ea17 [core] code format 2023-08-25 15:13:39 -07:00
tangxifan 89b392a51f [core] adapt changes in is_sb_exist() 2023-08-25 15:13:00 -07:00
tangxifan 66cc375996 [core] remove debugging messages 2023-08-18 22:08:47 -07:00
tangxifan 19d4d9a16d [core] code format 2023-08-18 21:05:26 -07:00
tangxifan fc523bed32 [core] fixed some bugs in spotting the correct pin index of given subtiles 2023-08-18 21:04:37 -07:00
tangxifan 3d8f76269a [core] fixed a bug when io is in the center of 3x3 fabric 2023-08-18 12:42:15 -07:00
tangxifan e9fd22790d [core] fixed a bug where pass thru cb blocks are not connected in tiles 2023-08-17 15:26:32 -07:00
tangxifan 94d80a9b7c [core] code format 2023-08-08 16:28:56 -07:00
tangxifan 867da98d3f [core] update to use latest api from vpr upstream 2023-08-08 16:28:19 -07:00
tangxifan 4d37421735 [core] fixed a bug on loading subkey to support fabric keys 2023-08-07 10:40:22 -07:00
tangxifan 18acb39fad [core] fixed a bug where heterogeneous fabric may fail 2023-08-06 22:12:32 -07:00
tangxifan a1f8b3c441 [core] fixed a bug on bitstream generator on supporting group_config_block 2023-08-05 21:58:03 -07:00
tangxifan 68f07d6fc9 [core] code format 2023-08-05 20:53:58 -07:00
tangxifan f4d7ad2bd1 [core] trying to fix the bug on instance naming so that bitstream generation can work 2023-08-05 13:38:51 -07:00
tangxifan 9a23dc7bff [core] fixed some bugs which causes architecture bitstream generation failed when supporting group_config_block 2023-08-04 21:20:21 -07:00
tangxifan 7d8d686f74 [core] add status codes to build grid modules 2023-08-04 16:52:43 -07:00
tangxifan bb9cf6dbcb [core] fixed a critical bug which causes undriven nets on config bus in group config block 2023-08-04 16:45:15 -07:00
tangxifan 64c0839e30 [core] now verilog writer supports memory group modules 2023-08-04 16:11:33 -07:00
tangxifan a0f81a5bf2 [core] now verilog generator can output feedthrough memory module to files 2023-08-04 13:34:38 -07:00
tangxifan 5bc8925c3a [core] fixed multiple bugs on fabric generator on supporting group_config_block 2023-08-04 12:36:59 -07:00
tangxifan 3c2518ac70 [core] adding debugging message when verbose is enabled 2023-08-04 11:20:05 -07:00
tangxifan 99bda2e5b0 [core] debugging 2023-08-03 22:50:14 -07:00
tangxifan 2aeeb0cacf [core] fixed a bug which causes reg tests failed 2023-08-03 22:13:27 -07:00
tangxifan d3895c3dc0 [core] code format 2023-08-03 17:34:25 -07:00