ganeshgore
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5828e51144
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Merge pull request #237 from lnis-uofu/dev
Move quicklogic regresssion tests to a dedicated CI run
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2021-02-16 11:45:33 -07:00 |
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ganeshgore
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d4ab913baa
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Merge pull request #236 from lnis-uofu/tpagarani_dev
Tpagarani dev
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2021-02-16 11:04:46 -07:00 |
tangxifan
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62bf0d0c5d
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[Test] Move quicklogic regresssion tests to a dedicated CI run
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2021-02-16 11:00:31 -07:00 |
Tarachand Pagarani
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426b6449d8
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change the test to turn off power analysis
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2021-02-15 02:45:38 -08:00 |
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Tarachand Pagarani
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3a587f663a
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copy yosys output file in case power analysis setting is off
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2021-02-15 02:36:02 -08:00 |
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ganeshgore
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45e8baf98f
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Merge pull request #235 from lnis-uofu/dev
Reorganize tutorial documentation
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2021-02-11 16:33:58 -07:00 |
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tangxifan
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2eaec13351
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[Doc] Reorganize tutorial documentation by grouping compilation guidelines, shell setup and tool guide into a section
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2021-02-11 14:09:20 -07:00 |
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tangxifan
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702bd3bbd5
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Merge pull request #231 from lnis-uofu/dev
Extended LUT Support: Now accept external LUT netlists with embedded custom logic
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2021-02-11 13:57:17 -07:00 |
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tangxifan
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184788880c
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Merge pull request #224 from lnis-uofu/gg_docs
[Docs] Added documentation for docker based run and shell shortcuts documentation
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2021-02-11 09:26:29 -07:00 |
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tangxifan
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c895422014
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Merge pull request #234 from lnis-uofu/bump_yosys
Bumping up latest checkins to yosys sub-module, related to adder_lut4…
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2021-02-11 09:24:49 -07:00 |
Lalit Sharma
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c495382416
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Bumping up latest checkins to yosys sub-module, related to adder_lut4 inference
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2021-02-10 22:22:58 -08:00 |
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tangxifan
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e683e00032
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[HDL] Add disclaimer for the frac_lut4_arith HDL codes
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2021-02-10 14:50:11 -07:00 |
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tangxifan
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1c4dc9f74b
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[Doc] Update documentation about the super LUT feature
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2021-02-10 11:49:59 -07:00 |
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tangxifan
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af4cc117fb
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[Tool] bug fix in spypad lut
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2021-02-09 22:53:18 -07:00 |
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tangxifan
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9b86f3bb85
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Merge branch 'master' into dev
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2021-02-09 22:40:45 -07:00 |
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tangxifan
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b2984b46ee
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[Tool] Upgrade libopenfpga to support superLUT-related XML syntax
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2021-02-09 21:15:57 -07:00 |
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tangxifan
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be24c904af
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[Test] Add superLUT test case to CI
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2021-02-09 21:15:21 -07:00 |
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tangxifan
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22e675148e
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[HDL] Add HDL codes for a super LUT with embedded carry logic
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2021-02-09 21:13:22 -07:00 |
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tangxifan
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b81b74aa7c
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[Arch] Patch architecture to support superLUT-related XML syntax
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2021-02-09 20:23:32 -07:00 |
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tangxifan
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6a0f4f354f
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[Tool] Support superLUT circuit model in core engine
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2021-02-09 20:23:05 -07:00 |
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tangxifan
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7dcc14d73f
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[Arch] Bug fix in the example arch with super LUT
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2021-02-09 15:52:22 -07:00 |
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tangxifan
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3ae501a5ea
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[Test] Update test case to use dedicated eblif file
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2021-02-09 15:51:57 -07:00 |
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tangxifan
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1712ee4edb
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[Benchmark] Add a dedicated eblif to test the frac lut4 arith architecture
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2021-02-09 15:41:21 -07:00 |
Nachiket Kapre
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4c7f4bd82f
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ahoy nice
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2021-02-09 17:38:19 -05:00 |
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tangxifan
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2b51b36dd6
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[Test] Now use the super LUT arch in the test case
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2021-02-09 15:27:44 -07:00 |
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tangxifan
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56284059de
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[Test] Add a test case for a super LUT
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2021-02-09 15:25:32 -07:00 |
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tangxifan
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304b26c97f
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[Arch] Add example architectures for superLUT circuit model
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2021-02-09 15:11:12 -07:00 |
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Nachiket Kapre
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71c76df063
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default to ns for time unit -- synopsys dc whines
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2021-02-09 17:08:38 -05:00 |
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Nachiket Kapre
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6bb2e29f17
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default to ns for time unit -- synopsys dc whines
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2021-02-09 17:04:52 -05:00 |
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Nachiket Kapre
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87c69460df
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what is going on
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2021-02-09 11:33:08 -05:00 |
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Nachiket Kapre
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cc74c6268a
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trying fix chan width
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2021-02-09 11:28:19 -05:00 |
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Nachiket Kapre
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95fe4d7dae
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adding dff synth
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2021-02-09 10:34:54 -05:00 |
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Nachiket Kapre
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b14b5f975d
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adding sweep for W
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2021-02-09 08:48:25 -05:00 |
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Nachiket Kapre
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d7967da328
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bugfix in alt
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2021-02-08 23:04:00 -05:00 |
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Nachiket Kapre
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485708423c
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no need for dff*, but need tap_buf4
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2021-02-08 23:00:13 -05:00 |
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Nachiket Kapre
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cf154d8bb9
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no need for dff*, but need tap_buf4
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2021-02-08 22:29:55 -05:00 |
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Nachiket Kapre
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e14c0bf0c4
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no need for dff*, but need tap_buf4
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2021-02-08 22:28:42 -05:00 |
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Nachiket Kapre
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45437fbc46
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no need for dff*, but need tap_buf4
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2021-02-08 22:27:57 -05:00 |
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Nachiket Kapre
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853bf8af43
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typos fixed;
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2021-02-08 22:03:14 -05:00 |
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Nachiket Kapre
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d040ba569c
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merge for consideration;
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2021-02-08 21:29:34 -05:00 |
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Nachiket Kapre
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94f858fcde
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merge for consideration;
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2021-02-08 21:27:01 -05:00 |
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Nachiket Kapre
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0c6d27cf7e
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merge for consideration;
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2021-02-08 21:26:48 -05:00 |
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Nachiket Kapre
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b4185f7e8c
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Merge branch 'master' of github.com:lnis-uofu/OpenFPGA
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2021-02-08 21:11:30 -05:00 |
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Nachiket Kapre
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2344cdcabc
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merge
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2021-02-08 21:11:28 -05:00 |
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Ganesh Gore
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c2b68606c9
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[Bugfix] Added shell globstar
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2021-02-08 14:07:01 -07:00 |
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tangxifan
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1ce94040da
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Merge pull request #221 from lnis-uofu/flow_dev
[Flow] Support multi-user environment for running task
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2021-02-08 12:43:57 -07:00 |
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Ganesh Gore
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6761df6d9d
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[Bugfix] Reverted setting OPENFPGA_PATH
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2021-02-08 12:36:50 -07:00 |
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Ganesh Gore
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7b8fd55916
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[Bugfix] Task name in regression flow
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2021-02-08 12:06:36 -07:00 |
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Ganesh Gore
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12e4fa07a2
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[bugfix] OPENFPGA_PATH location
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2021-02-08 11:57:15 -07:00 |
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Ganesh Gore
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9c5e1b1478
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[CI] Updated test
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2021-02-08 11:11:00 -07:00 |